293 lines
6.1 KiB
C
293 lines
6.1 KiB
C
/*
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief Boot informations provided by the Tegra SoC and it's BootROM. All
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* accessor functions are a header only implementations, as they are meant to
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* be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
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*/
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#ifndef __TEGRA_LOWLEVEL_H
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#define __TEGRA_LOWLEVEL_H
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#include <linux/compiler.h>
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#include <sizes.h>
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#include <io.h>
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#include <mach/iomap.h>
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/* Bootinfotable */
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#define NV_BIT_BCTSIZE 0x38 /* size of the BCT in IRAM */
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#define NV_BIT_BCTPTR 0x3C /* location of the BCT in IRAM */
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/* ODM data */
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#define BCT_ODMDATA_OFFSET 12 /* offset from the _end_ of the BCT */
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#define T20_ODMDATA_RAMSIZE_SHIFT 28
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#define T20_ODMDATA_RAMSIZE_MASK (3 << T20_ODMDATA_RAMSIZE_SHIFT)
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#define T30_ODMDATA_RAMSIZE_MASK (0xf << T20_ODMDATA_RAMSIZE_SHIFT)
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#define T20_ODMDATA_UARTTYPE_SHIFT 18
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#define T20_ODMDATA_UARTTYPE_MASK (3 << T20_ODMDATA_UARTTYPE_SHIFT)
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#define T20_ODMDATA_UARTID_SHIFT 15
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#define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT)
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static __always_inline
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u32 tegra_get_odmdata(void)
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{
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u32 bctsize, bctptr, odmdata;
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bctsize = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTSIZE);
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bctptr = cpu_readl(TEGRA_IRAM_BASE + NV_BIT_BCTPTR);
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odmdata = cpu_readl(bctptr + bctsize - BCT_ODMDATA_OFFSET);
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return odmdata;
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}
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/* chip ID */
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#define APB_MISC_HIDREV 0x804
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#define HIDREV_CHIPID_SHIFT 8
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#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
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enum tegra_chiptype {
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TEGRA_UNK_REV = -1,
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TEGRA20 = 0,
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TEGRA30 = 1,
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TEGRA114 = 2,
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TEGRA124 = 3,
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};
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static __always_inline
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u32 tegra_read_chipid(void)
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{
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return readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
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}
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static __always_inline
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enum tegra_chiptype tegra_get_chiptype(void)
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{
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u32 hidrev;
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hidrev = readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
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switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
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case 0x20:
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return TEGRA20;
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case 0x30:
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return TEGRA30;
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case 0x40:
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return TEGRA124;
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default:
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return TEGRA_UNK_REV;
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}
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}
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static __always_inline
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int tegra_get_num_cores(void)
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{
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switch (tegra_get_chiptype()) {
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case TEGRA20:
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return 2;
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case TEGRA30:
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case TEGRA124:
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return 4;
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default:
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return 0;
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}
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}
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/* Runtime data */
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static __always_inline
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int tegra_cpu_is_maincomplex(void)
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{
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u32 tag0;
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tag0 = readl(TEGRA_UP_TAG_BASE);
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return (tag0 & 0xff) == 0x55;
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}
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static __always_inline
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uint32_t tegra20_get_ramsize(void)
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{
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switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
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T20_ODMDATA_RAMSIZE_SHIFT) {
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case 1:
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return SZ_256M;
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default:
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case 2:
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return SZ_512M;
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case 3:
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return SZ_1G;
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}
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}
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static __always_inline
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uint32_t tegra30_get_ramsize(void)
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{
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switch ((tegra_get_odmdata() & T30_ODMDATA_RAMSIZE_MASK) >>
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T20_ODMDATA_RAMSIZE_SHIFT) {
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case 0:
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case 1:
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default:
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return SZ_256M;
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case 2:
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return SZ_512M;
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case 3:
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return SZ_512M + SZ_256M;
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case 4:
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return SZ_1G;
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case 8:
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return SZ_2G - SZ_1M;
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}
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}
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static long uart_id_to_base[] = {
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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TEGRA_UARTC_BASE,
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TEGRA_UARTD_BASE,
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TEGRA_UARTE_BASE,
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};
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static __always_inline
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long tegra20_get_debuguart_base(void)
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{
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u32 odmdata;
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int id;
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odmdata = tegra_get_odmdata();
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/*
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* Get type, we accept both "2" and "3", as they both demark a UART,
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* depending on the board type.
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*/
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if (!(((odmdata & T20_ODMDATA_UARTTYPE_MASK) >>
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T20_ODMDATA_UARTTYPE_SHIFT) & 0x2))
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return 0;
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id = (odmdata & T20_ODMDATA_UARTID_MASK) >> T20_ODMDATA_UARTID_SHIFT;
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if (id > ARRAY_SIZE(uart_id_to_base))
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return 0;
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return uart_id_to_base[id];
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}
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#define CRC_OSC_CTRL 0x050
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#define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30
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#define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
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static __always_inline
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int tegra_get_osc_clock(void)
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{
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u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
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switch ((osc_ctrl & CRC_OSC_CTRL_OSC_FREQ_MASK) >>
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CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
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case 0:
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return 13000000;
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case 1:
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return 19200000;
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case 2:
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return 12000000;
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case 3:
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return 26000000;
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default:
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return 0;
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}
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}
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static __always_inline
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int tegra_get_pllp_rate(void)
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{
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switch (tegra_get_chiptype()) {
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case TEGRA20:
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return 216000000;
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case TEGRA30:
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case TEGRA124:
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return 408000000;
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default:
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return 0;
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}
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}
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#define TIMER_CNTR_1US 0x00
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#define TIMER_USEC_CFG 0x04
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static __always_inline
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void tegra_ll_delay_setup(void)
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{
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u32 reg;
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/*
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* calibrate timer to run at 1MHz
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* TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
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* representing the divisor and bits [8:15] representing the dividend
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* each in n+1 form.
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*/
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switch (tegra_get_osc_clock()) {
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case 12000000:
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reg = 0x000b;
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break;
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case 13000000:
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reg = 0x000c;
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break;
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case 19200000:
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reg = 0x045f;
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break;
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case 26000000:
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reg = 0x0019;
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break;
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default:
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reg = 0;
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break;
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}
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writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG);
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}
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static __always_inline
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void tegra_ll_delay_usec(int delay)
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{
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int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay;
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while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0);
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}
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static __always_inline
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void tegra_cpu_lowlevel_setup(void)
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{
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uint32_t r;
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/* set the cpu to SVC32 mode */
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__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
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r &= ~0x1f;
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r |= 0xd3;
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__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
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arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K - 8);
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tegra_ll_delay_setup();
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}
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/* reset vector for the AVP, to be called from board reset vector */
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void tegra_avp_reset_vector(uint32_t boarddata);
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/* reset vector for the main CPU complex */
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void tegra_maincomplex_entry(void);
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#endif /* __TEGRA_LOWLEVEL_H */
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