From ae76afe1cdeb2343eb8b432718313bc6c9ce6ced Mon Sep 17 00:00:00 2001 From: Holger Hans Peter Freyther Date: Mon, 16 Jul 2012 23:03:13 +0200 Subject: [PATCH] Pre v1.0: Change the interface to match firmware v2.1 release The RevB hardware is not supported with newer firmware releases, adjust the header file of the pre v1.0 header files to be usable with the latest osmo-bts code. --- api/superfemto.h | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/api/superfemto.h b/api/superfemto.h index 46041f4..6c3bb8e 100644 --- a/api/superfemto.h +++ b/api/superfemto.h @@ -57,6 +57,28 @@ typedef enum SuperFemto_PrimId_t SuperFemto_PrimId_NUM } SuperFemto_PrimId_t; +/**************************************************************************** + * Enum : SuperFemto_ClkSrcId_t + ************************************************************************//** + * + * Clock source intifiers. + * + * @ingroup superfemto_api + * + ****************************************************************************/ +typedef enum SuperFemto_ClkSrcId_t +{ + // RF Diagnostic Primitives + SuperFemto_ClkSrcId_None = 0, ///< None + SuperFemto_ClkSrcId_Ocxo, ///< Optional on-board OCXO + SuperFemto_ClkSrcId_Tcxo, ///< Optional on-board TCXO + SuperFemto_ClkSrcId_External, ///< Multi-Trx external clock + SuperFemto_ClkSrcId_GpsPps, ///< GPS PPS + SuperFemto_ClkSrcId_Trx, ///< TRX clock + SuperFemto_ClkSrcId_Rx, ///< RX clock + SuperFemto_ClkSrcId_NetList, ///< Network listening + SuperFemto_ClkSrcId_Edge, ///< Debug edge connector clock, +} SuperFemto_ClkSrcId_t; /**************************************************************************** * Types * @@ -71,6 +93,7 @@ typedef enum SuperFemto_PrimId_t * @ingroup superfemto_api_prim_sys * ****************************************************************************/ +#define FEMTOBTS_NO_BOARD_VERSION typedef struct SuperFemto_SystemInfoCnf { SuperFemto_Status_t status; ///< Status @@ -148,14 +171,14 @@ typedef struct SuperFemto_ActivateRfReq struct { int iClkCor; ///< Clock correction value in PPB. - uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX) + uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX) } rfTrx; // RX RF clock options struct { int iClkCor; ///< Clock calibration value in PPB. - uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved) + uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved) } rfRx; } SuperFemto_ActivateRfReq_t; @@ -281,19 +304,19 @@ typedef struct SuperFemto_RfClockSetupReq struct { int iClkCor; ///< Clock correction value in PPB. - uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX) + uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX) } rfTrx; // RX RF clock options struct { int iClkCor; ///< Clock calibration value in PPB. - uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved) + uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved) } rfRx; // RF clock calibration struct { - uint8_t u8ClkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:NL) + uint8_t clkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:NL) } rfTrxClkCal; } SuperFemto_RfClockSetupReq_t;