qemu: add patch to add mips 24KEc CPU definition
This patch has been accepted upstream: http://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg05778.html (From OE-Core rev: b89bd412a69bfda262ed795e970b362ddbec6c68) Signed-off-by: André Draszik <git@andred.net> Signed-off-by: Ross Burton <ross.burton@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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@ -21,6 +21,7 @@ SRC_URI = "\
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file://wacom.patch \
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file://add-ptest-in-makefile.patch \
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file://run-ptest \
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file://0001-target-mips-add-24KEc-CPU-definition.patch \
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"
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SRC_URI_append_class-native = "\
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@ -0,0 +1,54 @@
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From 926bc194f918d46bd93557b15da8153b6a94a1d5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Andr=C3=A9=20Draszik?= <git@andred.net>
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Date: Mon, 25 Jul 2016 23:58:22 +0100
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Subject: [PATCH] target-mips: add 24KEc CPU definition
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Define a new CPU definition supporting 24KEc cores, similar to
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the existing 24Kc, but with added support for DSP instructions
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and MIPS16e (and without FPU).
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Signed-off-by: André Draszik <git@andred.net>
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---
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Upstream-Status: Submitted [http://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg05778.html]
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target-mips/translate_init.c | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
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index 39ed5c4..6ae23e4 100644
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--- a/target-mips/translate_init.c
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+++ b/target-mips/translate_init.c
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@@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] =
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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+ .name = "24KEc",
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+ .CP0_PRid = 0x00019600,
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+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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+ (MMU_TYPE_R4000 << CP0C0_MT),
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+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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+ (1 << CP0C1_CA),
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+ .CP0_Config2 = MIPS_CONFIG2,
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+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
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+ .CP0_LLAddr_rw_bitmask = 0,
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+ .CP0_LLAddr_shift = 4,
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+ .SYNCI_Step = 32,
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+ .CCRes = 2,
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+ /* we have a DSP, but no FPU */
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+ .CP0_Status_rw_bitmask = 0x1378FF1F,
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+ .SEGBITS = 32,
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+ .PABITS = 32,
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+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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+ .mmu_type = MMU_TYPE_R4000,
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+ },
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+ {
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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--
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2.8.1
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