273 lines
10 KiB
Diff
273 lines
10 KiB
Diff
Upstream-Status: Backport
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https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=2c62985659da21a3fe16062d211a7158f79ad2e9
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Signed-off-By: Armin Kuster <akuster@mvista.com>
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Index: git/bfd/archures.c
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===================================================================
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--- git.orig/bfd/archures.c
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+++ git/bfd/archures.c
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@@ -179,6 +179,7 @@ DESCRIPTION
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.#define bfd_mach_mips_octeon 6501
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.#define bfd_mach_mips_octeonp 6601
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.#define bfd_mach_mips_octeon2 6502
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+.#define bfd_mach_mips_octeon3 6503
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.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
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.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
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.#define bfd_mach_mipsisa32 32
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Index: git/bfd/bfd-in2.h
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===================================================================
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--- git.orig/bfd/bfd-in2.h
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+++ git/bfd/bfd-in2.h
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@@ -1969,6 +1969,7 @@ enum bfd_architecture
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#define bfd_mach_mips_octeon 6501
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#define bfd_mach_mips_octeonp 6601
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#define bfd_mach_mips_octeon2 6502
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+#define bfd_mach_mips_octeon3 6503
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#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
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#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
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#define bfd_mach_mipsisa32 32
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Index: git/bfd/cpu-mips.c
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===================================================================
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--- git.orig/bfd/cpu-mips.c
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+++ git/bfd/cpu-mips.c
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@@ -102,6 +102,7 @@ enum
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I_mipsocteon,
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I_mipsocteonp,
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I_mipsocteon2,
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+ I_mipsocteon3,
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I_xlr,
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I_micromips,
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I_xlp
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@@ -153,6 +154,7 @@ static const bfd_arch_info_type arch_inf
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N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
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N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
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N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
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+ N (64, 64, bfd_mach_mips_octeon3,"mips:octeon3", FALSE, NN(I_mipsocteon3)),
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N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
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N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
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N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
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Index: git/bfd/elfxx-mips.c
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===================================================================
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--- git.orig/bfd/elfxx-mips.c
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+++ git/bfd/elfxx-mips.c
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@@ -6604,6 +6604,9 @@ _bfd_elf_mips_mach (flagword flags)
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case E_MIPS_MACH_LS3A:
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return bfd_mach_mips_loongson_3a;
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+ case E_MIPS_MACH_OCTEON3:
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+ return bfd_mach_mips_octeon3;
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+
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case E_MIPS_MACH_OCTEON2:
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return bfd_mach_mips_octeon2;
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@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
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val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
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break;
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+ case bfd_mach_mips_octeon3:
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+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON3;
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+ break;
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+
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case bfd_mach_mips_xlr:
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val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
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break;
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@@ -14773,6 +14780,7 @@ struct mips_mach_extension
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static const struct mips_mach_extension mips_mach_extensions[] =
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{
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/* MIPS64r2 extensions. */
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+ { bfd_mach_mips_octeon3, bfd_mach_mips_octeon2 },
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{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
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{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
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{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
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Index: git/gas/config/tc-mips.c
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===================================================================
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--- git.orig/gas/config/tc-mips.c
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+++ git/gas/config/tc-mips.c
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@@ -306,7 +306,7 @@ static unsigned int file_ase_explicit;
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unsigned long mips_gprmask;
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unsigned long mips_cprmask[4];
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-/* True if any MIPS16 code was produced. */
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+/* 2True if any MIPS16 code was produced. */
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static int file_ase_mips16;
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#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
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@@ -510,7 +510,8 @@ static int mips_32bitmode = 0;
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#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
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/* True if CPU is in the Octeon family */
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-#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
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+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
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+ || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
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/* True if CPU has seq/sne and seqi/snei instructions. */
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#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
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@@ -18677,6 +18678,7 @@ static const struct mips_cpu_info mips_c
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{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
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{ "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
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{ "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
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+ { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R2, CPU_OCTEON3 },
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/* RMI Xlr */
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{ "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
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Index: git/gas/doc/c-mips.texi
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===================================================================
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--- git.orig/gas/doc/c-mips.texi
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+++ git/gas/doc/c-mips.texi
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@@ -382,6 +382,7 @@ loongson3a,
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octeon,
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octeon+,
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octeon2,
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+octeon3,
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xlr,
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xlp
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@end quotation
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Index: git/gas/testsuite/gas/mips/mips.exp
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===================================================================
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--- git.orig/gas/testsuite/gas/mips/mips.exp
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+++ git/gas/testsuite/gas/mips/mips.exp
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@@ -1102,6 +1102,7 @@ if { [istarget mips*-*-vxworks*] } {
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run_list_test_arches "octeon-ill" [mips_arch_list_matching octeon]
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run_dump_test_arches "octeon-pref" [mips_arch_list_matching octeon]
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run_dump_test_arches "octeon2" [mips_arch_list_matching octeon2]
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+ run_dump_test_arches "octeon3" [mips_arch_list_matching octeon3]
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run_dump_test "smartmips"
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run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2 \
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Index: git/gas/testsuite/gas/mips/octeon3.d
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===================================================================
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--- /dev/null
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+++ git/gas/testsuite/gas/mips/octeon3.d
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@@ -0,0 +1,20 @@
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+#objdump: -d -r --show-raw-insn
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+#name: MIPS octeon3 instructions
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+
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+.*: +file format .*mips.*
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+
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+Disassembly of section .text:
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+
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+[0-9a-f]+ <foo>:
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+.*: 71ec0008 mtm0 t3,t0
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+.*: 71a40008 mtm0 t1,a0
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+.*: 7083000c mtm1 a0,v1
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+.*: 70e1000c mtm1 a3,at
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+.*: 7022000d mtm2 at,v0
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+.*: 7083000c mtm1 a0,v1
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+.*: 70a20009 mtp0 a1,v0
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+.*: 70c40009 mtp0 a2,a0
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+.*: 7083000a mtp1 a0,v1
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+.*: 70e1000a mtp1 a3,at
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+.*: 7022000b mtp2 at,v0
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+.*: 7083000a mtp1 a0,v1
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Index: git/gas/testsuite/gas/mips/octeon3.s
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===================================================================
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--- /dev/null
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+++ git/gas/testsuite/gas/mips/octeon3.s
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@@ -0,0 +1,22 @@
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++ .text
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+ .set noreorder
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+ .set noat
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+
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+foo:
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+ mtm0 $15,$12
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+ mtm0 $13,$4
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+
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+ mtm1 $4,$3
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+ mtm1 $7,$1
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+
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+ mtm2 $1,$2
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+ mtm1 $4,$3
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+
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+ mtp0 $5,$2
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+ mtp0 $6,$4
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+
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+ mtp1 $4,$3
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+ mtp1 $7,$1
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+
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+ mtp2 $1,$2
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+ mtp1 $4,$3
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Index: git/include/opcode/mips.h
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===================================================================
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--- git.orig/include/opcode/mips.h
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+++ git/include/opcode/mips.h
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@@ -1196,6 +1196,7 @@ static const unsigned int mips_isa_table
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#define INSN_OCTEON 0x00000800
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#define INSN_OCTEONP 0x00000200
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#define INSN_OCTEON2 0x00000100
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+#define INSN_OCTEON3 0x00000040
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/* MIPS R5900 instruction */
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#define INSN_5900 0x00004000
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@@ -1325,6 +1326,7 @@ static const unsigned int mips_isa_table
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#define CPU_OCTEON 6501
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#define CPU_OCTEONP 6601
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#define CPU_OCTEON2 6502
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+#define CPU_OCTEON3 6503
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#define CPU_XLR 887682 /* decimal 'XLR' */
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#define CPU_XLP 887680 /* decimal 'XLP' */
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@@ -1391,6 +1393,9 @@ cpu_is_member (int cpu, unsigned int mas
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case CPU_OCTEON2:
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return (mask & INSN_OCTEON2) != 0;
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+ case CPU_OCTEON3:
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+ return (mask & INSN_OCTEON3) != 0;
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+
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case CPU_XLR:
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return (mask & INSN_XLR) != 0;
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Index: git/opcodes/mips-dis.c
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===================================================================
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--- git.orig/opcodes/mips-dis.c
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+++ git/opcodes/mips-dis.c
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@@ -649,6 +649,11 @@ const struct mips_arch_choice mips_arch_
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ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
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NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
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+ { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
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+ ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
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+ mips_cp0_names_numeric,
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+ NULL, 0, mips_hwr_names_numeric },
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+
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{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
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ISA_MIPS64 | INSN_XLR, 0,
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mips_cp0_names_xlr,
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Index: git/opcodes/mips-opc.c
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===================================================================
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--- git.orig/opcodes/mips-opc.c
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+++ git/opcodes/mips-opc.c
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@@ -316,9 +316,10 @@ decode_mips_operand (const char *p)
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#define N5 (INSN_5400 | INSN_5500)
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#define N54 INSN_5400
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#define N55 INSN_5500
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-#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
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-#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
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-#define IOCT2 INSN_OCTEON2
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+#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
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+#define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
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+#define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3)
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+#define IOCT3 INSN_OCTEON3
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#define XLR INSN_XLR
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#define XLP INSN_XLP
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#define IVIRT ASE_VIRT
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@@ -1505,11 +1506,17 @@ const struct mips_opcode mips_builtin_op
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{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
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{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
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{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
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+{"mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
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{"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 },
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{"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },
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{"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },
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