132 lines
4.0 KiB
Diff
132 lines
4.0 KiB
Diff
From: Riku Voipio <riku.voipio@nokia.com>
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Access the cp15.c13 TLS registers directly with TCG ops instead of with
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a slow helper. If the the cp15 read/write was not TLS register access,
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fall back to the cp15 helper.
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This makes accessing __thread variables in linux-user when apps are compiled
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with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
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already checked in cp15_user_ok.
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While at it, make the cp15.c13 Thread ID registers available only on
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ARMv6K and newer.
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Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
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Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
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diff --git a/target-arm/helper.c b/target-arm/helper.c
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index b3aec99..27001e8 100644
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--- a/target-arm/helper.c
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+++ b/target-arm/helper.c
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@@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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{
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cpu_abort(env, "cp15 insn %08x\n", insn);
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- return 0;
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}
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/* These should probably raise undefined insn exceptions. */
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@@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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tlb_flush(env, 0);
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env->cp15.c13_context = val;
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break;
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- case 2:
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- env->cp15.c13_tls1 = val;
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- break;
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- case 3:
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- env->cp15.c13_tls2 = val;
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- break;
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- case 4:
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- env->cp15.c13_tls3 = val;
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- break;
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default:
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goto bad_reg;
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}
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@@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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return env->cp15.c13_fcse;
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case 1:
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return env->cp15.c13_context;
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- case 2:
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- return env->cp15.c13_tls1;
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- case 3:
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- return env->cp15.c13_tls2;
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- case 4:
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- return env->cp15.c13_tls3;
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default:
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goto bad_reg;
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}
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index 5cf3e06..786c329 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn)
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return 0;
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}
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+static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
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+{
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+ TCGv tmp;
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+ int cpn = (insn >> 16) & 0xf;
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+ int cpm = insn & 0xf;
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+ int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
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+
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+ if (!arm_feature(env, ARM_FEATURE_V6K))
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+ return 0;
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+
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+ if (!(cpn == 13 && cpm == 0))
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+ return 0;
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+
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+ if (insn & ARM_CP_RW_BIT) {
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+ tmp = new_tmp();
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+ switch (op) {
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+ case 2:
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+ tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
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+ break;
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+ case 3:
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+ tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
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+ break;
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+ case 4:
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+ tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
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+ break;
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+ default:
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+ dead_tmp(tmp);
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+ return 0;
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+ }
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+ store_reg(s, rd, tmp);
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+
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+ } else {
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+ tmp = load_reg(s, rd);
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+ switch (op) {
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+ case 2:
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+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
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+ break;
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+ case 3:
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+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
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+ break;
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+ case 4:
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+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
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+ break;
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+ default:
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+ return 0;
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+ }
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+ dead_tmp(tmp);
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+ }
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+ return 1;
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+}
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+
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/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
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instruction is not defined. */
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static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
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@@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
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return 0;
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}
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rd = (insn >> 12) & 0xf;
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+
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+ if (cp15_tls_load_store(env, s, insn, rd))
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+ return 0;
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+
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tmp2 = tcg_const_i32(insn);
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if (insn & ARM_CP_RW_BIT) {
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tmp = new_tmp();
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