These patches are backport from gcc mainline they fix issues where eglibc was not compilable for e5500+ due to missing vector intrinsics It obsoletes the existing e5500 patch (From OE-Core rev: b440aeeceb8c2e9f412d98793fb1dd55ff9d73f5) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
119 lines
5.9 KiB
Diff
119 lines
5.9 KiB
Diff
Upstream-Status: Backport
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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From aab806a131efe9706396692ecc67d324371e39bc Mon Sep 17 00:00:00 2001
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From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Fri, 22 Jun 2012 20:13:23 +0000
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Subject: [PATCH] 2012-06-22 Edmar Wienskoski <edmar@freescale.com>
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* config/rs6000/rs6000.md (define_attr "type"): New type popcnt.
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(popcntb<mode>2): Add attribute type popcnt.
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(popcntd<mode>2): Ditto.
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* config/rs6000/power4.md (define_insn_reservation): Add type popcnt.
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* config/rs6000/power5.md (define_insn_reservation): Ditto.
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* config/rs6000/power7.md (define_insn_reservation): Ditto.
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* config/rs6000/476.md (define_insn_reservation): Ditto.
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* config/rs6000/power6.md (define_insn_reservation): New
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reservation for popcnt instructions.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188901 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/ChangeLog | 12 ++++++++++++
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gcc/config/rs6000/476.md | 2 +-
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gcc/config/rs6000/power5.md | 2 +-
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gcc/config/rs6000/power6.md | 5 +++++
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gcc/config/rs6000/power7.md | 2 +-
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gcc/config/rs6000/rs6000.md | 10 +++++++---
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6 files changed, 27 insertions(+), 6 deletions(-)
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Index: gcc-4_7-branch/gcc/config/rs6000/476.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/476.md 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/476.md 2012-07-06 19:50:30.078779999 -0700
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@@ -71,7 +71,7 @@
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ppc476_i_pipe|ppc476_lj_pipe")
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(define_insn_reservation "ppc476-complex-integer" 1
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- (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap")
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+ (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
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(eq_attr "cpu" "ppc476"))
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"ppc476_issue,\
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ppc476_i_pipe")
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Index: gcc-4_7-branch/gcc/config/rs6000/power5.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/power5.md 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/power5.md 2012-07-06 19:50:30.078779999 -0700
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@@ -142,7 +142,7 @@
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; Integer latency is 2 cycles
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(define_insn_reservation "power5-integer" 2
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(and (eq_attr "type" "integer,insert_dword,shift,trap,\
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- var_shift_rotate,cntlz,exts,isel")
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+ var_shift_rotate,cntlz,exts,isel,popcnt")
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(eq_attr "cpu" "power5"))
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"iq_power5")
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Index: gcc-4_7-branch/gcc/config/rs6000/power6.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/power6.md 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/power6.md 2012-07-06 19:50:30.078779999 -0700
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@@ -216,6 +216,11 @@
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(eq_attr "cpu" "power6"))
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"FXU_power6")
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+(define_insn_reservation "power6-popcnt" 1
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+ (and (eq_attr "type" "popcnt")
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+ (eq_attr "cpu" "power6"))
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+ "FXU_power6")
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+
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(define_insn_reservation "power6-insert" 1
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(and (eq_attr "type" "insert_word")
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(eq_attr "cpu" "power6"))
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Index: gcc-4_7-branch/gcc/config/rs6000/power7.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/power7.md 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/power7.md 2012-07-06 19:50:30.078779999 -0700
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@@ -150,7 +150,7 @@
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; FX Unit
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(define_insn_reservation "power7-integer" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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- var_shift_rotate,exts,isel")
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+ var_shift_rotate,exts,isel,popcnt")
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(eq_attr "cpu" "power7"))
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"DU_power7,FXU_power7")
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Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:44:38.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:50:30.078779999 -0700
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@@ -144,7 +144,7 @@
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;; Define an insn type attribute. This is used in function unit delay
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;; computations.
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-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
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+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
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(const_string "integer"))
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;; Define floating point instruction sub-types for use with Xfpu.md
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@@ -2329,13 +2329,17 @@
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(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
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UNSPEC_POPCNTB))]
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"TARGET_POPCNTB"
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- "popcntb %0,%1")
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+ "popcntb %0,%1"
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+ [(set_attr "length" "4")
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+ (set_attr "type" "popcnt")])
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(define_insn "popcntd<mode>2"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
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"TARGET_POPCNTD"
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- "popcnt<wd> %0,%1")
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+ "popcnt<wd> %0,%1"
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+ [(set_attr "length" "4")
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+ (set_attr "type" "popcnt")])
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(define_expand "popcount<mode>2"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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