These patches are backport from gcc mainline they fix issues where eglibc was not compilable for e5500+ due to missing vector intrinsics It obsoletes the existing e5500 patch (From OE-Core rev: b440aeeceb8c2e9f412d98793fb1dd55ff9d73f5) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
753 lines
29 KiB
Diff
753 lines
29 KiB
Diff
Upstream-Status: Backport
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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From 7630308303ea21c318bd57c35590fc4f249a30d8 Mon Sep 17 00:00:00 2001
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From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Wed, 16 May 2012 08:43:41 +0000
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Subject: [PATCH] * config/rs6000/rs6000-opts.h (enum processor_type):
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Add PROCESSOR_PPC8548. *
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config/rs6000/rs6000-cpus.def: Reference it for cpu="8548".
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* config/rs6000/rs6000.md (cpu attribute
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definition): Add ppc8548. * config/rs6000/8540.md:
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indicate that the units/patterns apply to ppc8548
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as well.
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* config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
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default_cpu into implicit_cpu, conveying what --with-cpu was passed at
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configure time. Treat implicit_cpu as have_CPU. Pick defaults for SPE
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related flags, check that what is queried is supported by the selected
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configuration. Rework the single/double_float and MASK_STRING resets to
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hit for all the E500 cores (854x + E500MC variants). Select the ppc8540
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costs for PROCESSOR_PPC8548 as well.
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(rs6000_issue_rate): case CPU_PPC8548 together with CPU_PPC8540.
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(rs6000_use_sched_lookahead): Likewise, rewriting function as a case
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statement instead of a sequence of ifs.
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* config/rs6000/rs6000.h (TARGET_E500): Remove.
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(TARGET_NO_LWSYNC): Adjust accordingly.
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* config/rs6000/e500.h (TARGET_E500): Remove.
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(CHECK_E500_OPTIONS): Adjust accordingly.
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* config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Remove.
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(TARGET_DEFAULT): Reformat definition to match the one in linuxspe.h.
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* config/rs6000/linuxspe.h: Likewise.
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* config/rs6000/vxworks.h: Remove bogus TARGET_E500 overrides and
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superfluous comments.
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* config/rs6000/e500-double.h: Remove.
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* config.gcc (pick a default with_cpu): For powerpc*-*-*spe*,
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default to with_cpu=8548 if --enable-e500-double, and to 8540
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otherwise.
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(set misc flags section): For powerpc*|rs6000*, remove inclusion
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of e500-double.h for --enable-e500-double.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187581 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/ChangeLog | 37 +++++++++
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gcc/config.gcc | 12 +--
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gcc/config/rs6000/8540.md | 50 ++++++------
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gcc/config/rs6000/e500-double.h | 24 ------
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gcc/config/rs6000/e500.h | 10 +--
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gcc/config/rs6000/eabispe.h | 17 +---
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gcc/config/rs6000/linuxspe.h | 16 +---
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gcc/config/rs6000/rs6000-cpus.def | 3 +-
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gcc/config/rs6000/rs6000-opts.h | 1 +
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gcc/config/rs6000/rs6000.c | 155 +++++++++++++++++++++++--------------
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gcc/config/rs6000/rs6000.h | 7 +-
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gcc/config/rs6000/rs6000.md | 2 +-
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gcc/config/rs6000/rtems.h | 14 ----
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gcc/config/rs6000/vxworks.h | 11 ---
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14 files changed, 178 insertions(+), 181 deletions(-)
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Index: gcc-4_7-branch/gcc/config.gcc
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:43:53.000000000 -0700
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+++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:44:38.000000000 -0700
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@@ -2876,6 +2876,13 @@
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mips*-*-vxworks)
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with_arch=mips2
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;;
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+ powerpc*-*-*spe*)
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+ if test x$enable_e500_double = xyes; then
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+ with_cpu=8548
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+ else
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+ with_cpu=8540
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+ fi
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+ ;;
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sparc-leon*-*)
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with_cpu=v8;
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;;
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@@ -3564,11 +3571,6 @@
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c_target_objs="${c_target_objs} rs6000-c.o"
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cxx_target_objs="${cxx_target_objs} rs6000-c.o"
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tmake_file="rs6000/t-rs6000 ${tmake_file}"
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-
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- if test x$enable_e500_double = xyes
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- then
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- tm_file="$tm_file rs6000/e500-double.h"
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- fi
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;;
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sh[123456ble]*-*-* | sh-*-*)
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Index: gcc-4_7-branch/gcc/config/rs6000/8540.md
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/8540.md 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/8540.md 2012-07-06 19:44:38.466780001 -0700
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@@ -87,18 +87,18 @@
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(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
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delayed_compare,var_delayed_compare,fast_compare,\
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shift,trap,var_shift_rotate,cntlz,exts,isel")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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(define_insn_reservation "ppc8540_two" 1
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(and (eq_attr "type" "two")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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(define_insn_reservation "ppc8540_three" 1
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(and (eq_attr "type" "three")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
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ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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@@ -106,13 +106,13 @@
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;; Branch. Actually this latency time is not used by the scheduler.
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(define_insn_reservation "ppc8540_branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Multiply
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(define_insn_reservation "ppc8540_multiply" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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@@ -122,57 +122,57 @@
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;; time.
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(define_insn_reservation "ppc8540_divide" 14
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(and (eq_attr "type" "idiv")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; CR logical
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(define_insn_reservation "ppc8540_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_bu,ppc8540_retire")
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;; Mfcr
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(define_insn_reservation "ppc8540_mfcr" 1
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(and (eq_attr "type" "mfcr")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtcrf
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(define_insn_reservation "ppc8540_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Mtjmpr
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(define_insn_reservation "ppc8540_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Loads
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(define_insn_reservation "ppc8540_load" 3
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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load_l,sync")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Stores.
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(define_insn_reservation "ppc8540_store" 3
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(and (eq_attr "type" "store,store_ux,store_u,store_c")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Simple FP
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(define_insn_reservation "ppc8540_simple_float" 1
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(and (eq_attr "type" "fpsimple")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; FP
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(define_insn_reservation "ppc8540_float" 4
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(and (eq_attr "type" "fp")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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@@ -180,44 +180,44 @@
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;; because of the result automata will be huge.
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(define_insn_reservation "ppc8540_float_vector_divide" 29
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(and (eq_attr "type" "vecfdiv")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*28")
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;; Brinc
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(define_insn_reservation "ppc8540_brinc" 1
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(and (eq_attr "type" "brinc")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Simple vector
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(define_insn_reservation "ppc8540_simple_vector" 1
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(and (eq_attr "type" "vecsimple")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Simple vector compare
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(define_insn_reservation "ppc8540_simple_vector_compare" 1
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(and (eq_attr "type" "veccmpsimple")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
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;; Vector compare
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(define_insn_reservation "ppc8540_vector_compare" 1
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(and (eq_attr "type" "veccmp")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; evsplatfi evsplati
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(define_insn_reservation "ppc8540_vector_perm" 1
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(and (eq_attr "type" "vecperm")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
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;; Vector float
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(define_insn_reservation "ppc8540_float_vector" 4
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(and (eq_attr "type" "vecfloat")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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@@ -226,25 +226,25 @@
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;; of miu_stage3 here because we use the average latency time.
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(define_insn_reservation "ppc8540_vector_divide" 14
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(and (eq_attr "type" "vecdiv")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
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ppc8540_mu_div*13")
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;; Complex vector.
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(define_insn_reservation "ppc8540_complex_vector" 4
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(and (eq_attr "type" "veccomplex")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
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ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
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;; Vector load
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(define_insn_reservation "ppc8540_vector_load" 3
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(and (eq_attr "type" "vecload")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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;; Vector store
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(define_insn_reservation "ppc8540_vector_store" 3
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(and (eq_attr "type" "vecstore")
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- (eq_attr "cpu" "ppc8540"))
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+ (eq_attr "cpu" "ppc8540,ppc8548"))
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"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
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Index: gcc-4_7-branch/gcc/config/rs6000/e500-double.h
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/e500-double.h 2012-07-05 23:49:07.000000000 -0700
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+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
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@@ -1,24 +0,0 @@
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-/* Target definitions for E500 with double precision FP.
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- Copyright (C) 2004, 2006, 2007, 2011 Free Software Foundation, Inc.
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- Contributed by Aldy Hernandez (aldyh@redhat.com).
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-
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- This file is part of GCC.
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-
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- GCC is free software; you can redistribute it and/or modify it
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- under the terms of the GNU General Public License as published
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- by the Free Software Foundation; either version 3, or (at your
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- option) any later version.
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-
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- GCC is distributed in the hope that it will be useful, but WITHOUT
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- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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- License for more details.
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-
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- You should have received a copy of the GNU General Public License
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- along with GCC; see the file COPYING3. If not see
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- <http://www.gnu.org/licenses/>. */
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-
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-#undef SUB3TARGET_OVERRIDE_OPTIONS
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-#define SUB3TARGET_OVERRIDE_OPTIONS \
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- if (!global_options_set.x_rs6000_float_gprs) \
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- rs6000_float_gprs = 2;
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Index: gcc-4_7-branch/gcc/config/rs6000/e500.h
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/e500.h 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/e500.h 2012-07-06 19:44:38.466780001 -0700
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@@ -19,7 +19,6 @@
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#undef TARGET_SPE_ABI
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#undef TARGET_SPE
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-#undef TARGET_E500
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#undef TARGET_FPRS
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#undef TARGET_E500_SINGLE
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#undef TARGET_E500_DOUBLE
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@@ -27,21 +26,20 @@
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#define TARGET_SPE_ABI rs6000_spe_abi
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#define TARGET_SPE rs6000_spe
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-#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
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#define TARGET_FPRS (rs6000_float_gprs == 0)
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#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
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#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
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#define CHECK_E500_OPTIONS \
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do { \
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- if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \
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+ if (TARGET_SPE || TARGET_SPE_ABI \
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|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
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{ \
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if (TARGET_ALTIVEC) \
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- error ("AltiVec and E500 instructions cannot coexist"); \
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+ error ("AltiVec and SPE instructions cannot coexist"); \
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if (TARGET_VSX) \
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- error ("VSX and E500 instructions cannot coexist"); \
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+ error ("VSX and SPE instructions cannot coexist"); \
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if (TARGET_64BIT) \
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- error ("64-bit E500 not supported"); \
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+ error ("64-bit SPE not supported"); \
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if (TARGET_HARD_FLOAT && TARGET_FPRS) \
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error ("E500 and FPRs not supported"); \
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} \
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Index: gcc-4_7-branch/gcc/config/rs6000/eabispe.h
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config/rs6000/eabispe.h 2012-07-05 23:49:07.000000000 -0700
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+++ gcc-4_7-branch/gcc/config/rs6000/eabispe.h 2012-07-06 19:44:38.466780001 -0700
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@@ -21,21 +21,8 @@
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<http://www.gnu.org/licenses/>. */
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#undef TARGET_DEFAULT
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-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI \
|
|
- | MASK_STRICT_ALIGN)
|
|
-
|
|
-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
|
|
-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
|
|
- if (!global_options_set.x_rs6000_cpu_index) \
|
|
- rs6000_cpu = PROCESSOR_PPC8540; \
|
|
- if (!global_options_set.x_rs6000_spe_abi) \
|
|
- rs6000_spe_abi = 1; \
|
|
- if (!global_options_set.x_rs6000_float_gprs) \
|
|
- rs6000_float_gprs = 1; \
|
|
- if (!global_options_set.x_rs6000_spe) \
|
|
- rs6000_spe = 1; \
|
|
- if (target_flags & MASK_64BIT) \
|
|
- error ("-m64 not supported in this configuration")
|
|
+#define TARGET_DEFAULT \
|
|
+ (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI)
|
|
|
|
#undef ASM_DEFAULT_SPEC
|
|
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/linuxspe.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/linuxspe.h 2012-07-05 23:52:14.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/linuxspe.h 2012-07-06 19:44:38.466780001 -0700
|
|
@@ -22,20 +22,8 @@
|
|
|
|
/* Override rs6000.h and sysv4.h definition. */
|
|
#undef TARGET_DEFAULT
|
|
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
|
|
-
|
|
-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
|
|
-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
|
|
- if (!global_options_set.x_rs6000_cpu_index) \
|
|
- rs6000_cpu = PROCESSOR_PPC8540; \
|
|
- if (!global_options_set.x_rs6000_spe_abi) \
|
|
- rs6000_spe_abi = 1; \
|
|
- if (!global_options_set.x_rs6000_float_gprs) \
|
|
- rs6000_float_gprs = 1; \
|
|
- if (!global_options_set.x_rs6000_spe) \
|
|
- rs6000_spe = 1; \
|
|
- if (target_flags & MASK_64BIT) \
|
|
- error ("-m64 not supported in this configuration")
|
|
+#define TARGET_DEFAULT \
|
|
+ (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
|
|
|
|
#undef ASM_DEFAULT_SPEC
|
|
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:44:38.000000000 -0700
|
|
@@ -76,8 +76,7 @@
|
|
RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
|
|
RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
|
|
| MASK_ISEL)
|
|
-/* 8548 has a dummy entry for now. */
|
|
-RS6000_CPU ("8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
|
|
+RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
|
|
| MASK_ISEL)
|
|
RS6000_CPU ("a2", PROCESSOR_PPCA2,
|
|
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:44:38.000000000 -0700
|
|
@@ -49,6 +49,7 @@
|
|
PROCESSOR_PPC7400,
|
|
PROCESSOR_PPC7450,
|
|
PROCESSOR_PPC8540,
|
|
+ PROCESSOR_PPC8548,
|
|
PROCESSOR_PPCE300C2,
|
|
PROCESSOR_PPCE300C3,
|
|
PROCESSOR_PPCE500MC,
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:43:53.194780001 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:44:38.000000000 -0700
|
|
@@ -2597,7 +2597,10 @@
|
|
{
|
|
bool ret = true;
|
|
bool have_cpu = false;
|
|
- const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
|
|
+
|
|
+ /* The default cpu requested at configure time, if any. */
|
|
+ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
|
|
+
|
|
int set_masks;
|
|
int cpu_index;
|
|
int tune_index;
|
|
@@ -2616,11 +2619,6 @@
|
|
warning (0, "-malign-power is not supported for 64-bit Darwin;"
|
|
" it is incompatible with the installed C and C++ libraries");
|
|
|
|
- if (global_options_set.x_rs6000_spe_abi
|
|
- && rs6000_spe_abi
|
|
- && !TARGET_SPE_ABI)
|
|
- error ("not configured for SPE ABI");
|
|
-
|
|
/* Numerous experiment shows that IRA based loop pressure
|
|
calculation works better for RTL loop invariant motion on targets
|
|
with enough (>= 32) registers. It is an expensive optimization.
|
|
@@ -2656,7 +2654,8 @@
|
|
/* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
|
|
the cpu in a target attribute or pragma, but did not specify a tuning
|
|
option, use the cpu for the tuning option rather than the option specified
|
|
- with -mtune on the command line. */
|
|
+ with -mtune on the command line. Process a '--with-cpu' configuration
|
|
+ request as an implicit --cpu. */
|
|
if (rs6000_cpu_index >= 0)
|
|
{
|
|
cpu_index = rs6000_cpu_index;
|
|
@@ -2669,10 +2668,12 @@
|
|
}
|
|
else
|
|
{
|
|
- if (!default_cpu)
|
|
- default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
|
|
+ const char *default_cpu =
|
|
+ (implicit_cpu ? implicit_cpu
|
|
+ : (TARGET_POWERPC64 ? "powerpc64" : "powerpc"));
|
|
|
|
rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
|
|
+ have_cpu = implicit_cpu != 0;
|
|
}
|
|
|
|
gcc_assert (cpu_index >= 0);
|
|
@@ -2703,6 +2704,42 @@
|
|
gcc_assert (tune_index >= 0);
|
|
rs6000_cpu = processor_target_table[tune_index].processor;
|
|
|
|
+ /* Pick defaults for SPE related control flags. Do this early to make sure
|
|
+ that the TARGET_ macros are representative ASAP. */
|
|
+ {
|
|
+ int spe_capable_cpu =
|
|
+ (rs6000_cpu == PROCESSOR_PPC8540
|
|
+ || rs6000_cpu == PROCESSOR_PPC8548);
|
|
+
|
|
+ if (!global_options_set.x_rs6000_spe_abi)
|
|
+ rs6000_spe_abi = spe_capable_cpu;
|
|
+
|
|
+ if (!global_options_set.x_rs6000_spe)
|
|
+ rs6000_spe = spe_capable_cpu;
|
|
+
|
|
+ if (!global_options_set.x_rs6000_float_gprs)
|
|
+ rs6000_float_gprs =
|
|
+ (rs6000_cpu == PROCESSOR_PPC8540 ? 1
|
|
+ : rs6000_cpu == PROCESSOR_PPC8548 ? 2
|
|
+ : 0);
|
|
+ }
|
|
+
|
|
+ if (global_options_set.x_rs6000_spe_abi
|
|
+ && rs6000_spe_abi
|
|
+ && !TARGET_SPE_ABI)
|
|
+ error ("not configured for SPE ABI");
|
|
+
|
|
+ if (global_options_set.x_rs6000_spe
|
|
+ && rs6000_spe
|
|
+ && !TARGET_SPE)
|
|
+ error ("not configured for SPE instruction set");
|
|
+
|
|
+ if (main_target_opt != NULL
|
|
+ && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
|
|
+ || (main_target_opt->x_rs6000_spe != rs6000_spe)
|
|
+ || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
|
|
+ error ("target attribute or pragma changes SPE ABI");
|
|
+
|
|
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|
|
|| rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
|
|
{
|
|
@@ -2938,35 +2975,44 @@
|
|
SUB3TARGET_OVERRIDE_OPTIONS;
|
|
#endif
|
|
|
|
- if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
|
|
- || rs6000_cpu == PROCESSOR_PPCE500MC64)
|
|
+ /* For the E500 family of cores, reset the single/double FP flags to let us
|
|
+ check that they remain constant across attributes or pragmas. Also,
|
|
+ clear a possible request for string instructions, not supported and which
|
|
+ we might have silently queried above for -Os.
|
|
+
|
|
+ For other families, clear ISEL in case it was set implicitly.
|
|
+ */
|
|
+
|
|
+ switch (rs6000_cpu)
|
|
{
|
|
- /* The e500 and e500mc do not have string instructions, and we set
|
|
- MASK_STRING above when optimizing for size. */
|
|
- if ((target_flags & MASK_STRING) != 0)
|
|
- target_flags = target_flags & ~MASK_STRING;
|
|
- }
|
|
- else if (global_options_set.x_rs6000_cpu_index)
|
|
- {
|
|
- /* For the powerpc-eabispe configuration, we set all these by
|
|
- default, so let's unset them if we manually set another
|
|
- CPU that is not the E500. */
|
|
- if (main_target_opt != NULL
|
|
- && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
|
|
- || (main_target_opt->x_rs6000_spe != rs6000_spe)
|
|
- || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
|
|
- error ("target attribute or pragma changes SPE ABI");
|
|
- else
|
|
- {
|
|
- if (!global_options_set.x_rs6000_spe_abi)
|
|
- rs6000_spe_abi = 0;
|
|
- if (!global_options_set.x_rs6000_spe)
|
|
- rs6000_spe = 0;
|
|
- if (!global_options_set.x_rs6000_float_gprs)
|
|
- rs6000_float_gprs = 0;
|
|
- }
|
|
- if (!(target_flags_explicit & MASK_ISEL))
|
|
+ case PROCESSOR_PPC8540:
|
|
+ case PROCESSOR_PPC8548:
|
|
+ case PROCESSOR_PPCE500MC:
|
|
+ case PROCESSOR_PPCE500MC64:
|
|
+
|
|
+ rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
|
|
+ rs6000_double_float = TARGET_E500_DOUBLE;
|
|
+
|
|
+ target_flags &= ~MASK_STRING;
|
|
+
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+
|
|
+ if (have_cpu && !(target_flags_explicit & MASK_ISEL))
|
|
target_flags &= ~MASK_ISEL;
|
|
+
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (main_target_opt)
|
|
+ {
|
|
+ if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
|
|
+ error ("target attribute or pragma changes single precision floating "
|
|
+ "point");
|
|
+ if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
|
|
+ error ("target attribute or pragma changes double precision floating "
|
|
+ "point");
|
|
}
|
|
|
|
/* Detect invalid option combinations with E500. */
|
|
@@ -3193,6 +3239,7 @@
|
|
break;
|
|
|
|
case PROCESSOR_PPC8540:
|
|
+ case PROCESSOR_PPC8548:
|
|
rs6000_cost = &ppc8540_cost;
|
|
break;
|
|
|
|
@@ -3265,26 +3312,6 @@
|
|
&& rs6000_single_float == 0 && rs6000_double_float == 0)
|
|
rs6000_single_float = rs6000_double_float = 1;
|
|
|
|
- /* Reset single and double FP flags if target is E500. */
|
|
- if (TARGET_E500)
|
|
- {
|
|
- rs6000_single_float = rs6000_double_float = 0;
|
|
- if (TARGET_E500_SINGLE)
|
|
- rs6000_single_float = 1;
|
|
- if (TARGET_E500_DOUBLE)
|
|
- rs6000_single_float = rs6000_double_float = 1;
|
|
- }
|
|
-
|
|
- if (main_target_opt)
|
|
- {
|
|
- if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
|
|
- error ("target attribute or pragma changes single precision floating "
|
|
- "point");
|
|
- if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
|
|
- error ("target attribute or pragma changes double precision floating "
|
|
- "point");
|
|
- }
|
|
-
|
|
/* If not explicitly specified via option, decide whether to generate indexed
|
|
load/store instructions. */
|
|
if (TARGET_AVOID_XFORM == -1)
|
|
@@ -22816,6 +22843,7 @@
|
|
case CPU_PPC750:
|
|
case CPU_PPC7400:
|
|
case CPU_PPC8540:
|
|
+ case CPU_PPC8548:
|
|
case CPU_CELL:
|
|
case CPU_PPCE300C2:
|
|
case CPU_PPCE300C3:
|
|
@@ -22846,11 +22874,18 @@
|
|
static int
|
|
rs6000_use_sched_lookahead (void)
|
|
{
|
|
- if (rs6000_cpu_attr == CPU_PPC8540)
|
|
- return 4;
|
|
- if (rs6000_cpu_attr == CPU_CELL)
|
|
- return (reload_completed ? 8 : 0);
|
|
- return 0;
|
|
+ switch (rs6000_cpu_attr)
|
|
+ {
|
|
+ case CPU_PPC8540:
|
|
+ case CPU_PPC8548:
|
|
+ return 4;
|
|
+
|
|
+ case CPU_CELL:
|
|
+ return (reload_completed ? 8 : 0);
|
|
+
|
|
+ default:
|
|
+ return 0;
|
|
+ }
|
|
}
|
|
|
|
/* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:44:38.000000000 -0700
|
|
@@ -457,7 +457,6 @@
|
|
|
|
#define TARGET_SPE_ABI 0
|
|
#define TARGET_SPE 0
|
|
-#define TARGET_E500 0
|
|
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
|
|
#define TARGET_FPRS 1
|
|
#define TARGET_E500_SINGLE 0
|
|
@@ -500,11 +499,11 @@
|
|
|| TARGET_ALTIVEC \
|
|
|| TARGET_VSX)))
|
|
|
|
+/* E500 cores only support plain "sync", not lwsync. */
|
|
+#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
|
|
+ || rs6000_cpu == PROCESSOR_PPC8548)
|
|
|
|
|
|
-/* E500 processors only support plain "sync", not lwsync. */
|
|
-#define TARGET_NO_LWSYNC TARGET_E500
|
|
-
|
|
/* Which machine supports the various reciprocal estimate instructions. */
|
|
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
|
|
&& TARGET_FPRS && TARGET_SINGLE_FLOAT)
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:44:38.000000000 -0700
|
|
@@ -166,7 +166,7 @@
|
|
;; Processor type -- this attribute must exactly match the processor_type
|
|
;; enumeration in rs6000.h.
|
|
|
|
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
|
|
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
|
|
(const (symbol_ref "rs6000_cpu_attr")))
|
|
|
|
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rtems.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rtems.h 2012-07-05 23:49:07.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rtems.h 2012-07-06 19:44:38.470780001 -0700
|
|
@@ -55,17 +55,3 @@
|
|
#undef SUBSUBTARGET_EXTRA_SPECS
|
|
#define SUBSUBTARGET_EXTRA_SPECS \
|
|
{ "cpp_os_rtems", CPP_OS_RTEMS_SPEC }
|
|
-
|
|
-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
|
|
-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
|
|
- do { \
|
|
- if (TARGET_E500) \
|
|
- { \
|
|
- if (TARGET_HARD_FLOAT && !global_options_set.x_rs6000_float_gprs) \
|
|
- rs6000_float_gprs = 1; \
|
|
- if (rs6000_float_gprs != 0 && !global_options_set.x_rs6000_spe) \
|
|
- rs6000_spe = 1; \
|
|
- if (rs6000_spe && !global_options_set.x_rs6000_spe_abi) \
|
|
- rs6000_spe_abi = 1; \
|
|
- } \
|
|
- } while(0)
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/vxworks.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/vxworks.h 2012-07-05 23:49:07.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/vxworks.h 2012-07-06 19:44:38.470780001 -0700
|
|
@@ -122,19 +122,8 @@
|
|
|
|
#undef ABI_STACK_BOUNDARY
|
|
|
|
-/* Make -mcpu=8540 imply SPE. ISEL is automatically enabled, the
|
|
- others must be done by hand. Handle -mrtp. Disable -fPIC
|
|
- for -mrtp - the VxWorks PIC model is not compatible with it. */
|
|
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
|
|
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
|
|
- do { \
|
|
- if (TARGET_E500) \
|
|
- { \
|
|
- rs6000_spe = 1; \
|
|
- rs6000_spe_abi = 1; \
|
|
- rs6000_float_gprs = 1; \
|
|
- } \
|
|
- \
|
|
if (!global_options_set.x_g_switch_value) \
|
|
g_switch_value = SDATA_DEFAULT_SIZE; \
|
|
VXWORKS_OVERRIDE_OPTIONS; \
|