These patches are backport from gcc mainline they fix issues where eglibc was not compilable for e5500+ due to missing vector intrinsics It obsoletes the existing e5500 patch (From OE-Core rev: b440aeeceb8c2e9f412d98793fb1dd55ff9d73f5) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
714 lines
26 KiB
Diff
714 lines
26 KiB
Diff
Upstream-Status: Backport
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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From b770074cee13445eba1bf4e99649c5ceac9a4b5a Mon Sep 17 00:00:00 2001
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From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Tue, 5 Jun 2012 16:05:16 +0000
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Subject: [PATCH] 2012-06-01 Edmar Wienskoski <edmar@freescale.com>
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* config/rs6000/e5500.md: New file.
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* config/rs6000/e6500.md: New file.
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* config/rs6000/rs6000.c (processor_costs): Add new costs for
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e5500 and e6500.
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(rs6000_option_override_internal): Altivec and Spe options not
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allowed with e5500. Spe options not allowed with e6500. Increase
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move inline limit for e5500 and e6500. Disable string instructions
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for e5500 and e6500. Enable branch targets alignment for e5500 and
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e6500. Initialize rs6000_cost for e5500 and e6500.
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(rs6000_adjust_cost): Add extra scheduling cycles between compare
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and brnach for e5500 and e6500.
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(rs6000_issue_rate): Set issue rate for e5500 and e6500.
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* config/rs6000/rs6000-cpus.def: Add cpu definitions for e5500 and
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e6500.
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* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add e5500 and e6500.
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* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce5500 and
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ppce6500.
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Include e5500.md and e6500.md.
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* config/rs6000/rs6000-opt.h (processor_type): Add
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PROCESSOR_PPCE5500 and PROCESSOR_PPCE6500.
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* config.gcc (cpu_is_64bit): Add new cores e5500, e6500.
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(powerpc*-*-*): Add new cores e5500, e6500.
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* doc/invoke.texi: (item -mcpu): Add e5500 and e6500 to list of cpus.
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gcc/testsuite
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2012-06-01 Edmar Wienskoski <edmar@freescale.com>
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* gcc.dg/tree-ssa/vector-3.c: Adjust regular expression.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188244 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/ChangeLog | 26 ++++
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gcc/config.gcc | 6 +-
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gcc/config/rs6000/e5500.md | 176 ++++++++++++++++++++++++
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gcc/config/rs6000/e6500.md | 213 ++++++++++++++++++++++++++++++
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gcc/config/rs6000/rs6000-cpus.def | 4 +
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gcc/config/rs6000/rs6000-opts.h | 2 +
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gcc/config/rs6000/rs6000.c | 68 +++++++++-
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gcc/config/rs6000/rs6000.h | 2 +
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gcc/config/rs6000/rs6000.md | 4 +-
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gcc/doc/invoke.texi | 12 +-
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gcc/testsuite/ChangeLog | 4 +
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gcc/testsuite/gcc.dg/tree-ssa/vector-3.c | 2 +-
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12 files changed, 506 insertions(+), 13 deletions(-)
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create mode 100644 gcc/config/rs6000/e5500.md
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create mode 100644 gcc/config/rs6000/e6500.md
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Index: gcc-4_7-branch/gcc/config.gcc
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===================================================================
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--- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:52:30.000000000 -0700
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+++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:53:26.350779999 -0700
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@@ -413,7 +413,7 @@
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extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
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need_64bit_hwint=yes
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case x$with_cpu in
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- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
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+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
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cpu_is_64bit=yes
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;;
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esac
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@@ -3361,8 +3361,8 @@
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| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
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| 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
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| 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
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- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
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- | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | e6500 \
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+ | titan | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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# OK
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;;
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*)
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Index: gcc-4_7-branch/gcc/config/rs6000/e5500.md
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ gcc-4_7-branch/gcc/config/rs6000/e5500.md 2012-07-06 19:53:26.350779999 -0700
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@@ -0,0 +1,176 @@
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+;; Pipeline description for Freescale PowerPC e5500 core.
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+;; Copyright (C) 2012 Free Software Foundation, Inc.
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+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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+;;
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+;; This file is part of GCC.
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+;;
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+;; GCC is free software; you can redistribute it and/or modify it
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+;; under the terms of the GNU General Public License as published
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+;; by the Free Software Foundation; either version 3, or (at your
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+;; option) any later version.
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+;;
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+;; GCC is distributed in the hope that it will be useful, but WITHOUT
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+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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+;; License for more details.
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+;;
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING3. If not see
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+;; <http://www.gnu.org/licenses/>.
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+;;
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+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
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+;; Max issue 3 insns/clock cycle (includes 1 branch)
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+
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+(define_automaton "e5500_most,e5500_long")
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+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
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+
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+;; SFX.
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+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
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+
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+;; CFX.
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+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
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+
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+;; Non-pipelined division.
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+(define_cpu_unit "e5500_cfx_div" "e5500_long")
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+
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+;; LSU.
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+(define_cpu_unit "e5500_lsu" "e5500_most")
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+
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+;; FPU.
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+(define_cpu_unit "e5500_fpu" "e5500_long")
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+
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+;; BU.
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+(define_cpu_unit "e5500_bu" "e5500_most")
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+
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+;; The following units are used to make the automata deterministic.
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+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
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+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
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+(presence_set "present_e5500_decode_0" "e5500_decode_0")
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+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
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+
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+;; Some useful abbreviations.
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+(define_reservation "e5500_decode"
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+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
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+(define_reservation "e5500_sfx"
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+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
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+
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+;; SFX.
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+(define_insn_reservation "e5500_sfx" 1
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+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
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+ shift,cntlz,exts")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx")
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+
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+(define_insn_reservation "e5500_sfx2" 2
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+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx")
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+
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+(define_insn_reservation "e5500_delayed" 2
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+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx*2")
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+
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+(define_insn_reservation "e5500_two" 2
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+ (and (eq_attr "type" "two")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
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+
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+(define_insn_reservation "e5500_three" 3
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+ (and (eq_attr "type" "three")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
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+
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+;; SFX - Mfcr.
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+(define_insn_reservation "e5500_mfcr" 4
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+ (and (eq_attr "type" "mfcr")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx_0*4")
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+
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+;; SFX - Mtcrf.
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+(define_insn_reservation "e5500_mtcrf" 1
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+ (and (eq_attr "type" "mtcr")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx_0")
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+
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+;; SFX - Mtjmpr.
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+(define_insn_reservation "e5500_mtjmpr" 1
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+ (and (eq_attr "type" "mtjmpr,mfjmpr")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_sfx")
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+
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+;; CFX - Multiply.
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+(define_insn_reservation "e5500_multiply" 4
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+ (and (eq_attr "type" "imul")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
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+
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+(define_insn_reservation "e5500_multiply_i" 5
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+ (and (eq_attr "type" "imul2,imul3,imul_compare")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_cfx_stage0,\
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+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
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+
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+;; CFX - Divide.
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+(define_insn_reservation "e5500_divide" 16
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+ (and (eq_attr "type" "idiv")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
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+ e5500_cfx_div*15")
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+
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+(define_insn_reservation "e5500_divide_d" 26
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+ (and (eq_attr "type" "ldiv")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
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+ e5500_cfx_div*25")
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+
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+;; LSU - Loads.
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+(define_insn_reservation "e5500_load" 3
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+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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+ load_l,sync")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_lsu")
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+
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+(define_insn_reservation "e5500_fpload" 4
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+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_lsu")
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+
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+;; LSU - Stores.
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+(define_insn_reservation "e5500_store" 3
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+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_lsu")
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+
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+(define_insn_reservation "e5500_fpstore" 3
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+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_lsu")
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+
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+;; FP.
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+(define_insn_reservation "e5500_float" 7
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+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_fpu")
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+
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+(define_insn_reservation "e5500_sdiv" 20
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+ (and (eq_attr "type" "sdiv")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_fpu*20")
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+
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+(define_insn_reservation "e5500_ddiv" 35
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+ (and (eq_attr "type" "ddiv")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_fpu*35")
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+
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+;; BU.
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+(define_insn_reservation "e5500_branch" 1
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+ (and (eq_attr "type" "jmpreg,branch,isync")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_bu")
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+
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+;; BU - CR logical.
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+(define_insn_reservation "e5500_cr_logical" 1
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+ (and (eq_attr "type" "cr_logical,delayed_cr")
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+ (eq_attr "cpu" "ppce5500"))
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+ "e5500_decode,e5500_bu")
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Index: gcc-4_7-branch/gcc/config/rs6000/e6500.md
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ gcc-4_7-branch/gcc/config/rs6000/e6500.md 2012-07-06 19:53:26.354779999 -0700
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@@ -0,0 +1,213 @@
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+;; Pipeline description for Freescale PowerPC e6500 core.
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+;; Copyright (C) 2012 Free Software Foundation, Inc.
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+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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+;;
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+;; This file is part of GCC.
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+;;
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+;; GCC is free software; you can redistribute it and/or modify it
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+;; under the terms of the GNU General Public License as published
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+;; by the Free Software Foundation; either version 3, or (at your
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+;; option) any later version.
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+;;
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+;; GCC is distributed in the hope that it will be useful, but WITHOUT
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+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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+;; License for more details.
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+;;
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING3. If not see
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+;; <http://www.gnu.org/licenses/>.
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+;;
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+;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
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+;; Max issue 3 insns/clock cycle (includes 1 branch)
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+
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+(define_automaton "e6500_most,e6500_long,e6500_vec")
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+(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
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+
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+;; SFX.
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+(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
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+
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+;; CFX.
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+(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
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+
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+;; Non-pipelined division.
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+(define_cpu_unit "e6500_cfx_div" "e6500_long")
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+
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+;; LSU.
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+(define_cpu_unit "e6500_lsu" "e6500_most")
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+
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+;; FPU.
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+(define_cpu_unit "e6500_fpu" "e6500_long")
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+
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+;; BU.
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+(define_cpu_unit "e6500_bu" "e6500_most")
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+
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+;; Altivec unit
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+(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
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+
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+;; The following units are used to make the automata deterministic.
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+(define_cpu_unit "present_e6500_decode_0" "e6500_most")
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+(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
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+(presence_set "present_e6500_decode_0" "e6500_decode_0")
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+(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
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+
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+;; Some useful abbreviations.
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+(define_reservation "e6500_decode"
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+ "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
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+(define_reservation "e6500_sfx"
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+ "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
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+
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+;; SFX.
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+(define_insn_reservation "e6500_sfx" 1
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+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
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+ shift,cntlz,exts")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,e6500_sfx")
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+
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+(define_insn_reservation "e6500_sfx2" 2
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+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,e6500_sfx")
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+
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+(define_insn_reservation "e6500_delayed" 2
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+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,e6500_sfx*2")
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+
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+(define_insn_reservation "e6500_two" 2
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+ (and (eq_attr "type" "two")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
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+
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+(define_insn_reservation "e6500_three" 3
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+ (and (eq_attr "type" "three")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
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+
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+;; SFX - Mfcr.
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+(define_insn_reservation "e6500_mfcr" 4
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+ (and (eq_attr "type" "mfcr")
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+ (eq_attr "cpu" "ppce6500"))
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+ "e6500_decode,e6500_sfx_0*4")
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+
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+;; SFX - Mtcrf.
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+(define_insn_reservation "e6500_mtcrf" 1
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+ (and (eq_attr "type" "mtcr")
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+ (eq_attr "cpu" "ppce6500"))
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|
+ "e6500_decode,e6500_sfx_0")
|
|
+
|
|
+;; SFX - Mtjmpr.
|
|
+(define_insn_reservation "e6500_mtjmpr" 1
|
|
+ (and (eq_attr "type" "mtjmpr,mfjmpr")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_sfx")
|
|
+
|
|
+;; CFX - Multiply.
|
|
+(define_insn_reservation "e6500_multiply" 4
|
|
+ (and (eq_attr "type" "imul")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
|
|
+
|
|
+(define_insn_reservation "e6500_multiply_i" 5
|
|
+ (and (eq_attr "type" "imul2,imul3,imul_compare")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_cfx_stage0,\
|
|
+ e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
|
|
+
|
|
+;; CFX - Divide.
|
|
+(define_insn_reservation "e6500_divide" 16
|
|
+ (and (eq_attr "type" "idiv")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
|
|
+ e6500_cfx_div*15")
|
|
+
|
|
+(define_insn_reservation "e6500_divide_d" 26
|
|
+ (and (eq_attr "type" "ldiv")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
|
|
+ e6500_cfx_div*25")
|
|
+
|
|
+;; LSU - Loads.
|
|
+(define_insn_reservation "e6500_load" 3
|
|
+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
|
|
+ load_l,sync")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+(define_insn_reservation "e6500_fpload" 4
|
|
+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+(define_insn_reservation "e6500_vecload" 4
|
|
+ (and (eq_attr "type" "vecload")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+;; LSU - Stores.
|
|
+(define_insn_reservation "e6500_store" 3
|
|
+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+(define_insn_reservation "e6500_fpstore" 3
|
|
+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+(define_insn_reservation "e6500_vecstore" 4
|
|
+ (and (eq_attr "type" "vecstore")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_lsu")
|
|
+
|
|
+;; FP.
|
|
+(define_insn_reservation "e6500_float" 7
|
|
+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_fpu")
|
|
+
|
|
+(define_insn_reservation "e6500_sdiv" 20
|
|
+ (and (eq_attr "type" "sdiv")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_fpu*20")
|
|
+
|
|
+(define_insn_reservation "e6500_ddiv" 35
|
|
+ (and (eq_attr "type" "ddiv")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_fpu*35")
|
|
+
|
|
+;; BU.
|
|
+(define_insn_reservation "e6500_branch" 1
|
|
+ (and (eq_attr "type" "jmpreg,branch,isync")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_bu")
|
|
+
|
|
+;; BU - CR logical.
|
|
+(define_insn_reservation "e6500_cr_logical" 1
|
|
+ (and (eq_attr "type" "cr_logical,delayed_cr")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_bu")
|
|
+
|
|
+;; VSFX.
|
|
+(define_insn_reservation "e6500_vecsimple" 1
|
|
+ (and (eq_attr "type" "vecsimple,veccmp")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_vec")
|
|
+
|
|
+;; VCFX.
|
|
+(define_insn_reservation "e6500_veccomplex" 4
|
|
+ (and (eq_attr "type" "veccomplex")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_vec")
|
|
+
|
|
+;; VFPU.
|
|
+(define_insn_reservation "e6500_vecfloat" 6
|
|
+ (and (eq_attr "type" "vecfloat")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_vec")
|
|
+
|
|
+;; VPERM.
|
|
+(define_insn_reservation "e6500_vecperm" 2
|
|
+ (and (eq_attr "type" "vecperm")
|
|
+ (eq_attr "cpu" "ppce6500"))
|
|
+ "e6500_decode,e6500_vecperm")
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:52:30.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:53:26.354779999 -0700
|
|
@@ -87,6 +87,10 @@
|
|
| MASK_ISEL)
|
|
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
|
|
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
|
|
+RS6000_CPU ("e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
|
|
+ | MASK_PPC_GFXOPT | MASK_ISEL)
|
|
+RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
|
|
+ | MASK_MFCRF | MASK_ISEL)
|
|
RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
|
|
RS6000_CPU ("970", PROCESSOR_POWER4,
|
|
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:52:30.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:53:26.354779999 -0700
|
|
@@ -54,6 +54,8 @@
|
|
PROCESSOR_PPCE300C3,
|
|
PROCESSOR_PPCE500MC,
|
|
PROCESSOR_PPCE500MC64,
|
|
+ PROCESSOR_PPCE5500,
|
|
+ PROCESSOR_PPCE6500,
|
|
PROCESSOR_POWER4,
|
|
PROCESSOR_POWER5,
|
|
PROCESSOR_POWER6,
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:52:30.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:53:26.354779999 -0700
|
|
@@ -755,6 +755,44 @@
|
|
1, /* prefetch streams /*/
|
|
};
|
|
|
|
+/* Instruction costs on PPCE5500 processors. */
|
|
+static const
|
|
+struct processor_costs ppce5500_cost = {
|
|
+ COSTS_N_INSNS (5), /* mulsi */
|
|
+ COSTS_N_INSNS (5), /* mulsi_const */
|
|
+ COSTS_N_INSNS (4), /* mulsi_const9 */
|
|
+ COSTS_N_INSNS (5), /* muldi */
|
|
+ COSTS_N_INSNS (14), /* divsi */
|
|
+ COSTS_N_INSNS (14), /* divdi */
|
|
+ COSTS_N_INSNS (7), /* fp */
|
|
+ COSTS_N_INSNS (10), /* dmul */
|
|
+ COSTS_N_INSNS (36), /* sdiv */
|
|
+ COSTS_N_INSNS (66), /* ddiv */
|
|
+ 64, /* cache line size */
|
|
+ 32, /* l1 cache */
|
|
+ 128, /* l2 cache */
|
|
+ 1, /* prefetch streams /*/
|
|
+};
|
|
+
|
|
+/* Instruction costs on PPCE6500 processors. */
|
|
+static const
|
|
+struct processor_costs ppce6500_cost = {
|
|
+ COSTS_N_INSNS (5), /* mulsi */
|
|
+ COSTS_N_INSNS (5), /* mulsi_const */
|
|
+ COSTS_N_INSNS (4), /* mulsi_const9 */
|
|
+ COSTS_N_INSNS (5), /* muldi */
|
|
+ COSTS_N_INSNS (14), /* divsi */
|
|
+ COSTS_N_INSNS (14), /* divdi */
|
|
+ COSTS_N_INSNS (7), /* fp */
|
|
+ COSTS_N_INSNS (10), /* dmul */
|
|
+ COSTS_N_INSNS (36), /* sdiv */
|
|
+ COSTS_N_INSNS (66), /* ddiv */
|
|
+ 64, /* cache line size */
|
|
+ 32, /* l1 cache */
|
|
+ 128, /* l2 cache */
|
|
+ 1, /* prefetch streams /*/
|
|
+};
|
|
+
|
|
/* Instruction costs on AppliedMicro Titan processors. */
|
|
static const
|
|
struct processor_costs titan_cost = {
|
|
@@ -2741,13 +2779,19 @@
|
|
error ("target attribute or pragma changes SPE ABI");
|
|
|
|
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|
|
- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
|
|
+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
|
|
+ || rs6000_cpu == PROCESSOR_PPCE5500)
|
|
{
|
|
if (TARGET_ALTIVEC)
|
|
error ("AltiVec not supported in this target");
|
|
if (TARGET_SPE)
|
|
error ("SPE not supported in this target");
|
|
}
|
|
+ if (rs6000_cpu == PROCESSOR_PPCE6500)
|
|
+ {
|
|
+ if (TARGET_SPE)
|
|
+ error ("SPE not supported in this target");
|
|
+ }
|
|
|
|
/* Disable Cell microcode if we are optimizing for the Cell
|
|
and not optimizing for size. */
|
|
@@ -2842,7 +2886,9 @@
|
|
user's opinion, though. */
|
|
if (rs6000_block_move_inline_limit == 0
|
|
&& (rs6000_cpu == PROCESSOR_PPCE500MC
|
|
- || rs6000_cpu == PROCESSOR_PPCE500MC64))
|
|
+ || rs6000_cpu == PROCESSOR_PPCE500MC64
|
|
+ || rs6000_cpu == PROCESSOR_PPCE5500
|
|
+ || rs6000_cpu == PROCESSOR_PPCE6500))
|
|
rs6000_block_move_inline_limit = 128;
|
|
|
|
/* store_one_arg depends on expand_block_move to handle at least the
|
|
@@ -2989,6 +3035,8 @@
|
|
case PROCESSOR_PPC8548:
|
|
case PROCESSOR_PPCE500MC:
|
|
case PROCESSOR_PPCE500MC64:
|
|
+ case PROCESSOR_PPCE5500:
|
|
+ case PROCESSOR_PPCE6500:
|
|
|
|
rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
|
|
rs6000_double_float = TARGET_E500_DOUBLE;
|
|
@@ -3033,7 +3081,9 @@
|
|
|| rs6000_cpu == PROCESSOR_POWER6
|
|
|| rs6000_cpu == PROCESSOR_POWER7
|
|
|| rs6000_cpu == PROCESSOR_PPCE500MC
|
|
- || rs6000_cpu == PROCESSOR_PPCE500MC64);
|
|
+ || rs6000_cpu == PROCESSOR_PPCE500MC64
|
|
+ || rs6000_cpu == PROCESSOR_PPCE5500
|
|
+ || rs6000_cpu == PROCESSOR_PPCE6500);
|
|
|
|
/* Allow debug switches to override the above settings. These are set to -1
|
|
in rs6000.opt to indicate the user hasn't directly set the switch. */
|
|
@@ -3256,6 +3306,14 @@
|
|
rs6000_cost = &ppce500mc64_cost;
|
|
break;
|
|
|
|
+ case PROCESSOR_PPCE5500:
|
|
+ rs6000_cost = &ppce5500_cost;
|
|
+ break;
|
|
+
|
|
+ case PROCESSOR_PPCE6500:
|
|
+ rs6000_cost = &ppce6500_cost;
|
|
+ break;
|
|
+
|
|
case PROCESSOR_TITAN:
|
|
rs6000_cost = &titan_cost;
|
|
break;
|
|
@@ -22304,6 +22362,8 @@
|
|
|| rs6000_cpu_attr == CPU_PPC750
|
|
|| rs6000_cpu_attr == CPU_PPC7400
|
|
|| rs6000_cpu_attr == CPU_PPC7450
|
|
+ || rs6000_cpu_attr == CPU_PPCE5500
|
|
+ || rs6000_cpu_attr == CPU_PPCE6500
|
|
|| rs6000_cpu_attr == CPU_POWER4
|
|
|| rs6000_cpu_attr == CPU_POWER5
|
|
|| rs6000_cpu_attr == CPU_POWER7
|
|
@@ -22849,6 +22909,8 @@
|
|
case CPU_PPCE300C3:
|
|
case CPU_PPCE500MC:
|
|
case CPU_PPCE500MC64:
|
|
+ case CPU_PPCE5500:
|
|
+ case CPU_PPCE6500:
|
|
case CPU_TITAN:
|
|
return 2;
|
|
case CPU_RIOS2:
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:52:30.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:53:26.358779999 -0700
|
|
@@ -168,6 +168,8 @@
|
|
%{mcpu=e300c3: -me300} \
|
|
%{mcpu=e500mc: -me500mc} \
|
|
%{mcpu=e500mc64: -me500mc64} \
|
|
+%{mcpu=e5500: -me5500} \
|
|
+%{mcpu=e6500: -me6500} \
|
|
%{maltivec: -maltivec} \
|
|
%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
|
|
-many"
|
|
Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:52:32.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:53:26.358779999 -0700
|
|
@@ -166,7 +166,7 @@
|
|
;; Processor type -- this attribute must exactly match the processor_type
|
|
;; enumeration in rs6000.h.
|
|
|
|
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
|
|
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
|
|
(const (symbol_ref "rs6000_cpu_attr")))
|
|
|
|
|
|
@@ -194,6 +194,8 @@
|
|
(include "e300c2c3.md")
|
|
(include "e500mc.md")
|
|
(include "e500mc64.md")
|
|
+(include "e5500.md")
|
|
+(include "e6500.md")
|
|
(include "power4.md")
|
|
(include "power5.md")
|
|
(include "power6.md")
|
|
Index: gcc-4_7-branch/gcc/doc/invoke.texi
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/doc/invoke.texi 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/doc/invoke.texi 2012-07-06 19:53:26.362779999 -0700
|
|
@@ -16565,11 +16565,13 @@
|
|
@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
|
|
@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
|
|
@samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
|
|
-@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3},
|
|
-@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
|
|
-@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
|
|
-@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
|
|
-@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
|
|
+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
|
|
+@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
|
|
+@samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
|
|
+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
|
|
+@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc},
|
|
+@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc},
|
|
+and @samp{rs64}.
|
|
|
|
@option{-mcpu=common} selects a completely generic processor. Code
|
|
generated under this option will run on any POWER or PowerPC processor.
|
|
Index: gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c
|
|
===================================================================
|
|
--- gcc-4_7-branch.orig/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:43:53.000000000 -0700
|
|
+++ gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:53:26.362779999 -0700
|
|
@@ -14,7 +14,7 @@
|
|
|
|
/* We should be able to optimize this to just "return 0.0;" */
|
|
/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized"} } */
|
|
-/* { dg-final { scan-tree-dump-times "0.0" 1 "optimized"} } */
|
|
+/* { dg-final { scan-tree-dump-times "0\\\.0" 1 "optimized"} } */
|
|
|
|
/* { dg-final { cleanup-tree-dump "optimized" } } */
|
|
|