- Upgrade elfutils to 0.160
- Move 0.148 patches from elfutils to elfutils-0.148
- Drop 0.158 patches that got from debain, so far debian
doesn't provide patches for 0.160 (the latest is 0.159)
- Move fixheadercheck.patch from 0.159 to 0.160
- We choose to use 0.159 patches from debian for the current 0.160
which located in elfutils-0.160
1) Rebase the following patches from 0.159 to 0.160
hppa_backend.diff
arm_backend.diff
mips_backend.diff
m68k_backend.diff
arm_func_value.patch
arm_unwind_ret_mask.patch
2) Rebase redhat-portability.diff according to
commit 52a6d20519
Author: Roxana Ciobanu <roxana.ciobanu@intel.com>
Date: Tue Jul 1 17:17:00 2014 +0300
elfutils/elfutils-native: Fix patching generated files
3) Drop the following patches which have already beem merged to 0.160
arm_unsupported.patch
arm_syscall.patch
unaligned.patch
aarch64-run-native-test-fix.patch
(From OE-Core rev: 74b191022494fc1d357c1f05dbce38c986bed365)
Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
450 lines
13 KiB
Diff
450 lines
13 KiB
Diff
Upstream-Status: Backport
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Index: elfutils-0.146/backends/arm_init.c
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===================================================================
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--- elfutils-0.146.orig/backends/arm_init.c 2009-04-21 14:50:01.000000000 +0000
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+++ elfutils-0.146/backends/arm_init.c 2010-04-24 10:11:13.000000000 +0000
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@@ -32,21 +32,32 @@
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#define RELOC_PREFIX R_ARM_
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#include "libebl_CPU.h"
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+#include "libebl_arm.h"
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+
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/* This defines the common reloc hooks based on arm_reloc.def. */
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#include "common-reloc.c"
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const char *
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arm_init (elf, machine, eh, ehlen)
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- Elf *elf __attribute__ ((unused));
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+ Elf *elf;
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GElf_Half machine __attribute__ ((unused));
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Ebl *eh;
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size_t ehlen;
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{
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+ int soft_float = 0;
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+
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/* Check whether the Elf_BH object has a sufficent size. */
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if (ehlen < sizeof (Ebl))
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return NULL;
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+ if (elf) {
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+ GElf_Ehdr ehdr_mem;
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+ GElf_Ehdr *ehdr = gelf_getehdr (elf, &ehdr_mem);
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+ if (ehdr && (ehdr->e_flags & EF_ARM_SOFT_FLOAT))
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+ soft_float = 1;
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+ }
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+
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/* We handle it. */
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eh->name = "ARM";
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arm_init_reloc (eh);
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@@ -58,7 +69,10 @@
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HOOK (eh, core_note);
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HOOK (eh, auxv_info);
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HOOK (eh, check_object_attribute);
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- HOOK (eh, return_value_location);
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+ if (soft_float)
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+ eh->return_value_location = arm_return_value_location_soft;
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+ else
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+ eh->return_value_location = arm_return_value_location_hard;
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return MODVERSION;
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}
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Index: elfutils-0.146/backends/arm_regs.c
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===================================================================
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--- elfutils-0.146.orig/backends/arm_regs.c 2009-04-21 14:50:01.000000000 +0000
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+++ elfutils-0.146/backends/arm_regs.c 2010-04-24 10:11:13.000000000 +0000
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@@ -28,6 +28,7 @@
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#endif
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#include <string.h>
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+#include <stdio.h>
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#include <dwarf.h>
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#define BACKEND arm_
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@@ -58,7 +59,15 @@
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namelen = 2;
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break;
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- case 10 ... 12:
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+ case 10 ... 11:
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+ name[0] = 'r';
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+ name[1] = '1';
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+ name[2] = regno % 10 + '0';
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+ namelen = 3;
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+ break;
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+
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+ case 12:
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+ *type = DW_ATE_unsigned;
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name[0] = 'r';
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name[1] = '1';
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name[2] = regno % 10 + '0';
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@@ -73,6 +82,9 @@
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break;
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case 16 + 0 ... 16 + 7:
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+ /* AADWARF says that there are no registers in that range,
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+ * but gcc maps FPA registers here
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+ */
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regno += 96 - 16;
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/* Fall through. */
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case 96 + 0 ... 96 + 7:
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@@ -84,11 +96,139 @@
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namelen = 2;
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break;
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+ case 64 + 0 ... 64 + 9:
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+ *setname = "VFP";
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+ *bits = 32;
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+ *type = DW_ATE_float;
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+ name[0] = 's';
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+ name[1] = regno - 64 + '0';
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+ namelen = 2;
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+ break;
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+
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+ case 64 + 10 ... 64 + 31:
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+ *setname = "VFP";
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+ *bits = 32;
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+ *type = DW_ATE_float;
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+ name[0] = 's';
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+ name[1] = (regno - 64) / 10 + '0';
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+ name[2] = (regno - 64) % 10 + '0';
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+ namelen = 3;
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+ break;
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+
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+ case 104 + 0 ... 104 + 7:
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+ /* XXX TODO:
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+ * This can be either intel wireless MMX general purpose/control
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+ * registers or xscale accumulator, which have different usage.
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+ * We only have the intel wireless MMX here now.
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+ * The name needs to be changed for the xscale accumulator too. */
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+ *setname = "MMX";
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+ *type = DW_ATE_unsigned;
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+ *bits = 32;
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+ memcpy(name, "wcgr", 4);
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+ name[4] = regno - 104 + '0';
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+ namelen = 5;
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+ break;
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+
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+ case 112 + 0 ... 112 + 9:
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+ *setname = "MMX";
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+ *type = DW_ATE_unsigned;
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+ *bits = 64;
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+ name[0] = 'w';
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+ name[1] = 'r';
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+ name[2] = regno - 112 + '0';
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+ namelen = 3;
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+ break;
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+
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+ case 112 + 10 ... 112 + 15:
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+ *setname = "MMX";
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+ *type = DW_ATE_unsigned;
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+ *bits = 64;
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+ name[0] = 'w';
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+ name[1] = 'r';
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+ name[2] = '1';
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+ name[3] = regno - 112 - 10 + '0';
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+ namelen = 4;
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+ break;
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+
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case 128:
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+ *setname = "special";
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*type = DW_ATE_unsigned;
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return stpcpy (name, "spsr") + 1 - name;
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+ case 129:
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+ *setname = "special";
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+ *type = DW_ATE_unsigned;
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+ return stpcpy(name, "spsr_fiq") + 1 - name;
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+
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+ case 130:
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+ *setname = "special";
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+ *type = DW_ATE_unsigned;
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+ return stpcpy(name, "spsr_irq") + 1 - name;
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+
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+ case 131:
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+ *setname = "special";
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+ *type = DW_ATE_unsigned;
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+ return stpcpy(name, "spsr_abt") + 1 - name;
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+
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+ case 132:
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+ *setname = "special";
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+ *type = DW_ATE_unsigned;
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+ return stpcpy(name, "spsr_und") + 1 - name;
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+
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+ case 133:
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+ *setname = "special";
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+ *type = DW_ATE_unsigned;
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+ return stpcpy(name, "spsr_svc") + 1 - name;
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+
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+ case 144 ... 150:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_usr", regno - 144 + 8) + 1;
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+
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+ case 151 ... 157:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_fiq", regno - 151 + 8) + 1;
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+
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+ case 158 ... 159:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_irq", regno - 158 + 13) + 1;
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+
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+ case 160 ... 161:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_abt", regno - 160 + 13) + 1;
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+
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+ case 162 ... 163:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_und", regno - 162 + 13) + 1;
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+
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+ case 164 ... 165:
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+ *setname = "integer";
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+ *type = DW_ATE_signed;
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+ *bits = 32;
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+ return sprintf(name, "r%d_svc", regno - 164 + 13) + 1;
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+
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+ case 192 ... 199:
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+ *setname = "MMX";
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+ *bits = 32;
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+ *type = DW_ATE_unsigned;
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+ name[0] = 'w';
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+ name[1] = 'c';
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+ name[2] = regno - 192 + '0';
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+ namelen = 3;
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+ break;
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+
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case 256 + 0 ... 256 + 9:
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+ /* XXX TODO: Neon also uses those registers and can contain
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+ * both float and integers */
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*setname = "VFP";
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*type = DW_ATE_float;
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*bits = 64;
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Index: elfutils-0.146/backends/arm_retval.c
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===================================================================
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--- elfutils-0.146.orig/backends/arm_retval.c 2010-01-12 16:57:54.000000000 +0000
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+++ elfutils-0.146/backends/arm_retval.c 2010-04-24 10:11:13.000000000 +0000
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@@ -45,6 +45,13 @@
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#define nloc_intreg 1
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#define nloc_intregs(n) (2 * (n))
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+/* f1 */ /* XXX TODO: f0 can also have number 96 if program was compiled with -mabi=aapcs */
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+static const Dwarf_Op loc_fpreg[] =
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+ {
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+ { .atom = DW_OP_reg16 },
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+ };
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+#define nloc_fpreg 1
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+
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/* The return value is a structure and is actually stored in stack space
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passed in a hidden argument by the caller. But, the compiler
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helpfully returns the address of that space in r0. */
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@@ -55,8 +62,9 @@
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#define nloc_aggregate 1
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-int
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-arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
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+static int
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+arm_return_value_location_ (Dwarf_Die *functypedie, const Dwarf_Op **locp,
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+ int soft_float)
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{
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/* Start with the function's type, and get the DW_AT_type attribute,
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which is the type of the return value. */
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@@ -109,14 +117,31 @@
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else
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return -1;
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}
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+ if (tag == DW_TAG_base_type)
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+ {
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+ Dwarf_Word encoding;
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+ if (dwarf_formudata (dwarf_attr_integrate (typedie, DW_AT_encoding,
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+ &attr_mem), &encoding) != 0)
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+ return -1;
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+
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+ if ((encoding == DW_ATE_float) && !soft_float)
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+ {
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+ *locp = loc_fpreg;
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+ if (size <= 8)
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+ return nloc_fpreg;
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+ goto aggregate;
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+ }
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+ }
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if (size <= 16)
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{
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intreg:
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*locp = loc_intreg;
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return size <= 4 ? nloc_intreg : nloc_intregs ((size + 3) / 4);
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}
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+ /* fall through. */
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aggregate:
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+ /* XXX TODO sometimes aggregates are returned in r0 (-mabi=aapcs) */
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*locp = loc_aggregate;
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return nloc_aggregate;
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@@ -135,3 +160,18 @@
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DWARF and might be valid. */
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return -2;
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}
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+
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+/* return location for -mabi=apcs-gnu -msoft-float */
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+int
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+arm_return_value_location_soft (Dwarf_Die *functypedie, const Dwarf_Op **locp)
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+{
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+ return arm_return_value_location_ (functypedie, locp, 1);
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+}
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+
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+/* return location for -mabi=apcs-gnu -mhard-float (current default) */
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+int
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+arm_return_value_location_hard (Dwarf_Die *functypedie, const Dwarf_Op **locp)
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+{
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+ return arm_return_value_location_ (functypedie, locp, 0);
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+}
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+
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Index: elfutils-0.146/libelf/elf.h
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===================================================================
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--- elfutils-0.146.orig/libelf/elf.h 2010-04-24 10:11:11.000000000 +0000
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+++ elfutils-0.146/libelf/elf.h 2010-04-24 10:11:13.000000000 +0000
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@@ -2290,6 +2290,9 @@
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#define EF_ARM_EABI_VER4 0x04000000
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#define EF_ARM_EABI_VER5 0x05000000
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+/* EI_OSABI values */
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+#define ELFOSABI_ARM_AEABI 64 /* Contains symbol versioning. */
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+
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/* Additional symbol types for Thumb. */
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#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
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#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
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@@ -2307,12 +2310,19 @@
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/* Processor specific values for the Phdr p_type field. */
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#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */
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+#define PT_ARM_UNWIND PT_ARM_EXIDX
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/* Processor specific values for the Shdr sh_type field. */
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#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */
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#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */
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#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */
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+/* Processor specific values for the Dyn d_tag field. */
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+#define DT_ARM_RESERVED1 (DT_LOPROC + 0)
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+#define DT_ARM_SYMTABSZ (DT_LOPROC + 1)
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+#define DT_ARM_PREEMTMAB (DT_LOPROC + 2)
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+#define DT_ARM_RESERVED2 (DT_LOPROC + 3)
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+#define DT_ARM_NUM 4
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/* ARM relocs. */
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@@ -2344,12 +2354,75 @@
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#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */
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#define R_ARM_GOT32 26 /* 32 bit GOT entry */
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#define R_ARM_PLT32 27 /* 32 bit PLT address */
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+#define R_ARM_CALL 28
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+#define R_ARM_JUMP24 29
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+#define R_ARM_THM_JUMP24 30
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+#define R_ARM_BASE_ABS 31
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#define R_ARM_ALU_PCREL_7_0 32
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#define R_ARM_ALU_PCREL_15_8 33
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#define R_ARM_ALU_PCREL_23_15 34
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#define R_ARM_LDR_SBREL_11_0 35
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#define R_ARM_ALU_SBREL_19_12 36
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#define R_ARM_ALU_SBREL_27_20 37
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+#define R_ARM_TARGET1 38
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+#define R_ARM_SBREL31 39
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+#define R_ARM_V4BX 40
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+#define R_ARM_TARGET2 41
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+#define R_ARM_PREL31 42
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+#define R_ARM_MOVW_ABS_NC 43
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+#define R_ARM_MOVT_ABS 44
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+#define R_ARM_MOVW_PREL_NC 45
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+#define R_ARM_MOVT_PREL 46
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+#define R_ARM_THM_MOVW_ABS_NC 47
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+#define R_ARM_THM_MOVT_ABS 48
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+#define R_ARM_THM_MOVW_PREL_NC 49
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+#define R_ARM_THM_MOVT_PREL 50
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+#define R_ARM_THM_JUMP19 51
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+#define R_ARM_THM_JUMP6 52
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+#define R_ARM_THM_ALU_PREL_11_0 53
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+#define R_ARM_THM_PC12 54
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+#define R_ARM_ABS32_NOI 55
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+#define R_ARM_REL32_NOI 56
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+#define R_ARM_ALU_PC_G0_NC 57
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+#define R_ARM_ALU_PC_G0 58
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+#define R_ARM_ALU_PC_G1_NC 59
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+#define R_ARM_ALU_PC_G1 60
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+#define R_ARM_ALU_PC_G2 61
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+#define R_ARM_LDR_PC_G1 62
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+#define R_ARM_LDR_PC_G2 63
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+#define R_ARM_LDRS_PC_G0 64
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+#define R_ARM_LDRS_PC_G1 65
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+#define R_ARM_LDRS_PC_G2 66
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+#define R_ARM_LDC_PC_G0 67
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+#define R_ARM_LDC_PC_G1 68
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+#define R_ARM_LDC_PC_G2 69
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+#define R_ARM_ALU_SB_G0_NC 70
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+#define R_ARM_ALU_SB_G0 71
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+#define R_ARM_ALU_SB_G1_NC 72
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+#define R_ARM_ALU_SB_G1 73
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+#define R_ARM_ALU_SB_G2 74
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+#define R_ARM_LDR_SB_G0 75
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+#define R_ARM_LDR_SB_G1 76
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+#define R_ARM_LDR_SB_G2 77
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+#define R_ARM_LDRS_SB_G0 78
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+#define R_ARM_LDRS_SB_G1 79
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+#define R_ARM_LDRS_SB_G2 80
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+#define R_ARM_LDC_G0 81
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+#define R_ARM_LDC_G1 82
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+#define R_ARM_LDC_G2 83
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+#define R_ARM_MOVW_BREL_NC 84
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+#define R_ARM_MOVT_BREL 85
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+#define R_ARM_MOVW_BREL 86
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+#define R_ARM_THM_MOVW_BREL_NC 87
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+#define R_ARM_THM_MOVT_BREL 88
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+#define R_ARM_THM_MOVW_BREL 89
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+/* 90-93 unallocated */
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+#define R_ARM_PLT32_ABS 94
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+#define R_ARM_GOT_ABS 95
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+#define R_ARM_GOT_PREL 96
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+#define R_ARM_GOT_BREL12 97
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+#define R_ARM_GOTOFF12 98
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+#define R_ARM_GOTRELAX 99
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#define R_ARM_GNU_VTENTRY 100
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#define R_ARM_GNU_VTINHERIT 101
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#define R_ARM_THM_PC11 102 /* thumb unconditional branch */
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@@ -2364,6 +2437,12 @@
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static TLS block offset */
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#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static
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TLS block */
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+#define R_ARM_TLS_LDO12 109
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+#define R_ARM_TLS_LE12 110
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|
+#define R_ARM_TLS_IE12GP 111
|
|
+/* 112 - 127 private range */
|
|
+#define R_ARM_ME_TOO 128 /* obsolete */
|
|
+
|
|
#define R_ARM_RXPC25 249
|
|
#define R_ARM_RSBREL32 250
|
|
#define R_ARM_THM_RPC22 251
|
|
Index: elfutils-0.146/backends/libebl_arm.h
|
|
===================================================================
|
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
|
+++ elfutils-0.146/backends/libebl_arm.h 2010-04-24 10:11:13.000000000 +0000
|
|
@@ -0,0 +1,9 @@
|
|
+#ifndef _LIBEBL_ARM_H
|
|
+#define _LIBEBL_ARM_H 1
|
|
+
|
|
+#include <libdw.h>
|
|
+
|
|
+extern int arm_return_value_location_soft(Dwarf_Die *, const Dwarf_Op **locp);
|
|
+extern int arm_return_value_location_hard(Dwarf_Die *, const Dwarf_Op **locp);
|
|
+
|
|
+#endif
|