2e7e072f58
Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
320 lines
13 KiB
Diff
320 lines
13 KiB
Diff
Adds support for Freescale Power architecture e300c2 and e300c3 cores.
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http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
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Leon Woestenberg <leonw@mailcan.com>
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---
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gcc/config.gcc | 2
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gcc/config/rs6000/e300c2c3.md | 189 ++++++++++++++++++++++++++++++++++++++++++
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gcc/config/rs6000/rs6000.c | 24 +++++
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gcc/config/rs6000/rs6000.h | 4
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gcc/config/rs6000/rs6000.md | 3
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5 files changed, 220 insertions(+), 2 deletions(-)
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Index: gcc-4.3.1/gcc/config/rs6000/e300c2c3.md
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ gcc-4.3.1/gcc/config/rs6000/e300c2c3.md 2008-08-23 16:51:33.000000000 -0700
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@@ -0,0 +1,189 @@
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+;; Pipeline description for Motorola PowerPC e300c3 core.
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+;; Copyright (C) 2003 Free Software Foundation, Inc.
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+;;
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+;; This file is part of GCC.
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+
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+;; GCC is free software; you can redistribute it and/or modify it
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+;; under the terms of the GNU General Public License as published
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+;; by the Free Software Foundation; either version 2, or (at your
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+;; option) any later version.
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+
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+;; GCC is distributed in the hope that it will be useful, but WITHOUT
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+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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+;; License for more details.
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+
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING. If not, write to the
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+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
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+;; MA 02111-1307, USA.
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+
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+(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
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+(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
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+
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+;; We don't simulate general issue queue (GIC). If we have SU insn
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+;; and then SU1 insn, they can not be issued on the same cycle
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+;; (although SU1 insn and then SU insn can be issued) because the SU
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+;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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+;; multipass insn scheduling will find the situation and issue the SU1
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+;; insn and then the SU insn.
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+(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
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+
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+;; We could describe completion buffers slots in combination with the
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+;; retirement units and the order of completion but the result
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+;; automaton would behave in the same way because we can not describe
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+;; real latency time with taking in order completion into account.
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+;; Actually we could define the real latency time by querying reserved
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+;; automaton units but the current scheduler uses latency time before
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+;; issuing insns and making any reservations.
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+;;
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+;; So our description is aimed to achieve a insn schedule in which the
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+;; insns would not wait in the completion buffer.
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+(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
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+
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+;; Branch unit:
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+(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
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+
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+;; IU:
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+(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
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+
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+;; IU: This used to describe non-pipelined division.
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+(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
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+
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+;; SRU:
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+(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
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+
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+;; Here we simplified LSU unit description not describing the stages.
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+(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
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+
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+;; FPU:
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+(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
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+
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+;; The following units are used to make automata deterministic
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+(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
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+(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
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+(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
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+(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
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+
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+;; The following sets to make automata deterministic when option ndfa is used.
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+(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
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+(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
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+(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
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+(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
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+
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+;; Some useful abbreviations.
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+(define_reservation "ppce300c3_decode"
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+ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
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+(define_reservation "ppce300c3_issue"
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+ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
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+(define_reservation "ppce300c3_retire"
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+ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
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+(define_reservation "ppce300c3_iu_stage0"
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+ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
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+
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+;; Compares can be executed either one of the IU or SRU
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+(define_insn_reservation "ppce300c3_cmp" 1
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+ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
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+ +ppce300c3_retire")
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+
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+;; Other one cycle IU insns
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+(define_insn_reservation "ppce300c3_iu" 1
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+ (and (eq_attr "type" "integer,insert_word")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
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+
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+;; Branch. Actually this latency time is not used by the scheduler.
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+(define_insn_reservation "ppce300c3_branch" 1
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+ (and (eq_attr "type" "jmpreg,branch")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
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+
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+;; Multiply is non-pipelined but can be executed in any IU
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+(define_insn_reservation "ppce300c3_multiply" 2
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+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
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+ ppce300c3_iu_stage0+ppce300c3_retire")
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+
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+;; Divide. We use the average latency time here. We omit reserving a
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+;; retire unit because of the result automata will be huge.
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+(define_insn_reservation "ppce300c3_divide" 20
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+ (and (eq_attr "type" "idiv")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
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+ ppce300c3_mu_div*19")
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+
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+;; CR logical
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+(define_insn_reservation "ppce300c3_cr_logical" 1
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+ (and (eq_attr "type" "cr_logical,delayed_cr")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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+
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+;; Mfcr
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+(define_insn_reservation "ppce300c3_mfcr" 1
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+ (and (eq_attr "type" "mfcr")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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+
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+;; Mtcrf
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+(define_insn_reservation "ppce300c3_mtcrf" 1
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+ (and (eq_attr "type" "mtcr")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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+
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+;; Mtjmpr
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+(define_insn_reservation "ppce300c3_mtjmpr" 1
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+ (and (eq_attr "type" "mtjmpr,mfjmpr")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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+
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+;; Float point instructions
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+(define_insn_reservation "ppce300c3_fpcompare" 3
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+ (and (eq_attr "type" "fpcompare")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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+
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+(define_insn_reservation "ppce300c3_fp" 3
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+ (and (eq_attr "type" "fp")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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+
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+(define_insn_reservation "ppce300c3_dmul" 4
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+ (and (eq_attr "type" "dmul")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
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+
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+; Divides are not pipelined
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+(define_insn_reservation "ppce300c3_sdiv" 18
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+ (and (eq_attr "type" "sdiv")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
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+
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+(define_insn_reservation "ppce300c3_ddiv" 33
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+ (and (eq_attr "type" "ddiv")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
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+
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+;; Loads
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+(define_insn_reservation "ppce300c3_load" 2
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+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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+
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+(define_insn_reservation "ppce300c3_fpload" 2
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+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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+
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+;; Stores.
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+(define_insn_reservation "ppce300c3_store" 2
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+ (and (eq_attr "type" "store,store_ux,store_u")
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+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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+
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+(define_insn_reservation "ppce300c3_fpstore" 2
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+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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+ (eq_attr "cpu" "ppce300c3"))
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+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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Index: gcc-4.3.1/gcc/config/rs6000/rs6000.c
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===================================================================
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--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.c 2008-08-23 16:49:39.000000000 -0700
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+++ gcc-4.3.1/gcc/config/rs6000/rs6000.c 2008-08-23 16:54:25.000000000 -0700
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@@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = {
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1, /* prefetch streams /*/
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};
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+/* Instruction costs on E300C2 and E300C3 cores. */
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+static const
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+struct processor_costs ppce300c2c3_cost = {
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+ COSTS_N_INSNS (4), /* mulsi */
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+ COSTS_N_INSNS (4), /* mulsi_const */
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+ COSTS_N_INSNS (4), /* mulsi_const9 */
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+ COSTS_N_INSNS (4), /* muldi */
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+ COSTS_N_INSNS (19), /* divsi */
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+ COSTS_N_INSNS (19), /* divdi */
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+ COSTS_N_INSNS (3), /* fp */
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+ COSTS_N_INSNS (4), /* dmul */
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+ COSTS_N_INSNS (18), /* sdiv */
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+ COSTS_N_INSNS (33), /* ddiv */
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+};
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+
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/* Instruction costs on POWER4 and POWER5 processors. */
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static const
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struct processor_costs power4_cost = {
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@@ -1420,6 +1435,8 @@ rs6000_override_options (const char *def
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{"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
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/* 8548 has a dummy entry for now. */
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{"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
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+ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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+ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
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{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"970", PROCESSOR_POWER4,
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POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
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@@ -1845,6 +1862,11 @@ rs6000_override_options (const char *def
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rs6000_cost = &ppc8540_cost;
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break;
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+ case PROCESSOR_PPCE300C2:
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+ case PROCESSOR_PPCE300C3:
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+ rs6000_cost = &ppce300c2c3_cost;
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+ break;
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+
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case PROCESSOR_POWER4:
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case PROCESSOR_POWER5:
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rs6000_cost = &power4_cost;
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@@ -18606,6 +18628,8 @@ rs6000_issue_rate (void)
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case CPU_PPC7400:
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case CPU_PPC8540:
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case CPU_CELL:
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+ case CPU_PPCE300C2:
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+ case CPU_PPCE300C3:
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return 2;
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case CPU_RIOS2:
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case CPU_PPC604:
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Index: gcc-4.3.1/gcc/config/rs6000/rs6000.h
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===================================================================
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--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.h 2008-01-26 09:18:35.000000000 -0800
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+++ gcc-4.3.1/gcc/config/rs6000/rs6000.h 2008-08-23 16:55:30.000000000 -0700
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@@ -117,6 +117,8 @@
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%{mcpu=G5: -mpower4 -maltivec} \
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%{mcpu=8540: -me500} \
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%{mcpu=8548: -me500} \
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+%{mcpu=e300c2: -mppc} \
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+%{mcpu=e300c3: -mppc -mpmr} \
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%{maltivec: -maltivec} \
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-many"
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@@ -262,6 +264,8 @@ enum processor_type
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PROCESSOR_PPC7400,
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PROCESSOR_PPC7450,
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PROCESSOR_PPC8540,
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+ PROCESSOR_PPCE300C2,
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+ PROCESSOR_PPCE300C3,
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PROCESSOR_POWER4,
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PROCESSOR_POWER5,
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PROCESSOR_POWER6,
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Index: gcc-4.3.1/gcc/config/rs6000/rs6000.md
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===================================================================
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--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.md 2008-02-13 16:14:45.000000000 -0800
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+++ gcc-4.3.1/gcc/config/rs6000/rs6000.md 2008-08-23 16:57:29.000000000 -0700
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@@ -133,7 +133,7 @@
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in rs6000.h.
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-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
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+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell,ppce300c2,ppce300c3"
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(const (symbol_ref "rs6000_cpu_attr")))
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@@ -166,6 +166,7 @@
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(include "7xx.md")
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(include "7450.md")
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(include "8540.md")
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+(include "e300c2c3.md")
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(include "power4.md")
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(include "power5.md")
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(include "power6.md")
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Index: gcc-4.3.1/gcc/config.gcc
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===================================================================
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--- gcc-4.3.1.orig/gcc/config.gcc 2008-08-23 16:49:43.000000000 -0700
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+++ gcc-4.3.1/gcc/config.gcc 2008-08-23 17:03:55.000000000 -0700
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@@ -3144,7 +3144,7 @@ case "${target}" in
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| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
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| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
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| 601 | 602 | 603 | 603e | ec603e | 604 \
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- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
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+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
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| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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# OK
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;;
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