497 lines
14 KiB
Diff
497 lines
14 KiB
Diff
From 1306abec905df1ff5cf2b1d91ac0d94d18d96c5b Mon Sep 17 00:00:00 2001
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From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
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Date: Fri, 20 Jul 2007 19:00:07 -0400
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Subject: [PATCH] cm-x270-it8152
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---
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arch/arm/common/Makefile | 1 +
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arch/arm/common/it8152.c | 272 +++++++++++++++++++++++++++++++++++++
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arch/arm/kernel/bios32.c | 28 ++++-
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include/asm-arm/hardware/it8152.h | 104 ++++++++++++++
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include/asm-arm/pci.h | 7 +
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include/linux/pci_ids.h | 1 +
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6 files changed, 410 insertions(+), 3 deletions(-)
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create mode 100644 arch/arm/common/it8152.c
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create mode 100644 include/asm-arm/hardware/it8152.h
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diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
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index e1289a2..3d0b9fa 100644
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--- a/arch/arm/common/Makefile
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+++ b/arch/arm/common/Makefile
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@@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_ARCH_IXP2000) += uengine.o
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obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
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+obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
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diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
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new file mode 100644
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index 0000000..8563610
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--- /dev/null
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+++ b/arch/arm/common/it8152.c
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@@ -0,0 +1,272 @@
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+/*
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+ * arch/arm/common/it8152.c: PCI functions for IT8152
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+ *
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+ * Compulab Ltd, 2002-2006
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+ *
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+ * The DMA bouncing is taken from arch/arm/mach-ixp4xx/common-pci.c
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+ * (see this file for respective copyrights)
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/sched.h>
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/ptrace.h>
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+#include <linux/interrupt.h>
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+#include <linux/mm.h>
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+#include <linux/slab.h>
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+#include <linux/init.h>
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+#include <linux/ioport.h>
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+#include <asm/mach/map.h>
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+
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+
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <asm/system.h>
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+#include <asm/mach/pci.h>
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+#include <asm/hardware/it8152.h>
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+
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+#define MAX_SLOTS 21
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+
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+static unsigned long
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+it8152_pci_dev_base_address(struct pci_bus *bus, unsigned int devfn)
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+{
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+ unsigned long addr = 0;
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+
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+ if (bus->number == 0) {
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+ if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
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+ addr = (devfn << 8);
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+ } else
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+ addr = (bus->number << 16) | (devfn << 8);
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+
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+ return addr;
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+}
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+
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+static int
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+it8152_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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+ int size, u32 *value)
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+{
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+ unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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+ u32 v;
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+ int shift;
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+
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+#ifdef CONFIG_MACH_ARMCORE
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+ if(devfn!=0) IT8152_GPIO_GPLR=0x00;
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+#endif
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+ shift = (where & 3);
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+
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+ IT8152_PCI_CFG_ADDR = (addr + where);
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+ v = (IT8152_PCI_CFG_DATA >> (8 * (shift)));
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+
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+ *value = v;
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+
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+#ifdef CONFIG_MACH_ARMCORE
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+ if(devfn!=0) IT8152_GPIO_GPLR=0x20;
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+#endif
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+
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+static int
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+it8152_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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+ int size, u32 value)
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+{
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+ unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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+ u32 v, vtemp, mask=0;
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+ int shift;
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+
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+#ifdef CONFIG_MACH_ARMCORE
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+ if(devfn!=0) IT8152_GPIO_GPLR=0x00;
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+#endif
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+
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+ if(size==1) mask=0xff;
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+ if(size==2) mask=0xffff;
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+
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+ shift = (where & 3);
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+
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+ IT8152_PCI_CFG_ADDR = addr + where;
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+ vtemp = IT8152_PCI_CFG_DATA;
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+
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+ if(mask) vtemp &= ~(mask << (8 * shift));
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+ else vtemp = 0;
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+
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+ v = (value << (8 * shift));
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+ IT8152_PCI_CFG_ADDR = addr + where;
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+ IT8152_PCI_CFG_DATA = (v | vtemp);
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+
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+#ifdef CONFIG_MACH_ARMCORE
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+ if(devfn!=0) IT8152_GPIO_GPLR=0x20;
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+#endif
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static struct pci_ops it8152_ops = {
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+ .read = it8152_pci_read_config,
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+ .write = it8152_pci_write_config,
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+};
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+
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+static struct resource it8152_io = {
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+ .name = "IT8152 PCI I/O region",
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static struct resource it8152_mem1 = {
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+ .name = "First IT8152 PCI memory region",
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+ .start = 0x10000000,
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+ .end = 0x13e00000,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+/*
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+ * The following functions are needed for DMA bouncing.
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+ * ITE8152 chip can addrees up to 64MByte, so all the devices
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+ * connected to ITE8152 (PCI and USB) should have limited DMA window
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+ */
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+
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+/*
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+ * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
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+ * other devices.
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+ */
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+static int it8152_pci_platform_notify(struct device *dev)
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+{
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+ if ( dev->bus == &pci_bus_type ) {
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+ if ( dev->dma_mask )
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+ *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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+ dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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+ dmabounce_register_dev(dev, 2048, 4096);
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+ }
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+ return 0;
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+}
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+
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+static int it8152_pci_platform_notify_remove(struct device *dev)
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+{
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+ if ( dev->bus == &pci_bus_type ) {
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+ dmabounce_unregister_dev(dev);
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+ }
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+ return 0;
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+}
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+
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+int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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+{
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+ dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
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+ __FUNCTION__, dma_addr, size);
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+ return (dev->bus == &pci_bus_type ) &&
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+ ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
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+}
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+
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+/*
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+ * Only first 64MB of memory can be accessed via PCI.
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+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
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+ * This is really ugly and we need a better way of specifying
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+ * DMA-capable regions of memory.
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+ */
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+void __init it8152_adjust_zones(int node, unsigned long *zone_size,
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+ unsigned long *zhole_size)
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+{
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+ unsigned int sz = SZ_64M >> PAGE_SHIFT;
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+
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+ /*
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+ * Only adjust if > 64M on current system
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+ */
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+ if (node || (zone_size[0] <= sz))
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+ return;
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+
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+ zone_size[1] = zone_size[0] - sz;
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+ zone_size[0] = sz;
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+ zhole_size[1] = zhole_size[0];
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+ zhole_size[0] = 0;
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+}
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+
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+/*
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+ * We override these so we properly do dmabounce otherwise drivers
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+ * are able to set the dma_mask to 0xffffffff and we can no longer
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+ * trap bounces. :(
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+ *
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+ * We just return true on everyhing except for < 64MB in which case
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+ * we will fail miseralby and die since we can't handle that case.
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+ */
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+int
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+pci_set_dma_mask(struct pci_dev *dev, u64 mask)
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+{
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+ printk(KERN_INFO "===> %s: %s %x\n", __FUNCTION__, dev->dev.bus_id, mask);
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+ if (mask >= PHYS_OFFSET + SZ_64M - 1 )
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+ return 0;
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+
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+ return -EIO;
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+}
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+
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+int
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+pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
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+{
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+ printk(KERN_INFO "===> %s: %s %x\n", __FUNCTION__, dev->dev.bus_id, mask);
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+ if (mask >= PHYS_OFFSET + SZ_64M - 1 )
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+ return 0;
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+
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+ return -EIO;
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+}
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+
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+EXPORT_SYMBOL(pci_set_dma_mask);
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+EXPORT_SYMBOL(pci_set_consistent_dma_mask);
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+
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+
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+int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
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+{
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+ it8152_io.start = IT8152_IO_BASE + 0x12000;
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+ it8152_io.end = IT8152_IO_BASE + 0x100000;
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+
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+ if (request_resource(&ioport_resource, &it8152_io)) {
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+ printk(KERN_ERR "PCI: unable to allocate IO region\n");
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+ return -EBUSY;
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+ }
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+ if (request_resource(&iomem_resource, &it8152_mem1)) {
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+ printk(KERN_ERR "PCI: unable to allocate memory region\n");
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+ return -EBUSY;
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+ }
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+
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+ sys->resource[0] = &it8152_io;
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+ sys->resource[1] = &it8152_mem1;
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+
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+ if (platform_notify || platform_notify_remove) {
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+ printk(KERN_ERR "PCI: Can't use platform_notify\n");
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+ return -EBUSY;
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+ }
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+
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+ platform_notify = it8152_pci_platform_notify;
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+ platform_notify_remove = it8152_pci_platform_notify_remove;
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+
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+ return 1;
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+}
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+
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+/*
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+ * If we set up a device for bus mastering, we need to check the latency
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+ * timer as we don't have even crappy BIOSes to set it properly.
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+ * The implementation is from arch/i386/pci/i386.c
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+ */
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+unsigned int pcibios_max_latency = 255;
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+
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+void pcibios_set_master(struct pci_dev *dev)
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+{
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+ u8 lat;
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+
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+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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+ if (lat < 16)
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+ lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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+ else if (lat > pcibios_max_latency)
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+ lat = pcibios_max_latency;
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+ else
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+ return;
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+ printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
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+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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+}
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+
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+
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+struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
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+{
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+ return pci_scan_bus(nr, &it8152_ops, sys);
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+}
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+
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diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
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index 240c448..d8d2352 100644
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--- a/arch/arm/kernel/bios32.c
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+++ b/arch/arm/kernel/bios32.c
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@@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
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+static void __init pci_fixup_it8152(struct pci_dev *dev)
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+{
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+ int i;
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+ /* fixup for ITE 8152 devices */
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+ /* FIXME: add defines for class 0x68000 and 0x80103 */
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+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
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+ dev->class == 0x68000 ||
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+ dev->class == 0x80103) {
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+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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+ dev->resource[i].start = 0;
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+ dev->resource[i].end = 0;
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+ dev->resource[i].flags = 0;
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+ }
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+ }
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+}
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
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+
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+
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+
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void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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if (debug_pci)
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@@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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*/
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static inline int pdev_bad_for_parity(struct pci_dev *dev)
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{
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- return (dev->vendor == PCI_VENDOR_ID_INTERG &&
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- (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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- dev->device == PCI_DEVICE_ID_INTERG_2010));
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+ return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
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+ (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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+ dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
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+ (dev->vendor == PCI_VENDOR_ID_ITE &&
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+ dev->device == PCI_DEVICE_ID_ITE_8152));
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+
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}
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/*
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diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
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new file mode 100644
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index 0000000..d28210d
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--- /dev/null
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+++ b/include/asm-arm/hardware/it8152.h
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@@ -0,0 +1,104 @@
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+/*
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+ * arch/arm/mach-pxa/it8152.h
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+ *
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+ * Compulab Ltd., 2006
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+ *
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+ * ITE 8152 companion chip definitions
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+ */
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+
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+
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+/* #define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) */
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+
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+
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+extern unsigned long it8152_base_address;
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+
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+#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
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+#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
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+
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+/* #define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) */
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+
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+#define IT8152_SHORT_IO(x) (*((volatile unsigned short *)(IT8152_CFGREG_BASE+(x))))
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+#define IT8152_LONG_IO(x) (*((volatile unsigned long *)(IT8152_CFGREG_BASE+(x))))
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+
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+
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+#define IT8152_PCI_MEMBASE (*((volatile unsigned long *)(it8152_base_address)))
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+/* #define IT8152_PCI_IOBASE (*((volatile unsigned long *)(it8152_base_address + 0x3e00000))) */
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+
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+#define IT8152_PCI_IACK (*((volatile unsigned long *)(it8152_base_address + 0x3f00808)))
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+#define IT8152_PCI_CFG_ADDR (*((volatile unsigned long *)(it8152_base_address + 0x3f00800)))
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+#define IT8152_PCI_CFG_DATA (*((volatile unsigned long *)(it8152_base_address + 0x3f00804)))
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+
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+#define IT_BUSNUM_SHF 16
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+#define IT_DEVNUM_SHF 11
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+#define IT_FUNCNUM_SHF 8
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+#define IT_REGNUM_SHF 2
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+
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+/* Power management & PLL registers */
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+#define IT8152_PMPLL_DSR IT8152_LONG_IO(0x00)
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+#define IT8152_PMPLL_DSSR IT8152_LONG_IO(0x04)
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+#define IT8152_PMPLL_PLLCR IT8152_LONG_IO(0x20)
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+#define IT8152_PMPLL_MFSR IT8152_LONG_IO(0x24)
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+
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+/* Memory controller */
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+#define IT8152_MC_REG_OFFSET 0x100
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+
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+#define IT8152_MC_SDCR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x00)
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+#define IT8152_MC_PCICR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x04)
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+
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+/* Interrupt related definitions */
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+#define IT8152_INTC_REG_OFFSET 0x300
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+
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+#define IT8152_INTC_LDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x00)
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+#define IT8152_INTC_LDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x04)
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+#define IT8152_INTC_LDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x08)
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+#define IT8152_INTC_LDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x0C)
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+#define IT8152_INTC_LDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x10)
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+#define IT8152_INTC_LDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x14)
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+#define IT8152_INTC_LPCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x20)
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+#define IT8152_INTC_LPPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x24)
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+#define IT8152_INTC_LPCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x28)
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+#define IT8152_INTC_LPPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x2C)
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+#define IT8152_INTC_LPNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x30)
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+#define IT8152_INTC_LPNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x34)
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+#define IT8152_INTC_PDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x40)
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+#define IT8152_INTC_PDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x44)
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+#define IT8152_INTC_PDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x48)
|
|
+#define IT8152_INTC_PDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x4C)
|
|
+#define IT8152_INTC_PDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x50)
|
|
+#define IT8152_INTC_PDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x54)
|
|
+#define IT8152_INTC_INTC_TYPER IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0xFC)
|
|
+
|
|
+#define IT8152_UART_BASE IT8152_LONG_IO(0x200)
|
|
+
|
|
+#define IT8152_GPIO_REG_OFFSET 0x500
|
|
+
|
|
+#define IT8152_GPIO_GPLR IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET)
|
|
+#define IT8152_GPIO_GPCR12 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x04)
|
|
+#define IT8152_GPIO_GPCR34 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x08)
|
|
+
|
|
+
|
|
+/* Interrupt bit definitions */
|
|
+#define PCISERR_BIT (1<<14)
|
|
+#define H2PTADR_BIT (1<<13)
|
|
+#define H2PMAR_BIT (1<<12)
|
|
+#define PCI_INTD_BIT (1<<11)
|
|
+#define PCI_INTC_BIT (1<<10)
|
|
+#define PCI_INTB_BIT (1<<9)
|
|
+#define PCI_INTA_BIT (1<<8)
|
|
+#define CDMA_INT_BIT (1<<2)
|
|
+#define USB_INT_BIT (1<<1)
|
|
+#define AUDIO_INT_BIT (1<<0)
|
|
+
|
|
+/* IT8152 UART */
|
|
+#define ITESER_BIT (1<<5)
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
|
|
index f21abd4..2cf30bf 100644
|
|
--- a/include/asm-arm/pci.h
|
|
+++ b/include/asm-arm/pci.h
|
|
@@ -8,10 +8,17 @@
|
|
|
|
#define pcibios_scan_all_fns(a, b) 0
|
|
|
|
+#ifdef CONFIG_PCI_HOST_ITE8152
|
|
+/* ITE bridge requires setting latency timer to avoid early bus access
|
|
+ termination by PIC bus mater devices
|
|
+*/
|
|
+extern void pcibios_set_master(struct pci_dev *dev);
|
|
+#else
|
|
static inline void pcibios_set_master(struct pci_dev *dev)
|
|
{
|
|
/* No special bus mastering setup handling */
|
|
}
|
|
+#endif
|
|
|
|
static inline void pcibios_penalize_isa_irq(int irq, int active)
|
|
{
|
|
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
|
|
index 5b1c999..b4c81d5 100644
|
|
--- a/include/linux/pci_ids.h
|
|
+++ b/include/linux/pci_ids.h
|
|
@@ -1650,6 +1650,7 @@
|
|
#define PCI_DEVICE_ID_ITE_8211 0x8211
|
|
#define PCI_DEVICE_ID_ITE_8212 0x8212
|
|
#define PCI_DEVICE_ID_ITE_8213 0x8213
|
|
+#define PCI_DEVICE_ID_ITE_8152 0x8152
|
|
#define PCI_DEVICE_ID_ITE_8872 0x8872
|
|
#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
|
|
|
|
--
|
|
1.5.1.6
|
|
|