451 lines
14 KiB
Diff
451 lines
14 KiB
Diff
From: "Rajendra Nayak" <rnayak@ti.com>
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To: <linux-omap@vger.kernel.org>
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Subject: [PATCH 01/02] OMAP3 CPUidle driver
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Date: Tue, 10 Jun 2008 12:39:00 +0530
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This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
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before it queries the governor for the next state.
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Signed-off-by: Rajendra Nayak <rnayak@ti.com>
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---
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arch/arm/mach-omap2/Makefile | 2
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arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
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arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
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arch/arm/mach-omap2/pm34xx.c | 5
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drivers/cpuidle/cpuidle.c | 10 +
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5 files changed, 359 insertions(+), 2 deletions(-)
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Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
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===================================================================
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--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
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+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
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@@ -20,7 +20,7 @@ obj-y += pm.o
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obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
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obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
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obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
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-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
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+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
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obj-$(CONFIG_PM_DEBUG) += pm-debug.o
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endif
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Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
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@@ -0,0 +1,293 @@
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+/*
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+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
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+ *
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+ * OMAP3 CPU IDLE Routines
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+ *
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+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
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+ * Rajendra Nayak <rnayak@ti.com>
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+ *
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+ * Copyright (C) 2007 Texas Instruments, Inc.
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+ * Karthik Dasu <karthik-dp@ti.com>
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+ *
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+ * Copyright (C) 2006 Nokia Corporation
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+ * Tony Lindgren <tony@atomide.com>
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+ *
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+ * Copyright (C) 2005 Texas Instruments, Inc.
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/cpuidle.h>
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+#include <asm/arch/pm.h>
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+#include <asm/arch/prcm.h>
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+#include <asm/arch/powerdomain.h>
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+#include <asm/arch/clockdomain.h>
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+#include <asm/arch/irqs.h>
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+#include "cpuidle34xx.h"
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+
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+#ifdef CONFIG_CPU_IDLE
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+
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+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
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+struct omap3_processor_cx current_cx_state;
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+
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+static int omap3_idle_bm_check(void)
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+{
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+ /* Check for omap3_fclks_active() here once available */
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+ return 0;
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+}
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+
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+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
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+ * returns the total time during which the system was idle.
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+ */
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+static int omap3_enter_idle(struct cpuidle_device *dev,
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+ struct cpuidle_state *state)
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+{
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+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
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+ struct timespec ts_preidle, ts_postidle, ts_idle;
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+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
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+ int neon_pwrst;
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+
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+ current_cx_state = *cx;
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+
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+ if (cx->type == OMAP3_STATE_C0) {
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+ /* Do nothing for C0, not even a wfi */
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+ return 0;
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+ }
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+
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+ /* Used to keep track of the total time in idle */
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+ getnstimeofday(&ts_preidle);
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+
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+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
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+ core_pd = pwrdm_lookup("core_pwrdm");
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+ per_pd = pwrdm_lookup("per_pwrdm");
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+ neon_pd = pwrdm_lookup("neon_pwrdm");
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+
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+ /* Reset previous power state registers */
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+ pwrdm_clear_all_prev_pwrst(mpu_pd);
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+ pwrdm_clear_all_prev_pwrst(neon_pd);
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+ pwrdm_clear_all_prev_pwrst(core_pd);
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+ pwrdm_clear_all_prev_pwrst(per_pd);
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+
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+ if (omap_irq_pending())
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+ return 0;
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+
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+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
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+
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+ /* Program MPU/NEON to target state */
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+ if (cx->mpu_state < PWRDM_POWER_ON) {
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+ if (neon_pwrst == PWRDM_POWER_ON) {
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+ if (cx->mpu_state == PWRDM_POWER_RET)
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+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
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+ else if (cx->mpu_state == PWRDM_POWER_OFF)
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+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
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+ }
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+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
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+ }
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+
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+ /* Program CORE to target state */
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+ if (cx->core_state < PWRDM_POWER_ON)
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+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
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+
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+ /* Execute ARM wfi */
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+ omap_sram_idle();
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+
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+ /* Program MPU/NEON to ON */
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+ if (cx->mpu_state < PWRDM_POWER_ON) {
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+ if (neon_pwrst == PWRDM_POWER_ON)
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+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
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+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
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+ }
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+
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+ if (cx->core_state < PWRDM_POWER_ON)
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+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
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+
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+ getnstimeofday(&ts_postidle);
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+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
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+ return timespec_to_ns(&ts_idle);
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+}
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+
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+/*
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+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
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+ *
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+ * This function checks for all the pre-requisites needed for OMAP3 to enter
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+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
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+ * C state.
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+ */
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+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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+ struct cpuidle_state *state)
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+{
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+ struct cpuidle_state *new_state = NULL;
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+ int i, j;
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+
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+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
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+
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+ /* Find current state in list */
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+ for (i = 0; i < OMAP3_MAX_STATES; i++)
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+ if (state == &dev->states[i])
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+ break;
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+ BUG_ON(i == OMAP3_MAX_STATES);
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+
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+ /* Back up to non 'CHECK_BM' state */
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+ for (j = i - 1; j > 0; j--) {
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+ struct cpuidle_state *s = &dev->states[j];
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+
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+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
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+ new_state = s;
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+ break;
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+ }
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+ }
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+
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+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
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+ __FUNCTION__, new_state->name, state->name);
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+ }
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+
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+ return omap3_enter_idle(dev, new_state ? : state);
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+}
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+
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+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
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+
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+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
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+ * Below is the desciption of each C state.
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+ *
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+ C0 . System executing code
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+ C1 . MPU WFI + Core active
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+ C2 . MPU CSWR + Core active
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+ C3 . MPU OFF + Core active
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+ C4 . MPU CSWR + Core CSWR
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+ C5 . MPU OFF + Core CSWR
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+ C6 . MPU OFF + Core OFF
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+ */
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+void omap_init_power_states(void)
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+{
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+ /* C0 . System executing code */
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+ omap3_power_states[0].valid = 1;
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+ omap3_power_states[0].type = OMAP3_STATE_C0;
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+ omap3_power_states[0].sleep_latency = 0;
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+ omap3_power_states[0].wakeup_latency = 0;
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+ omap3_power_states[0].threshold = 0;
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+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
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+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
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+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_SHALLOW;
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+
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+ /* C1 . MPU WFI + Core active */
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+ omap3_power_states[1].valid = 1;
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+ omap3_power_states[1].type = OMAP3_STATE_C1;
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+ omap3_power_states[1].sleep_latency = 10;
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+ omap3_power_states[1].wakeup_latency = 10;
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+ omap3_power_states[1].threshold = 30;
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+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
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+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
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+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_SHALLOW;
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+
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+ /* C2 . MPU CSWR + Core active */
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+ omap3_power_states[2].valid = 1;
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+ omap3_power_states[2].type = OMAP3_STATE_C2;
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+ omap3_power_states[2].sleep_latency = 50;
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+ omap3_power_states[2].wakeup_latency = 50;
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+ omap3_power_states[2].threshold = 300;
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+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
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+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
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+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_BALANCED;
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+
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+ /* C3 . MPU OFF + Core active */
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+ omap3_power_states[3].valid = 0;
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+ omap3_power_states[3].type = OMAP3_STATE_C3;
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+ omap3_power_states[3].sleep_latency = 1500;
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+ omap3_power_states[3].wakeup_latency = 1800;
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+ omap3_power_states[3].threshold = 4000;
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+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
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+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
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+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_BALANCED;
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+
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+ /* C4 . MPU CSWR + Core CSWR*/
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+ omap3_power_states[4].valid = 1;
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+ omap3_power_states[4].type = OMAP3_STATE_C4;
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+ omap3_power_states[4].sleep_latency = 2500;
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+ omap3_power_states[4].wakeup_latency = 7500;
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+ omap3_power_states[4].threshold = 12000;
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+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
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+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
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+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
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+
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+ /* C5 . MPU OFF + Core CSWR */
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+ omap3_power_states[5].valid = 0;
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+ omap3_power_states[5].type = OMAP3_STATE_C5;
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+ omap3_power_states[5].sleep_latency = 3000;
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+ omap3_power_states[5].wakeup_latency = 8500;
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+ omap3_power_states[5].threshold = 15000;
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+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
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+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
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+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
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+
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+ /* C6 . MPU OFF + Core OFF */
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+ omap3_power_states[6].valid = 0;
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+ omap3_power_states[6].type = OMAP3_STATE_C6;
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+ omap3_power_states[6].sleep_latency = 10000;
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+ omap3_power_states[6].wakeup_latency = 30000;
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+ omap3_power_states[6].threshold = 300000;
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+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
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+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
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+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
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+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
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+}
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+
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+struct cpuidle_driver omap3_idle_driver = {
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+ .name = "omap3_idle",
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+ .owner = THIS_MODULE,
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+};
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+/*
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+ * omap3_idle_init - Init routine for OMAP3 idle.
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+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
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+ * with the valid set of states.
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+ */
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+int omap3_idle_init(void)
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+{
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+ int i, count = 0;
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+ struct omap3_processor_cx *cx;
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+ struct cpuidle_state *state;
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+ struct cpuidle_device *dev;
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+
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+ omap_init_power_states();
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+ cpuidle_register_driver(&omap3_idle_driver);
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+
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+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
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+
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+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
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+ cx = &omap3_power_states[i];
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+ state = &dev->states[count];
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+
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+ if (!cx->valid)
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+ continue;
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+ cpuidle_set_statedata(state, cx);
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+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
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+ state->target_residency = cx->threshold;
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+ state->flags = cx->flags;
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+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
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+ omap3_enter_idle_bm : omap3_enter_idle;
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+ sprintf(state->name, "C%d", count+1);
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+ count++;
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+ }
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+
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+ if (!count)
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+ return -EINVAL;
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+ dev->state_count = count;
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+
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+ if (cpuidle_register_device(dev)) {
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+ printk(KERN_ERR "%s: CPUidle register device failed\n",
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+ __FUNCTION__);
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+ return -EIO;
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+ }
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+
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+ return 0;
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+}
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+__initcall(omap3_idle_init);
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+#endif /* CONFIG_CPU_IDLE */
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Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
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@@ -0,0 +1,51 @@
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+/*
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+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
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+ *
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+ * OMAP3 cpuidle structure definitions
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+ *
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+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
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+ * Written by Rajendra Nayak <rnayak@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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+ *
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+ * History:
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+ *
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+ */
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+
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+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
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+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
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+
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+#define OMAP3_MAX_STATES 7
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+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
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+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
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+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
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+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
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+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
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+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
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+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
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+
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+extern void omap_sram_idle(void);
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+extern int omap3_irq_pending(void);
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+
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+struct omap3_processor_cx {
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+ u8 valid;
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+ u8 type;
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+ u32 sleep_latency;
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+ u32 wakeup_latency;
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+ u32 mpu_state;
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+ u32 core_state;
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+ u32 threshold;
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+ u32 flags;
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+};
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+
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+void omap_init_power_states(void);
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+int omap3_idle_init(void);
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+
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+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
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+
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Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
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===================================================================
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--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
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+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
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@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
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return IRQ_HANDLED;
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}
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-static void omap_sram_idle(void)
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+void omap_sram_idle(void)
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|
{
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|
/* Variable to tell what needs to be saved and restored
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* in omap_sram_idle*/
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|
@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
|
|
|
|
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
|
|
switch (mpu_next_state) {
|
|
+ case PWRDM_POWER_ON:
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|
case PWRDM_POWER_RET:
|
|
/* No need to save context */
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|
save_state = 0;
|
|
@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
|
|
|
|
prcm_setup_regs();
|
|
|
|
+#ifndef CONFIG_CPU_IDLE
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|
pm_idle = omap3_pm_idle;
|
|
+#endif
|
|
|
|
err1:
|
|
return ret;
|
|
Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
|
|
===================================================================
|
|
--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
|
|
+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
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|
@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
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|
return;
|
|
}
|
|
|
|
+#ifdef CONFIG_ARCH_OMAP3
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|
+ local_irq_disable();
|
|
+ local_fiq_disable();
|
|
+#endif
|
|
+
|
|
/* ask the governor for the next state */
|
|
next_state = cpuidle_curr_governor->select(dev);
|
|
if (need_resched())
|
|
@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
|
|
target_state->time += (unsigned long long)dev->last_residency;
|
|
target_state->usage++;
|
|
|
|
+#ifdef CONFIG_ARCH_OMAP3
|
|
+ local_irq_enable();
|
|
+ local_fiq_enable();
|
|
+#endif
|
|
+
|
|
/* give the governor an opportunity to reflect on the outcome */
|
|
if (cpuidle_curr_governor->reflect)
|
|
cpuidle_curr_governor->reflect(dev);
|
|
|
|
--
|
|
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