279 lines
9.7 KiB
Diff
279 lines
9.7 KiB
Diff
TWL4030: use symbolic ISR/IMR register names during twl_init_irq()
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From: Paul Walmsley <paul@pwsan.com>
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twl_init_irq() uses a bunch of magic numbers as register indices; this
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has already led to several errors, fixed earlier in this patch series.
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Now use descriptive macros instead of magic numbers. This patch should
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not change kernel behavior.
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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---
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drivers/i2c/chips/twl4030-core.c | 188 +++++++++++++++++++-------------------
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1 files changed, 96 insertions(+), 92 deletions(-)
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diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
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index 99cc143..38c227a 100644
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--- a/drivers/i2c/chips/twl4030-core.c
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+++ b/drivers/i2c/chips/twl4030-core.c
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@@ -40,6 +40,9 @@
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#include <linux/i2c.h>
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#include <linux/i2c/twl4030.h>
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+#include <linux/i2c/twl4030-gpio.h>
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+#include <linux/i2c/twl4030-madc.h>
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+#include <linux/i2c/twl4030-pwrirq.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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@@ -114,6 +117,23 @@
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#define TWL4030_BASEADD_RTC 0x001C
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#define TWL4030_BASEADD_SECURED_REG 0x0000
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+/* TWL4030 BCI registers */
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+#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
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+#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
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+#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
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+#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
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+#define TWL4030_INTERRUPTS_BCIISR1A 0x0
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+#define TWL4030_INTERRUPTS_BCIISR2A 0x1
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+#define TWL4030_INTERRUPTS_BCIISR1B 0x4
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+#define TWL4030_INTERRUPTS_BCIISR2B 0x5
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+
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+/* TWL4030 keypad registers */
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+#define TWL4030_KEYPAD_KEYP_IMR1 0x12
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+#define TWL4030_KEYPAD_KEYP_IMR2 0x14
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+#define TWL4030_KEYPAD_KEYP_ISR1 0x11
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+#define TWL4030_KEYPAD_KEYP_ISR2 0x13
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+
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+
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/* Triton Core internal information (END) */
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/* Few power values */
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@@ -133,12 +153,10 @@
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/* on I2C-1 for 2430SDP */
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#define CONFIG_I2C_TWL4030_ID 1
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-/* SIH_CTRL registers */
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-#define TWL4030_INT_PWR_SIH_CTRL 0x07
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+/* SIH_CTRL registers that aren't defined elsewhere */
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#define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
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#define TWL4030_MADC_MADC_SIH_CTRL 0x67
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#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
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-#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
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#define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
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@@ -776,135 +794,121 @@ static void twl_init_irq(void)
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* handlers present.
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*/
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-
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- /* PWR_IMR1 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0);
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-
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- /* PWR_IMR2 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0);
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-
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- /* Clear off any other pending interrupts on power */
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+ /* Mask INT (PWR) interrupts at TWL4030 */
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
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+ TWL4030_INT_PWR_IMR1) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
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+ TWL4030_INT_PWR_IMR2) < 0);
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/* Are PWR interrupt status bits cleared by reads or writes? */
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cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
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TWL4030_INT_PWR_SIH_CTRL);
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WARN_ON(cor < 0);
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- /* PWR_ISR1 */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
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-
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- /* PWR_ISR2 */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
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+ /* Clear TWL4030 INT (PWR) ISRs */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
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+ TWL4030_INT_PWR_ISR1, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
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+ TWL4030_INT_PWR_ISR2, cor) < 0);
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/* Slave address 0x4A */
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- /* BCIIMR1A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0);
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-
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- /* BCIIMR2A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0);
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-
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- /* BCIIMR2A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0);
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-
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- /* BCIIMR2B */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0);
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+ /* Mask BCI interrupts at TWL4030 */
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
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+ TWL4030_INTERRUPTS_BCIIMR1A) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
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+ TWL4030_INTERRUPTS_BCIIMR2A) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
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+ TWL4030_INTERRUPTS_BCIIMR1B) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
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+ TWL4030_INTERRUPTS_BCIIMR2B) < 0);
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/* Are BCI interrupt status bits cleared by reads or writes? */
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cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
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TWL4030_INTERRUPTS_BCISIHCTRL);
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WARN_ON(cor < 0);
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- /* BCIISR1A */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
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-
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- /* BCIISR2A */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
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-
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- /* BCIISR1B */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
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-
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- /* BCIISR2B */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
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+ /* Clear TWL4030 BCI ISRs */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
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+ TWL4030_INTERRUPTS_BCIISR1A, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
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+ TWL4030_INTERRUPTS_BCIISR2A, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
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+ TWL4030_INTERRUPTS_BCIISR1B, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
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+ TWL4030_INTERRUPTS_BCIISR2B, cor) < 0);
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/* MAD C */
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- /* MADC_IMR1 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0);
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-
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- /* MADC_IMR2 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0);
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+ /* Mask MADC interrupts at TWL4030 */
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
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+ TWL4030_MADC_IMR1) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
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+ TWL4030_MADC_IMR2) < 0);
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/* Are MADC interrupt status bits cleared by reads or writes? */
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cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
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TWL4030_MADC_MADC_SIH_CTRL);
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WARN_ON(cor < 0);
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- /* MADC_ISR1 */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
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-
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- /* MADC_ISR2 */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
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+ /* Clear TWL4030 MADC ISRs */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
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+ TWL4030_MADC_ISR1, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
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+ TWL4030_MADC_ISR2, cor) < 0);
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/* key Pad */
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- /* KEYPAD - IMR1 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0);
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+ /* Mask keypad interrupts at TWL4030 */
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
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+ TWL4030_KEYPAD_KEYP_IMR1) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
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+ TWL4030_KEYPAD_KEYP_IMR2) < 0);
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/* Are keypad interrupt status bits cleared by reads or writes? */
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cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
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TWL4030_KEYPAD_KEYP_SIH_CTRL);
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WARN_ON(cor < 0);
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- /* KEYPAD - ISR1 */
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+ /* Clear TWL4030 keypad ISRs */
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/* XXX does this still need to be done twice for some reason? */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
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-
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- /* KEYPAD - IMR2 */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0);
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-
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- /* KEYPAD - ISR2 */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
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+ TWL4030_KEYPAD_KEYP_ISR1, cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
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+ TWL4030_KEYPAD_KEYP_ISR2, cor) < 0);
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/* Slave address 0x49 */
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- /* GPIO_IMR1A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0);
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-
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- /* GPIO_IMR2A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0);
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-
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- /* GPIO_IMR3A */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0);
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-
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- /* GPIO_IMR1B */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0);
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- /* GPIO_IMR2B */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0);
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-
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- /* GPIO_IMR3B */
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- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0);
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+ /* Mask GPIO interrupts at TWL4030 */
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR1A) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR2A) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR3A) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR1B) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR2B) < 0);
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+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
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+ REG_GPIO_IMR3B) < 0);
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/* Are GPIO interrupt status bits cleared by reads or writes? */
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cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
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- TWL4030_GPIO_GPIO_SIH_CTRL);
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+ REG_GPIO_SIH_CTRL);
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WARN_ON(cor < 0);
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- /* GPIO_ISR1A */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
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-
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- /* GPIO_ISR2A */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
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-
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- /* GPIO_ISR3A */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
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-
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- /* GPIO_ISR1B */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
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-
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- /* GPIO_ISR2B */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
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-
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- /* GPIO_ISR3B */
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- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
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+ /* Clear TWL4030 GPIO ISRs */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A,
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+ cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A,
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+ cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A,
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+ cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B,
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+ cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B,
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+ cor) < 0);
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B,
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+ cor) < 0);
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/* install an irq handler for each of the PIH modules */
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for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
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