239 lines
7.4 KiB
Diff
239 lines
7.4 KiB
Diff
On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote:
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> Catalin Marinas wrote:
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> > But, anyway, if you want a patch, Harry is updating it to a recent
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> > kernel.
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>
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> Any news on this? I think there are some people wanting a patch ;)
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See below for a preliminary patch updated to 2.6.26-rc8. Note that I
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don't plan to submit it in its current form but clean it up a bit first.
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Show the cache type of ARMv7 CPUs
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From: Catalin Marinas <catalin.marinas@arm.com>
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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---
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arch/arm/kernel/setup.c | 137 +++++++++++++++++++++++++++++++++++++++++++++-
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include/asm-arm/system.h | 18 ++++++
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2 files changed, 153 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
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index 5ae0eb2..0cd238d 100644
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--- a/arch/arm/kernel/setup.c
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+++ b/arch/arm/kernel/setup.c
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@@ -256,6 +256,24 @@ static const char *proc_arch[] = {
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"?(17)",
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};
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+static const char *v7_cache_policy[4] = {
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+ "reserved",
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+ "AVIVT",
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+ "VIPT",
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+ "PIPT",
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+};
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+
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+static const char *v7_cache_type[8] = {
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+ "none",
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+ "instruction only",
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+ "data only",
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+ "separate instruction and data",
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+ "unified",
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+ "unknown type",
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+ "unknown type",
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+ "unknown type",
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+};
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+
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#define CACHE_TYPE(x) (((x) >> 25) & 15)
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#define CACHE_S(x) ((x) & (1 << 24))
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#define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */
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@@ -266,6 +284,22 @@ static const char *proc_arch[] = {
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#define CACHE_M(y) ((y) & (1 << 2))
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#define CACHE_LINE(y) ((y) & 3)
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+#define CACHE_TYPE_V7(x) (((x) >> 14) & 3)
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+#define CACHE_UNIFIED(x) ((((x) >> 27) & 7)+1)
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+#define CACHE_COHERENT(x) ((((x) >> 24) & 7)+1)
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+
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+#define CACHE_ID_LEVEL_MASK 7
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+#define CACHE_ID_LEVEL_BITS 3
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+
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+#define CACHE_LINE_V7(v) ((1 << (((v) & 7)+4)))
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+#define CACHE_ASSOC_V7(v) ((((v) >> 3) & ((1<<10)-1))+1)
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+#define CACHE_SETS_V7(v) ((((v) >> 13) & ((1<<15)-1))+1)
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+#define CACHE_SIZE_V7(v) (CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v))
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+#define CACHE_WA_V7(v) (((v) & (1<<28)) != 0)
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+#define CACHE_RA_V7(v) (((v) & (1<<29)) != 0)
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+#define CACHE_WB_V7(v) (((v) & (1<<30)) != 0)
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+#define CACHE_WT_V7(v) (((v) & (1<<31)) != 0)
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+
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static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
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{
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unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
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@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
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CACHE_LINE(cache)));
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}
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+static void dump_v7_cache(const char *type, int cpu, unsigned int level)
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+{
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+ unsigned int cachesize;
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+
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+ write_extended_cpuid(2,0,0,0,level); /* Set the cache size selection register */
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+ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */
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+ cachesize = read_extended_cpuid(1,0,0,0);
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+
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+ printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n supports%s%s%s%s\n",
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+ cpu, type,
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+ CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize),
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+ CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize),
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+ CACHE_WA_V7(cachesize) ? " WA" : "",
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+ CACHE_RA_V7(cachesize) ? " RA" : "",
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+ CACHE_WB_V7(cachesize) ? " WB" : "",
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+ CACHE_WT_V7(cachesize) ? " WT" : "");
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+}
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+
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static void __init dump_cpu_info(int cpu)
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{
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unsigned int info = read_cpuid(CPUID_CACHETYPE);
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- if (info != processor_id) {
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+ if (info != processor_id && (info & (1 << 31))) {
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+ /* ARMv7 style of cache info register */
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+ unsigned int id = read_extended_cpuid(1,0,0,1);
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+ unsigned int level = 0;
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+ printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n",
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+ cpu,
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+ v7_cache_policy[CACHE_TYPE_V7(info)],
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+ CACHE_UNIFIED(id),
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+ CACHE_COHERENT(id));
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+
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+ while (id & CACHE_ID_LEVEL_MASK) {
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+ printk("CPU%u: Level %u cache is %s\n",
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+ cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
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+
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+ if (id & 1) {
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+ /* Dump I at this level */
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+ dump_v7_cache("I", cpu, level | 1);
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+ }
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+
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+ if (id & (4 | 2)) {
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+ /* Dump D or unified at this level */
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+ dump_v7_cache((id & 4) ? "unified" : "D", cpu, level);
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+ }
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+
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+ /* Next level out */
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+ level += 2;
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+ id >>= CACHE_ID_LEVEL_BITS;
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+ }
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+ } else if (info != processor_id) {
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printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
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cache_types[CACHE_TYPE(info)]);
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if (CACHE_S(info)) {
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@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
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CACHE_LINE(cache)));
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}
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+static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect)
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+{
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+ unsigned int cachesize;
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+ unsigned int level = (levelselect >> 1) + 1;
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+
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+ write_extended_cpuid(2,0,0,0,levelselect); /* Set the cache size selection register */
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+ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */
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+ cachesize = read_extended_cpuid(1,0,0,0);
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+
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+ seq_printf(m, "L%u %s size\t\t: %d bytes\n"
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+ "L%u %s assoc\t\t: %d\n"
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+ "L%u %s line length\t: %d\n"
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+ "L%u %s sets\t\t: %d\n"
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+ "L%u %s supports\t\t:%s%s%s%s\n",
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+ level, type, CACHE_SIZE_V7(cachesize),
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+ level, type, CACHE_ASSOC_V7(cachesize),
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+ level, type, CACHE_LINE_V7(cachesize),
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+ level, type, CACHE_SETS_V7(cachesize),
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+ level, type, CACHE_WA_V7(cachesize) ? " WA" : "",
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+ CACHE_RA_V7(cachesize) ? " RA" : "",
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+ CACHE_WB_V7(cachesize) ? " WB" : "",
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+ CACHE_WT_V7(cachesize) ? " WT" : "");
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+}
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+
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static int c_show(struct seq_file *m, void *v)
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{
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int i;
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@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v)
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{
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unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
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- if (cache_info != processor_id) {
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+ if (cache_info != processor_id && (cache_info & (1<<31))) {
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+ /* V7 style of cache info register */
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+ unsigned int id = read_extended_cpuid(1,0,0,1);
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+ unsigned int levelselect = 0;
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+ seq_printf(m, "L1 I cache\t:%s\n"
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+ "Cache unification level\t: %u\n"
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+ "Cache coherency level\t: %u\n",
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+ v7_cache_policy[CACHE_TYPE_V7(cache_info)],
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+ CACHE_UNIFIED(id),
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+ CACHE_COHERENT(id));
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+
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+ while (id & CACHE_ID_LEVEL_MASK) {
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+ seq_printf(m, "Level %u cache\t\t: %s\n",
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+ (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
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+
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+ if (id & 1) {
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+ /* Dump I at this level */
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+ c_show_v7_cache(m, "I", levelselect | 1);
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+ }
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+
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+ if (id & (4 | 2)) {
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+ /* Dump D or unified at this level */
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+ c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect);
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+ }
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+
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+ /* Next level out */
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+ levelselect += 2;
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+ id >>= CACHE_ID_LEVEL_BITS;
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+ }
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+ } else if (cache_info != processor_id) {
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seq_printf(m, "Cache type\t: %s\n"
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"Cache clean\t: %s\n"
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"Cache lockdown\t: %s\n"
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diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
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index 514af79..704738e 100644
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--- a/include/asm-arm/system.h
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+++ b/include/asm-arm/system.h
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@@ -74,6 +74,24 @@
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: "cc"); \
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__val; \
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})
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+#define read_extended_cpuid(op1,op2,op3,op4) \
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+ ({ \
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+ unsigned int __val; \
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+ asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \
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+ : "=r" (__val) \
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+ : \
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+ : "cc"); \
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+ __val; \
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+ })
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+
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+#define write_extended_cpuid(op1,op2,op3,op4,v) \
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+ ({ \
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+ unsigned int __val = v; \
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+ asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \
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+ : \
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+ : "r" (__val) \
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+ : "cc"); \
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+ })
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#else
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extern unsigned int processor_id;
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#define read_cpuid(reg) (processor_id)
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--
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Catalin
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