559 lines
18 KiB
Diff
559 lines
18 KiB
Diff
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
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index 13d0043..d582b8f 100644
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--- a/arch/arm/mach-omap2/Makefile
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+++ b/arch/arm/mach-omap2/Makefile
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@@ -44,7 +44,8 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \
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board-omap3evm-flash.o
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obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \
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usb-musb.o usb-ehci.o \
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- hsmmc.o
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+ hsmmc.o \
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+ board-omap3beagle-flash.o
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obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \
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hsmmc.o \
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usb-musb.o
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diff --git a/arch/arm/mach-omap2/board-omap3beagle-flash.c b/arch/arm/mach-omap2/board-omap3beagle-flash.c
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new file mode 100644
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index 0000000..5346df0
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--- /dev/null
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+++ b/arch/arm/mach-omap2/board-omap3beagle-flash.c
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@@ -0,0 +1,119 @@
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+/*
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+ * board-omap3beagle-flash.c
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+ *
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+ * Copyright (c) 2008 Texas Instruments
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+ *
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+ * Modified from board-omap3evm-flash.c
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/platform_device.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/types.h>
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+#include <linux/io.h>
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+
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+#include <asm/mach/flash.h>
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+#include <asm/arch/board.h>
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+#include <asm/arch/gpmc.h>
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+#include <asm/arch/nand.h>
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+
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+#define GPMC_CS0_BASE 0x60
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+#define GPMC_CS_SIZE 0x30
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+
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+static struct mtd_partition omap3beagle_nand_partitions[] = {
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+ /* All the partition sizes are listed in terms of NAND block size */
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+ {
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+ .name = "X-Loader",
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+ .offset = 0,
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+ .size = 4*(64 * 2048),
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ },
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+ {
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+ .name = "U-Boot",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
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+ .size = 15*(64 * 2048),
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ },
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+ {
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+ .name = "U-Boot Env",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
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+ .size = 1*(64 * 2048),
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+ },
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+ {
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+ .name = "Kernel",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
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+ .size = 32*(64 * 2048),
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+ },
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+ {
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+ .name = "File System",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
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+ .size = MTDPART_SIZ_FULL,
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+ },
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+};
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+
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+static struct omap_nand_platform_data omap3beagle_nand_data = {
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+ .parts = omap3beagle_nand_partitions,
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+ .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
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+ .dma_channel = -1, /* disable DMA in OMAP NAND driver */
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+ .nand_setup = NULL,
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+ .dev_ready = NULL,
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+};
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+
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+static struct resource omap3beagle_nand_resource = {
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct platform_device omap3beagle_nand_device = {
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+ .name = "omap2-nand",
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+ .id = -1,
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+ .dev = {
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+ .platform_data = &omap3beagle_nand_data,
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+ },
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+ .num_resources = 1,
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+ .resource = &omap3beagle_nand_resource,
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+};
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+
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+
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+void __init omap3beagle_flash_init(void)
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+{
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+ u8 cs = 0;
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+ u8 nandcs = GPMC_CS_NUM + 1;
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+
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+ u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
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+
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+ /* find out the chip-select on which NAND exists */
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+ while (cs < GPMC_CS_NUM) {
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+ u32 ret = 0;
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+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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+
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+ if ((ret & 0xC00) == 0x800) {
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+ printk(KERN_INFO "Found NAND on CS%d\n", cs);
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+ if (nandcs > GPMC_CS_NUM)
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+ nandcs = cs;
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+ }
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+ cs++;
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+ }
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+
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+ if (nandcs > GPMC_CS_NUM) {
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+ printk(KERN_INFO "NAND: Unable to find configuration "
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+ "in GPMC\n ");
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+ return;
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+ }
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+
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+ if (nandcs < GPMC_CS_NUM) {
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+ omap3beagle_nand_data.cs = nandcs;
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+ omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add +
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+ GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
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+ omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
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+
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+ printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
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+ if (platform_device_register(&omap3beagle_nand_device) < 0)
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+ printk(KERN_ERR "Unable to register NAND device\n");
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+ }
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+}
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diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
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index c992cc7..99e042e 100644
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--- a/arch/arm/mach-omap2/board-omap3beagle.c
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+++ b/arch/arm/mach-omap2/board-omap3beagle.c
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@@ -94,6 +94,7 @@ static void __init omap3_beagle_init(void)
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hsmmc_init();
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usb_musb_init();
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usb_ehci_init();
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+ omap3beagle_flash_init();
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}
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arch_initcall(omap3_beagle_i2c_init);
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diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
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index 3d5e432..02b9ced 100644
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -71,7 +71,7 @@ config MTD_NAND_AMS_DELTA
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config MTD_NAND_OMAP2
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tristate "NAND Flash device on OMAP 2420H4/2430SDP boards"
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- depends on (ARM && ARCH_OMAP2 && MTD_NAND)
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+ depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3)
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help
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Support for NAND flash on Texas Instruments 2430SDP/2420H4 platforms.
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diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
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index 3b7307c..3aac1d2 100644
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--- a/drivers/mtd/nand/omap2.c
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+++ b/drivers/mtd/nand/omap2.c
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@@ -111,15 +111,6 @@
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static const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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-static int hw_ecc = 1;
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-
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-/* new oob placement block for use with hardware ecc generation */
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-static struct nand_ecclayout omap_hw_eccoob = {
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- .eccbytes = 12,
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- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
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- .oobfree = {{16, 32}, {33, 63} },
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-};
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-
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struct omap_nand_info {
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struct nand_hw_control controller;
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struct omap_nand_platform_data *pdata;
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@@ -133,6 +124,13 @@ struct omap_nand_info {
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void __iomem *gpmc_cs_baseaddr;
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void __iomem *gpmc_baseaddr;
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};
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+
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+/*
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+ * omap_nand_wp - This function enable or disable the Write Protect feature on
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+ * NAND device
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+ * @mtd: MTD device structure
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+ * @mode: WP ON/OFF
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+ */
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static void omap_nand_wp(struct mtd_info *mtd, int mode)
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{
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struct omap_nand_info *info = container_of(mtd,
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@@ -189,11 +187,11 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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}
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/*
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-* omap_read_buf - read data from NAND controller into buffer
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-* @mtd: MTD device structure
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-* @buf: buffer to store date
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-* @len: number of bytes to read
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-*/
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+ * omap_read_buf - read data from NAND controller into buffer
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+ * @mtd: MTD device structure
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+ * @buf: buffer to store date
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+ * @len: number of bytes to read
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+ */
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static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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@@ -207,11 +205,11 @@ static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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}
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/*
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-* omap_write_buf - write buffer to NAND controller
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-* @mtd: MTD device structure
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-* @buf: data buffer
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-* @len: number of bytes to write
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-*/
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+ * omap_write_buf - write buffer to NAND controller
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+ * @mtd: MTD device structure
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+ * @buf: data buffer
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+ * @len: number of bytes to write
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+ */
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static void omap_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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@@ -250,10 +248,16 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
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return 0;
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}
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+#ifdef CONFIG_MTD_NAND_OMAP_HWECC
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+/*
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+ * omap_hwecc_init-Initialize the Hardware ECC for NAND flash in GPMC controller
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+ * @mtd: MTD device structure
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+ */
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static void omap_hwecc_init(struct mtd_info *mtd)
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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+ register struct nand_chip *chip = mtd->priv;
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unsigned long val = 0x0;
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/* Read from ECC Control Register */
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@@ -264,16 +268,15 @@ static void omap_hwecc_init(struct mtd_info *mtd)
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/* Read from ECC Size Config Register */
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val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
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- /* ECCSIZE1=512 | ECCSIZE0=8bytes | Select eccResultsize[0123] */
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- val = ((0x000000FF<<22) | (0x00000003<<12) | (0x0000000F));
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+ /* ECCSIZE1=512 | Select eccResultsize[0-3] */
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+ val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
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__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
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-
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-
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}
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/*
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- * This function will generate true ECC value, which can be used
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+ * gen_true_ecc - This function will generate true ECC value, which can be used
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* when correcting data read from NAND flash memory core
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+ * @ecc_buf: buffer to store ecc code
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*/
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static void gen_true_ecc(u8 *ecc_buf)
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{
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@@ -289,8 +292,12 @@ static void gen_true_ecc(u8 *ecc_buf)
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}
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/*
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- * This function compares two ECC's and indicates if there is an error.
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- * If the error can be corrected it will be corrected to the buffer
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+ * omap_compare_ecc - This function compares two ECC's and indicates if there
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+ * is an error. If the error can be corrected it will be corrected to the
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+ * buffer
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+ * @ecc_data1: ecc code from nand spare area
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+ * @ecc_data2: ecc code from hardware register obtained from hardware ecc
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+ * @page_data: page data
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*/
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static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
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u8 *ecc_data2, /* read from register */
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@@ -409,6 +416,14 @@ static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
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}
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}
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+/*
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+ * omap_correct_data - Compares the ecc read from nand spare area with ECC
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+ * registers values and corrects one bit error if it has occured
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+ * @mtd: MTD device structure
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+ * @dat: page data
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+ * @read_ecc: ecc read from nand flash
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+ * @calc_ecc: ecc read from ECC registers
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+ */
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static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
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u_char * read_ecc, u_char * calc_ecc)
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{
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@@ -436,65 +451,64 @@ static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
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}
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/*
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-** Generate non-inverted ECC bytes.
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-**
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-** Using noninverted ECC can be considered ugly since writing a blank
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-** page ie. padding will clear the ECC bytes. This is no problem as long
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-** nobody is trying to write data on the seemingly unused page.
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-**
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-** Reading an erased page will produce an ECC mismatch between
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-** generated and read ECC bytes that has to be dealt with separately.
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-*/
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+ * omap_calcuate_ecc - Generate non-inverted ECC bytes.
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+ * Using noninverted ECC can be considered ugly since writing a blank
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+ * page ie. padding will clear the ECC bytes. This is no problem as long
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+ * nobody is trying to write data on the seemingly unused page. Reading
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+ * an erased page will produce an ECC mismatch between generated and read
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+ * ECC bytes that has to be dealt with separately.
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+ * @mtd: MTD device structure
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+ * @dat: The pointer to data on which ecc is computed
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+ * @ecc_code: The ecc_code buffer
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+ */
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static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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unsigned long val = 0x0;
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- unsigned long reg, n;
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-
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- /* Ex NAND_ECC_HW12_2048 */
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- if ((info->nand.ecc.mode == NAND_ECC_HW) &&
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- (info->nand.ecc.size == 2048))
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- n = 4;
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- else
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- n = 1;
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+ unsigned long reg;
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/* Start Reading from HW ECC1_Result = 0x200 */
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reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
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- while (n--) {
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- val = __raw_readl(reg);
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- *ecc_code++ = val; /* P128e, ..., P1e */
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- *ecc_code++ = val >> 16; /* P128o, ..., P1o */
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- /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
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- *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
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- reg += 4;
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- }
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+ val = __raw_readl(reg);
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+ *ecc_code++ = val; /* P128e, ..., P1e */
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+ *ecc_code++ = val >> 16; /* P128o, ..., P1o */
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+ /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
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+ *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
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+ reg += 4;
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return 0;
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-} /* omap_calculate_ecc */
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+}
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+/*
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+ * omap_enable_hwecc - This function enables the hardware ecc functionality
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+ * @mtd: MTD device structure
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+ * @mode: Read/Write mode
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+ */
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static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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+ register struct nand_chip *chip = mtd->priv;
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+ unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
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unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
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switch (mode) {
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case NAND_ECC_READ :
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__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
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- val = (1 << 7) | (0x0) | (0x1) ;
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+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
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+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
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break;
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case NAND_ECC_READSYN :
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- __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
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- val = (1 << 7) | (0x0) | (0x1) ;
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+ __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
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+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
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break;
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case NAND_ECC_WRITE :
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__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
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- val = (1 << 7) | (0x0) | (0x1) ;
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+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
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+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
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break;
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default:
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DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
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@@ -504,7 +518,38 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
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__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
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}
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+#endif
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+/*
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+ * omap_wait - Wait function is called during Program and erase
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+ * operations and the way it is called from MTD layer, we should wait
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+ * till the NAND chip is ready after the programming/erase operation
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+ * has completed.
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+ * @mtd: MTD device structure
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+ * @chip: NAND Chip structure
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+ */
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+static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|
+{
|
|
+ register struct nand_chip *this = mtd->priv;
|
|
+ struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
|
+ mtd);
|
|
+ int status = 0;
|
|
+
|
|
+ this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
|
|
+ GPMC_CS_NAND_COMMAND;
|
|
+ this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
|
|
+
|
|
+ while (!(status & 0x40)) {
|
|
+ __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
|
|
+ status = __raw_readb(this->IO_ADDR_R);
|
|
+ }
|
|
+ return status;
|
|
+}
|
|
+
|
|
+/*
|
|
+ * omap_dev_ready - calls the platform specific dev_ready function
|
|
+ * @mtd: MTD device structure
|
|
+ */
|
|
static int omap_dev_ready(struct mtd_info *mtd)
|
|
{
|
|
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
|
@@ -534,7 +579,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
|
|
struct omap_nand_info *info;
|
|
struct omap_nand_platform_data *pdata;
|
|
int err;
|
|
- unsigned long val;
|
|
+ unsigned long val;
|
|
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
@@ -568,15 +613,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
|
|
}
|
|
|
|
/* Enable RD PIN Monitoring Reg */
|
|
- val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
|
|
- val |= WR_RD_PIN_MONITORING;
|
|
- gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
|
|
+ if (pdata->dev_ready) {
|
|
+ val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
|
|
+ val |= WR_RD_PIN_MONITORING;
|
|
+ gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
|
|
+ }
|
|
|
|
val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
|
|
val &= ~(0xf << 8);
|
|
val |= (0xc & 0xf) << 8;
|
|
gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
|
|
|
|
+ /* NAND write protect off */
|
|
+ omap_nand_wp(&info->mtd, NAND_WP_OFF);
|
|
+
|
|
if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
|
|
pdev->dev.driver->name)) {
|
|
err = -EBUSY;
|
|
@@ -597,29 +647,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
|
|
info->nand.write_buf = omap_write_buf;
|
|
info->nand.verify_buf = omap_verify_buf;
|
|
|
|
- info->nand.dev_ready = omap_dev_ready;
|
|
- info->nand.chip_delay = 0;
|
|
-
|
|
- /* Options */
|
|
- info->nand.options = NAND_BUSWIDTH_16;
|
|
- info->nand.options |= NAND_SKIP_BBTSCAN;
|
|
-
|
|
- if (hw_ecc) {
|
|
- /* init HW ECC */
|
|
- omap_hwecc_init(&info->mtd);
|
|
-
|
|
- info->nand.ecc.calculate = omap_calculate_ecc;
|
|
- info->nand.ecc.hwctl = omap_enable_hwecc;
|
|
- info->nand.ecc.correct = omap_correct_data;
|
|
- info->nand.ecc.mode = NAND_ECC_HW;
|
|
- info->nand.ecc.bytes = 12;
|
|
- info->nand.ecc.size = 2048;
|
|
- info->nand.ecc.layout = &omap_hw_eccoob;
|
|
-
|
|
+ /*
|
|
+ * If RDY/BSY line is connected to OMAP then use the omap ready funcrtion
|
|
+ * and the generic nand_wait function which reads the status register
|
|
+ * after monitoring the RDY/BSY line.Otherwise use a standard chip delay
|
|
+ * which is slightly more than tR (AC Timing) of the NAND device and read
|
|
+ * status register until you get a failure or success
|
|
+ */
|
|
+ if (pdata->dev_ready) {
|
|
+ info->nand.dev_ready = omap_dev_ready;
|
|
+ info->nand.chip_delay = 0;
|
|
} else {
|
|
- info->nand.ecc.mode = NAND_ECC_SOFT;
|
|
+ info->nand.waitfunc = omap_wait;
|
|
+ info->nand.chip_delay = 50;
|
|
}
|
|
|
|
+ info->nand.options |= NAND_SKIP_BBTSCAN;
|
|
+ if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
|
|
+ == 0x1000)
|
|
+ info->nand.options |= NAND_BUSWIDTH_16;
|
|
+
|
|
+#ifdef CONFIG_MTD_NAND_OMAP_HWECC
|
|
+ info->nand.ecc.bytes = 3;
|
|
+ info->nand.ecc.size = 512;
|
|
+ info->nand.ecc.calculate = omap_calculate_ecc;
|
|
+ info->nand.ecc.hwctl = omap_enable_hwecc;
|
|
+ info->nand.ecc.correct = omap_correct_data;
|
|
+ info->nand.ecc.mode = NAND_ECC_HW;
|
|
+
|
|
+ /* init HW ECC */
|
|
+ omap_hwecc_init(&info->mtd);
|
|
+#else
|
|
+ info->nand.ecc.mode = NAND_ECC_SOFT;
|
|
+#endif
|
|
|
|
/* DIP switches on some boards change between 8 and 16 bit
|
|
* bus widths for flash. Try the other width if the first try fails.
|
|
@@ -636,14 +696,12 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
|
|
err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
|
|
if (err > 0)
|
|
add_mtd_partitions(&info->mtd, info->parts, err);
|
|
- else if (err < 0 && pdata->parts)
|
|
+ else if (err <= 0 && pdata->parts)
|
|
add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
|
|
else
|
|
#endif
|
|
add_mtd_device(&info->mtd);
|
|
|
|
- omap_nand_wp(&info->mtd, NAND_WP_OFF);
|
|
-
|
|
platform_set_drvdata(pdev, &info->mtd);
|
|
|
|
return 0;
|
|
diff --git a/include/asm-arm/arch-omap/board-omap3beagle.h b/include/asm-arm/arch-omap/board-omap3beagle.h
|
|
index 46dff31..26ecfb8 100644
|
|
--- a/include/asm-arm/arch-omap/board-omap3beagle.h
|
|
+++ b/include/asm-arm/arch-omap/board-omap3beagle.h
|
|
@@ -29,5 +29,7 @@
|
|
#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
|
|
#define __ASM_ARCH_OMAP3_BEAGLE_H
|
|
|
|
+extern void omap3beagle_flash_init(void);
|
|
+
|
|
#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
|
|
|