95 lines
2.6 KiB
Diff
95 lines
2.6 KiB
Diff
From: Mans Rullgard <mans@mansr.com>
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Date: Wed, 23 Jul 2008 08:40:07 +0000 (+0100)
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Subject: ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock
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X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01ee28c50701caa94739e764c3dae9298edd8216
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ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock
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This sets the DSS1_ALWON_FCLK clock as close as possible to a
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multiple of the requested pixel clock, while keeping it below
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the 173MHz limit.
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Due to of the structure of the clock tree, dss1_alwon_fck cannot
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be set directly, and we must use dpll4_m4_ck instead.
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Signed-off-by: Mans Rullgard <mans@mansr.com>
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---
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diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
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index fd06ca2..e0e8528 100644
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--- a/drivers/video/omap/dispc.c
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+++ b/drivers/video/omap/dispc.c
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@@ -176,6 +176,7 @@ static struct {
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struct clk *dss_ick, *dss1_fck;
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struct clk *dss_54m_fck;
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+ struct clk *dpll4_m4_ck;
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enum omapfb_update_mode update_mode;
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struct omapfb_device *fbdev;
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@@ -738,21 +739,34 @@ static void setup_color_conv_coef(void)
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MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
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}
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-#define MAX_FCK_LCD 173000000
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+#define MAX_FCK 173000000
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static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
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{
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+ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
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+ unsigned long pcd_min = is_tft? 2: 3;
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+ unsigned long fck_div;
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unsigned long fck, lck;
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pck = max(1, pck);
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+
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+ if (pck * pcd_min > MAX_FCK) {
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+ dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n",
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+ pck / 1000);
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+ pck = MAX_FCK / pcd_min;
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+ }
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+
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+ fck = pck * 2;
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+ fck_div = (prate + pck) / fck;
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+ if (fck_div > 16)
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+ fck_div /= (fck_div + 15) / 16;
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+ if (fck_div < 1)
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+ fck_div = 1;
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+ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div);
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fck = clk_get_rate(dispc.dss1_fck);
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- *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD;
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- lck = fck / *lck_div;
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- *pck_div = (lck + pck - 1) / pck;
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- if (is_tft)
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- *pck_div = max(2, *pck_div);
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- else
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- *pck_div = max(3, *pck_div);
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+
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+ *lck_div = 1;
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+ *pck_div = (fck + pck - 1) / pck;
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if (*pck_div > 255) {
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*pck_div = 255;
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lck = pck * *pck_div;
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@@ -914,11 +928,21 @@ static int get_dss_clocks(void)
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return PTR_ERR(dispc.dss_54m_fck);
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}
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+ if (IS_ERR((dispc.dpll4_m4_ck =
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+ clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) {
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+ dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck");
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+ clk_put(dispc.dss_ick);
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+ clk_put(dispc.dss1_fck);
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+ clk_put(dispc.dss_54m_fck);
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+ return PTR_ERR(dispc.dss_54m_fck);
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+ }
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+
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return 0;
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}
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static void put_dss_clocks(void)
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{
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+ clk_put(dispc.dpll4_m4_ck);
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clk_put(dispc.dss_54m_fck);
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clk_put(dispc.dss1_fck);
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clk_put(dispc.dss_ick);
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