115 lines
4.7 KiB
Diff
115 lines
4.7 KiB
Diff
From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
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Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT)
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From: Paul Walmsley <paul@pwsan.com>
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To: linux-omap@vger.kernel.org
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Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
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Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com>
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X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9]
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OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
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DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
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into the OMAP3 clock framework.
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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---
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arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++----
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1 files changed, 16 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
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index b4dceea..9605744 100644
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--- a/arch/arm/mach-omap2/clock34xx.h
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+++ b/arch/arm/mach-omap2/clock34xx.h
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@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = {
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/* DPLL power domain clock controls */
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-static const struct clksel div2_core_clksel[] = {
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- { .parent = &core_ck, .rates = div2_rates },
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+static const struct clksel_rate div4_rates[] = {
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+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
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+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
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+ { .div = 0 }
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+};
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+
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+static const struct clksel div4_core_clksel[] = {
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+ { .parent = &core_ck, .rates = div4_rates },
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{ .parent = NULL }
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};
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@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = {
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.init = &omap2_init_clksel_parent,
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.clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
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.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
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- .clksel = div2_core_clksel,
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+ .clksel = div4_core_clksel,
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.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
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PARENT_CONTROLS_CLOCK,
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.recalc = &omap2_clksel_recalc,
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@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = {
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.init = &omap2_init_clksel_parent,
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.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
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.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
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- .clksel = div2_core_clksel,
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+ .clksel = div4_core_clksel,
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.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
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PARENT_CONTROLS_CLOCK,
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.recalc = &omap2_clksel_recalc,
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@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = {
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/* Common interface clocks */
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+static const struct clksel div2_core_clksel[] = {
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+ { .parent = &core_ck, .rates = div2_rates },
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+ { .parent = NULL }
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+};
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+
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static struct clk l3_ick = {
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.name = "l3_ick",
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.parent = &core_ck,
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--
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