197 lines
5.4 KiB
Diff
197 lines
5.4 KiB
Diff
With qemu 0.13.0, poky failed to start on ppc arch because both ppc_prep_init
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and i8042_initfn try to register to port 0x92 then cause conflict. Introduce
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this patch from upstream to fix it.
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Could remove it in future if necessary.
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Signed-off-by: Zhai, Edwin <edwin.zhai@intel.com>
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commit 4b78a802ffaabb325a0f7b773031da92d173bde1
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Author: Blue Swirl <blauwirbel@gmail.com>
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Date: Thu Jan 6 18:24:35 2011 +0000
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pc: move port 92 stuff back to pc.c from pckbd.c
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956a3e6bb7386de48b642d4fee11f7f86a2fcf9a introduced a bug concerning
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reset bit for port 92.
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Since the keyboard output port and port 92 are not compatible anyway,
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let's separate them.
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Reported-by: Peter Lieven <pl@dlh.net>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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--
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v2: added reset handler and VMState
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Index: qemu-0.13.0/hw/pc.c
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===================================================================
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--- qemu-0.13.0.orig/hw/pc.c 2010-10-16 04:56:09.000000000 +0800
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+++ qemu-0.13.0/hw/pc.c 2011-01-20 20:37:37.000000000 +0800
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@@ -409,11 +409,91 @@
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qemu_register_reset(pc_cmos_init_late, &arg);
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}
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+/* port 92 stuff: could be split off */
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+typedef struct Port92State {
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+ ISADevice dev;
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+ uint8_t outport;
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+ qemu_irq *a20_out;
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+} Port92State;
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+
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+static void port92_write(void *opaque, uint32_t addr, uint32_t val)
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+{
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+ Port92State *s = opaque;
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+
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+ DPRINTF("port92: write 0x%02x\n", val);
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+ s->outport = val;
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+ qemu_set_irq(*s->a20_out, (val >> 1) & 1);
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+ if (val & 1) {
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+ qemu_system_reset_request();
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+ }
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+}
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+
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+static uint32_t port92_read(void *opaque, uint32_t addr)
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+{
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+ Port92State *s = opaque;
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+ uint32_t ret;
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+
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+ ret = s->outport;
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+ DPRINTF("port92: read 0x%02x\n", ret);
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+ return ret;
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+}
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+
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+static void port92_init(ISADevice *dev, qemu_irq *a20_out)
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+{
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+ Port92State *s = DO_UPCAST(Port92State, dev, dev);
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+
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+ s->a20_out = a20_out;
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+}
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+
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+static const VMStateDescription vmstate_port92_isa = {
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+ .name = "port92",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .minimum_version_id_old = 1,
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+ .fields = (VMStateField []) {
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+ VMSTATE_UINT8(outport, Port92State),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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+static void port92_reset(DeviceState *d)
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+{
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+ Port92State *s = container_of(d, Port92State, dev.qdev);
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+
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+ s->outport &= ~1;
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+}
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+
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+static int port92_initfn(ISADevice *dev)
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+{
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+ Port92State *s = DO_UPCAST(Port92State, dev, dev);
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+
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+ register_ioport_read(0x92, 1, 1, port92_read, s);
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+ register_ioport_write(0x92, 1, 1, port92_write, s);
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+ s->outport = 0;
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+ return 0;
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+}
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+
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+static ISADeviceInfo port92_info = {
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+ .qdev.name = "port92",
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+ .qdev.size = sizeof(Port92State),
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+ .qdev.vmsd = &vmstate_port92_isa,
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+ .qdev.no_user = 1,
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+ .qdev.reset = port92_reset,
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+ .init = port92_initfn,
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+};
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+
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+static void port92_register(void)
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+{
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+ isa_qdev_register(&port92_info);
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+}
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+device_init(port92_register)
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+
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static void handle_a20_line_change(void *opaque, int irq, int level)
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{
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CPUState *cpu = opaque;
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/* XXX: send to all CPUs ? */
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+ /* XXX: add logic to handle multiple A20 line sources */
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cpu_x86_set_a20(cpu, level);
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}
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@@ -1017,7 +1097,7 @@
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PITState *pit;
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qemu_irq rtc_irq = NULL;
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qemu_irq *a20_line;
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- ISADevice *i8042;
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+ ISADevice *i8042, *port92;
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qemu_irq *cpu_exit_irq;
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register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
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@@ -1051,10 +1131,12 @@
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}
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}
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- a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
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+ a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
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i8042 = isa_create_simple("i8042");
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- i8042_setup_a20_line(i8042, a20_line);
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+ i8042_setup_a20_line(i8042, &a20_line[0]);
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vmmouse_init(i8042);
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+ port92 = isa_create_simple("port92");
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+ port92_init(port92, &a20_line[1]);
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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Index: qemu-0.13.0/hw/pckbd.c
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===================================================================
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--- qemu-0.13.0.orig/hw/pckbd.c 2010-10-16 04:56:09.000000000 +0800
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+++ qemu-0.13.0/hw/pckbd.c 2011-01-20 20:33:44.000000000 +0800
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@@ -209,10 +209,8 @@
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ps2_queue(s->kbd, b);
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}
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-static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
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+static void outport_write(KBDState *s, uint32_t val)
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{
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- KBDState *s = opaque;
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-
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DPRINTF("kbd: write outport=0x%02x\n", val);
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s->outport = val;
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if (s->a20_out) {
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@@ -223,16 +221,6 @@
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}
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}
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-static uint32_t ioport92_read(void *opaque, uint32_t addr)
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-{
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- KBDState *s = opaque;
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- uint32_t ret;
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-
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- ret = s->outport;
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- DPRINTF("kbd: read outport=0x%02x\n", ret);
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- return ret;
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-}
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-
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static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
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{
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KBDState *s = opaque;
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@@ -340,7 +328,7 @@
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kbd_queue(s, val, 1);
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break;
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case KBD_CCMD_WRITE_OUTPORT:
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- ioport92_write(s, 0, val);
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+ outport_write(s, val);
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break;
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case KBD_CCMD_WRITE_MOUSE:
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ps2_write_mouse(s->mouse, val);
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@@ -469,8 +457,6 @@
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register_ioport_write(0x60, 1, 1, kbd_write_data, s);
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register_ioport_read(0x64, 1, 1, kbd_read_status, s);
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register_ioport_write(0x64, 1, 1, kbd_write_command, s);
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- register_ioport_read(0x92, 1, 1, ioport92_read, s);
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- register_ioport_write(0x92, 1, 1, ioport92_write, s);
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s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
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s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
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