UBL is setting up the flash timings (A1CR) and so far U-Boot was overwriting it with a timing for the EVB development board of TI. Let UBL define ECC/ChipSelect and the A1CR timings. This might now cause different kind of flash issues because the per chip timings might be "wrong". This is why this commit should needs to stay in testing a bit longer. We should use this commit on RevC, D, E and F hardware ourselves a bit.laforge/owhw2
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