2003-10-15 23:53:47 +00:00
|
|
|
/*
|
2004-06-09 00:34:46 +00:00
|
|
|
* Copyright 2004 Freescale Semiconductor.
|
2003-10-15 23:53:47 +00:00
|
|
|
* (C) Copyright 2003,Motorola Inc.
|
|
|
|
* Xianghua Xiao, (X.Xiao@motorola.com)
|
|
|
|
*
|
|
|
|
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2003-10-15 23:53:47 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
|
|
#include <common.h>
|
2004-08-01 23:02:45 +00:00
|
|
|
#include <pci.h>
|
2003-10-15 23:53:47 +00:00
|
|
|
#include <asm/processor.h>
|
2008-03-18 16:12:44 +00:00
|
|
|
#include <asm/mmu.h>
|
2003-10-15 23:53:47 +00:00
|
|
|
#include <asm/immap_85xx.h>
|
2008-03-18 16:12:44 +00:00
|
|
|
#include <asm/fsl_ddr_sdram.h>
|
2003-10-15 23:53:47 +00:00
|
|
|
#include <ioports.h>
|
2008-03-04 16:03:03 +00:00
|
|
|
#include <spd_sdram.h>
|
2003-10-15 23:53:47 +00:00
|
|
|
#include <miiphy.h>
|
2007-11-29 04:40:31 +00:00
|
|
|
#include <libfdt.h>
|
|
|
|
#include <fdt_support.h>
|
2009-03-26 06:34:38 +00:00
|
|
|
#include <asm/fsl_lbc.h>
|
2006-10-20 20:54:34 +00:00
|
|
|
|
2005-07-25 19:05:07 +00:00
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
2004-07-09 23:27:13 +00:00
|
|
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2004-08-01 23:02:45 +00:00
|
|
|
void local_bus_init(void);
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* I/O Port configuration table
|
|
|
|
*
|
|
|
|
* if conf is 1, then that port pin will be configured at boot time
|
|
|
|
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
|
|
|
*/
|
|
|
|
|
|
|
|
const iop_conf_t iop_conf_tab[4][32] = {
|
|
|
|
|
|
|
|
/* Port A configuration */
|
|
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
|
|
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
|
|
|
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
|
|
|
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
|
|
|
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
|
|
|
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
|
|
|
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
|
|
|
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
|
|
|
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
|
|
|
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
|
|
|
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
|
|
|
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
|
|
|
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
|
|
|
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
|
|
|
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
|
|
|
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
|
|
|
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
|
|
|
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
|
|
|
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
|
|
|
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
|
|
|
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
|
|
|
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
|
|
|
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
|
|
|
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
|
|
|
|
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
|
|
|
|
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
|
|
|
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
|
|
|
|
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
|
|
|
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
|
|
|
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
|
|
|
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
|
|
|
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
|
|
|
|
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
|
|
|
},
|
|
|
|
|
|
|
|
/* Port B configuration */
|
|
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
|
|
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
|
|
|
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
|
|
|
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
|
|
|
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
|
|
|
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
|
|
|
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
|
|
|
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
|
|
|
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
|
|
|
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
|
|
|
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
|
|
|
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
|
|
|
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
|
|
|
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
|
|
|
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
|
|
|
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
|
|
|
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
|
|
|
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
|
|
|
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
|
|
|
|
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
|
|
|
|
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
|
|
|
|
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
|
|
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
|
|
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
|
|
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
|
|
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
|
|
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
|
|
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
|
|
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
|
|
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
|
|
|
},
|
|
|
|
|
|
|
|
/* Port C */
|
|
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
|
|
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
|
|
|
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
|
|
|
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
|
|
|
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
|
|
|
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
|
|
|
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
|
|
|
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
|
|
|
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
|
|
|
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
|
|
|
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
|
|
|
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
|
|
|
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
|
|
|
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
|
|
|
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
|
|
|
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
|
|
|
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
|
|
|
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
|
|
|
|
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
|
|
|
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
|
|
|
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
|
|
|
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
|
|
|
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
|
|
|
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
|
|
|
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
|
|
|
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
|
|
|
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
|
|
|
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
|
|
|
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
|
|
|
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
|
|
|
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
|
|
|
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
|
|
|
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
|
|
|
},
|
|
|
|
|
|
|
|
/* Port D */
|
|
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
|
|
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
|
|
|
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
|
|
|
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
|
|
|
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
|
|
|
|
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
|
|
|
|
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
|
|
|
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
|
|
|
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
|
|
|
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
|
|
|
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
|
|
|
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
|
|
|
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
|
|
|
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
|
|
|
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
|
|
|
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
|
|
|
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
|
|
|
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
|
|
|
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
|
|
|
|
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
|
|
|
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
|
|
|
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
|
|
|
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
|
|
|
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
|
|
|
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
|
|
|
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
|
|
|
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
|
|
|
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
|
|
|
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
|
|
|
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
|
|
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2004-07-09 23:27:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* MPC8560ADS Board Status & Control Registers
|
|
|
|
*/
|
|
|
|
typedef struct bcsr_ {
|
2003-10-15 23:53:47 +00:00
|
|
|
volatile unsigned char bcsr0;
|
|
|
|
volatile unsigned char bcsr1;
|
|
|
|
volatile unsigned char bcsr2;
|
|
|
|
volatile unsigned char bcsr3;
|
|
|
|
volatile unsigned char bcsr4;
|
|
|
|
volatile unsigned char bcsr5;
|
|
|
|
} bcsr_t;
|
|
|
|
|
|
|
|
void reset_phy (void)
|
|
|
|
{
|
|
|
|
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
|
2003-10-15 23:53:47 +00:00
|
|
|
#endif
|
|
|
|
/* reset Giga bit Ethernet port if needed here */
|
|
|
|
|
|
|
|
/* reset the CPM FEC port */
|
|
|
|
#if (CONFIG_ETHER_INDEX == 2)
|
|
|
|
bcsr->bcsr2 &= ~FETH2_RST;
|
|
|
|
udelay(2);
|
|
|
|
bcsr->bcsr2 |= FETH2_RST;
|
|
|
|
udelay(1000);
|
|
|
|
#elif (CONFIG_ETHER_INDEX == 3)
|
|
|
|
bcsr->bcsr3 &= ~FETH3_RST;
|
|
|
|
udelay(2);
|
|
|
|
bcsr->bcsr3 |= FETH3_RST;
|
|
|
|
udelay(1000);
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
|
2005-10-28 20:30:33 +00:00
|
|
|
/* reset PHY */
|
2010-07-20 15:45:02 +00:00
|
|
|
miiphy_reset("FCC1", 0x0);
|
2005-10-28 20:30:33 +00:00
|
|
|
|
|
|
|
/* change PHY address to 0x02 */
|
2010-12-23 20:40:12 +00:00
|
|
|
bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
|
2005-10-28 20:30:33 +00:00
|
|
|
|
2010-12-23 20:40:12 +00:00
|
|
|
bb_miiphy_write(NULL, 0x02, MII_BMCR,
|
|
|
|
BMCR_ANENABLE | BMCR_ANRESTART);
|
2003-10-15 23:53:47 +00:00
|
|
|
#endif /* CONFIG_MII */
|
|
|
|
}
|
|
|
|
|
2004-08-01 23:02:45 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
int checkboard (void)
|
|
|
|
{
|
2004-06-09 00:34:46 +00:00
|
|
|
puts("Board: ADS\n");
|
2004-07-09 23:27:13 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
2010-10-29 22:59:24 +00:00
|
|
|
printf("PCI1: 32 bit, %d MHz (compiled)\n",
|
2004-07-09 23:27:13 +00:00
|
|
|
CONFIG_SYS_CLK_FREQ / 1000000);
|
|
|
|
#else
|
2010-10-29 22:59:24 +00:00
|
|
|
printf("PCI1: disabled\n");
|
2004-07-09 23:27:13 +00:00
|
|
|
#endif
|
2004-08-01 23:02:45 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize local bus.
|
|
|
|
*/
|
|
|
|
local_bus_init();
|
|
|
|
|
2004-06-09 00:34:46 +00:00
|
|
|
return 0;
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
|
|
|
|
2004-07-09 23:27:13 +00:00
|
|
|
/*
|
2004-08-01 23:02:45 +00:00
|
|
|
* Initialize Local Bus
|
2004-07-09 23:27:13 +00:00
|
|
|
*/
|
|
|
|
|
2004-08-01 23:02:45 +00:00
|
|
|
void
|
|
|
|
local_bus_init(void)
|
2004-07-09 23:27:13 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
2010-06-17 16:37:20 +00:00
|
|
|
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2004-08-01 23:02:45 +00:00
|
|
|
uint clkdiv;
|
|
|
|
uint lbc_hz;
|
|
|
|
sys_info_t sysinfo;
|
2004-07-09 23:27:13 +00:00
|
|
|
|
|
|
|
/*
|
2004-08-01 23:02:45 +00:00
|
|
|
* Errata LBC11.
|
|
|
|
* Fix Local Bus clock glitch when DLL is enabled.
|
2004-07-09 23:27:13 +00:00
|
|
|
*
|
2008-10-19 00:35:50 +00:00
|
|
|
* If localbus freq is < 66MHz, DLL bypass mode must be used.
|
|
|
|
* If localbus freq is > 133MHz, DLL can be safely enabled.
|
2004-08-01 23:02:45 +00:00
|
|
|
* Between 66 and 133, the DLL is enabled with an override workaround.
|
2004-07-09 23:27:13 +00:00
|
|
|
*/
|
2004-08-01 23:02:45 +00:00
|
|
|
|
|
|
|
get_sys_info(&sysinfo);
|
2008-12-03 23:16:34 +00:00
|
|
|
clkdiv = lbc->lcrr & LCRR_CLKDIV;
|
2004-08-01 23:02:45 +00:00
|
|
|
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
|
|
|
|
|
|
|
|
if (lbc_hz < 66) {
|
2012-08-13 13:48:57 +00:00
|
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
|
2004-08-01 23:02:45 +00:00
|
|
|
|
|
|
|
} else if (lbc_hz >= 133) {
|
2012-08-13 13:48:57 +00:00
|
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
} else {
|
2004-07-09 23:27:13 +00:00
|
|
|
/*
|
|
|
|
* On REV1 boards, need to change CLKDIV before enable DLL.
|
|
|
|
* Default CLKDIV is 8, change it to 4 temporarily.
|
|
|
|
*/
|
2004-08-01 23:02:45 +00:00
|
|
|
uint pvr = get_pvr();
|
2004-07-09 23:27:13 +00:00
|
|
|
uint temp_lbcdll = 0;
|
2004-06-09 00:34:46 +00:00
|
|
|
|
|
|
|
if (pvr == PVR_85xx_REV1) {
|
2004-08-01 23:02:45 +00:00
|
|
|
/* FIXME: Justify the high bit here. */
|
2004-07-09 23:27:13 +00:00
|
|
|
lbc->lcrr = 0x10000004;
|
2004-06-09 00:34:46 +00:00
|
|
|
}
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2012-08-13 13:48:57 +00:00
|
|
|
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
|
2004-08-01 23:02:45 +00:00
|
|
|
udelay(200);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Sample LBC DLL ctrl reg, upshift it to set the
|
|
|
|
* override bits.
|
|
|
|
*/
|
2003-10-15 23:53:47 +00:00
|
|
|
temp_lbcdll = gur->lbcdllcr;
|
2004-08-01 23:02:45 +00:00
|
|
|
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
|
|
|
asm("sync;isync;msync");
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
2004-08-01 23:02:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize SDRAM memory on the Local Bus.
|
|
|
|
*/
|
2010-12-17 23:17:57 +00:00
|
|
|
void lbc_sdram_init(void)
|
2004-08-01 23:02:45 +00:00
|
|
|
{
|
2010-06-17 16:37:20 +00:00
|
|
|
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
2008-10-16 13:01:15 +00:00
|
|
|
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
|
2004-08-01 23:02:45 +00:00
|
|
|
|
2010-12-17 23:17:59 +00:00
|
|
|
puts("LBC SDRAM: ");
|
|
|
|
print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
|
|
|
|
"\n ");
|
2004-07-09 23:27:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup SDRAM Base and Option Registers
|
|
|
|
*/
|
2010-06-17 16:37:20 +00:00
|
|
|
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
|
|
|
|
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("msync");
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
|
|
|
|
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the SDRAM controller.
|
|
|
|
*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
*sdram_addr = 0xff;
|
2004-08-01 23:02:45 +00:00
|
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
|
|
udelay(100);
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
*sdram_addr = 0xff;
|
2004-08-01 23:02:45 +00:00
|
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
|
|
udelay(100);
|
2004-07-09 23:27:13 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
*sdram_addr = 0xff;
|
2004-08-01 23:02:45 +00:00
|
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
|
|
udelay(100);
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
*sdram_addr = 0xff;
|
2004-08-01 23:02:45 +00:00
|
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
|
|
udelay(100);
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
|
2004-08-01 23:02:45 +00:00
|
|
|
asm("sync");
|
2004-07-09 23:27:13 +00:00
|
|
|
*sdram_addr = 0xff;
|
2004-08-01 23:02:45 +00:00
|
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
|
|
udelay(100);
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_SPD_EEPROM)
|
|
|
|
/*************************************************************************
|
|
|
|
* fixed sdram init -- doesn't use serial presence detect.
|
|
|
|
************************************************************************/
|
2010-12-17 23:17:56 +00:00
|
|
|
phys_size_t fixed_sdram(void)
|
2003-10-15 23:53:47 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
2012-10-24 00:03:46 +00:00
|
|
|
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
|
2008-10-16 13:01:15 +00:00
|
|
|
|
|
|
|
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
|
|
|
|
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
|
|
|
|
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
|
|
|
|
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
|
|
|
|
ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
|
|
|
|
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
|
2003-10-15 23:53:47 +00:00
|
|
|
#if defined (CONFIG_DDR_ECC)
|
|
|
|
ddr->err_disable = 0x0000000D;
|
|
|
|
ddr->err_sbe = 0x00ff0000;
|
|
|
|
#endif
|
|
|
|
asm("sync;isync;msync");
|
|
|
|
udelay(500);
|
|
|
|
#if defined (CONFIG_DDR_ECC)
|
|
|
|
/* Enable ECC checking */
|
2008-10-16 13:01:15 +00:00
|
|
|
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
|
2003-10-15 23:53:47 +00:00
|
|
|
#else
|
2008-10-16 13:01:15 +00:00
|
|
|
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
|
2003-10-15 23:53:47 +00:00
|
|
|
#endif
|
|
|
|
asm("sync; isync; msync");
|
|
|
|
udelay(500);
|
|
|
|
#endif
|
2008-10-16 13:01:15 +00:00
|
|
|
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
2003-10-15 23:53:47 +00:00
|
|
|
}
|
|
|
|
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
2004-08-01 23:02:45 +00:00
|
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_PCI)
|
|
|
|
/*
|
|
|
|
* Initialize PCI Devices, report devices found.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef CONFIG_PCI_PNP
|
|
|
|
static struct pci_config_table pci_mpc85xxads_config_table[] = {
|
|
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
|
|
|
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
|
|
|
PCI_ENET0_MEMADDR,
|
|
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
|
|
|
|
} },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
static struct pci_controller hose = {
|
|
|
|
#ifndef CONFIG_PCI_PNP
|
|
|
|
config_table: pci_mpc85xxads_config_table,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
pci_init_board(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
pci_mpc85xx_init(&hose);
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
}
|
2006-06-28 15:43:36 +00:00
|
|
|
|
|
|
|
|
2007-11-29 04:40:31 +00:00
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
2006-06-28 15:43:36 +00:00
|
|
|
void
|
|
|
|
ft_board_setup(void *blob, bd_t *bd)
|
|
|
|
{
|
2007-11-29 04:40:31 +00:00
|
|
|
int node, tmp[2];
|
|
|
|
const char *path;
|
|
|
|
|
2006-06-28 15:43:36 +00:00
|
|
|
ft_cpu_setup(blob, bd);
|
2007-11-29 04:40:31 +00:00
|
|
|
|
|
|
|
node = fdt_path_offset(blob, "/aliases");
|
|
|
|
tmp[0] = 0;
|
|
|
|
if (node >= 0) {
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
|
|
|
if (path) {
|
|
|
|
tmp[1] = hose.last_busno - hose.first_busno;
|
|
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
2006-06-28 15:43:36 +00:00
|
|
|
}
|
|
|
|
#endif
|