2014-02-04 08:56:13 +00:00
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARC_CACHE_H
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#define __ASM_ARC_CACHE_H
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#include <config.h>
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/*
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* The current upper bound for ARC L1 data cache line sizes is 128 bytes.
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* We use that value for aligning DMA buffers unless the board config has
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* specified an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 128
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#endif
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2015-02-03 10:58:11 +00:00
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#if defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#endif
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2014-02-04 08:56:13 +00:00
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#endif /* __ASM_ARC_CACHE_H */
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