2016-05-12 19:32:55 +00:00
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#include "skeleton.dtsi"
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2016-07-18 18:15:03 +00:00
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#include <dt-bindings/gpio/tegra186-gpio.h>
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2016-05-12 19:32:55 +00:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2016-07-27 21:24:49 +00:00
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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2016-05-12 19:32:55 +00:00
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/ {
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compatible = "nvidia,tegra186";
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#address-cells = <2>;
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#size-cells = <2>;
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gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg =
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<0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts =
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x10000>;
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reg-shift = <2>;
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status = "disabled";
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};
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sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x200>;
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interrupts = <GIC_SPI 31 0x04>;
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status = "disabled";
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};
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2016-06-17 15:43:57 +00:00
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hsp: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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2016-07-27 21:24:49 +00:00
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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2016-06-17 15:43:57 +00:00
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};
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2016-05-12 19:32:55 +00:00
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gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg =
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<0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts =
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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