49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
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/*
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* From coreboot southbridge/intel/bd82x6x/lpc.c
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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int lpc_early_init(const void *blob, int node, pci_dev_t dev)
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{
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struct reg_info {
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u32 base;
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u32 size;
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} values[4], *ptr;
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int count;
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int i;
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count = fdtdec_get_int_array_count(blob, node, "gen-dec",
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(u32 *)values, sizeof(values) / sizeof(u32));
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if (count < 0)
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return -EINVAL;
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/* Set COM1/COM2 decode range */
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pci_write_config16(dev, LPC_IO_DEC, 0x0010);
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/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
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pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
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GAMEL_LPC_EN | COMA_LPC_EN);
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/* Write all registers but use 0 if we run out of data */
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count = count * sizeof(u32) / sizeof(values[0]);
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for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
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u32 reg = 0;
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if (i < count)
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reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
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pci_write_config32(dev, LPC_GENX_DEC(i), reg);
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}
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return 0;
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}
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