95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
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/*
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* (C) Copyright 2006-2010
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res[0xc];
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u32 tiocp_cfg; /* 0x10 rw */
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u32 tistat; /* 0x14 r */
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u32 tisr; /* 0x18 rw */
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u32 tier; /* 0x1c rw */
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u32 twer; /* 0x20 rw */
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u32 tclr; /* 0x24 rw */
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u32 tcrr; /* 0x28 rw */
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u32 tldr; /* 0x2c rw */
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u32 ttgr; /* 0x30 rw */
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u32 twpc; /* 0x34 r */
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u32 tmar; /* 0x38 rw */
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u32 tcar1; /* 0x3c r */
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u32 tcicr; /* 0x40 rw */
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u32 tcar2; /* 0x44 r */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct watchdog {
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u8 res1[0x34];
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u32 wwps; /* 0x34 r */
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u8 res2[0x10];
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u32 wspr; /* 0x48 rw */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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#define SYSCLKDIV_1 (0x1 << 6)
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#define SYSCLKDIV_2 (0x1 << 7)
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#define CLKSEL_GPT1 (0x1 << 0)
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#define EN_GPT1 (0x1 << 0)
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#define EN_32KSYNC (0x1 << 2)
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#define ST_WDT2 (0x1 << 5)
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#define RESETDONE (0x1 << 0)
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* I2C base */
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#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
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#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
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#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
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#endif /* _CPU_H */
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