u-boot/arch/x86/cpu/ivybridge/Makefile

#
# Copyright (c) 2014 Google, Inc
#
# SPDX-License-Identifier:	GPL-2.0+
#

obj-y += car.o
obj-y += cpu.o
obj-y += lpc.o
obj-y += pci.o
obj-y += sdram.o
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:07 +00:00			`#`
			`# Copyright (c) 2014 Google, Inc`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`obj-y += car.o`
			`obj-y += cpu.o`
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:15 +00:00			`obj-y += lpc.o`
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:13 +00:00			`obj-y += pci.o`
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:07 +00:00			`obj-y += sdram.o`