103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
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/*
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* Novena video output support
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/video.h>
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#include <i2c.h>
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#include <input.h>
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#include <ipu_pixfmt.h>
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#include <linux/fb.h>
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#include <linux/input.h>
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#include <malloc.h>
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#include <stdio_dev.h>
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#include "novena.h"
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static void enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {
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{
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/* HDMI Output */
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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},
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},
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};
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size_t display_count = ARRAY_SIZE(displays);
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void setup_display_clock(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
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/* set LDB0, LDB1 clk select to 011/011 */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
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MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
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(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
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(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
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setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
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IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
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IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
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&iomux->gpr[2]);
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clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
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IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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}
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