104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
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/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2003
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* Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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/*****************************************************************************
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* initialize SDRAM/DDRAM controller.
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* TBD: get data from I2C EEPROM
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*****************************************************************************/
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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#if 0
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ulong t;
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ulong tap_del;
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#endif
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#define MODE_EN 0x80000000
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#define SOFT_PRE 2
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#define SOFT_REF 4
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/* configure SDRAM start/end */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x8000000;
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
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#ifdef CFG_DRAM_DDR
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/* set extended mode register */
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*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
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#endif
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/* set mode register */
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*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
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/* set mode register */
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*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
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/* write default TAP delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
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#endif /* CFG_RAMBOOT */
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dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20) +
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((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
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/* return total ram size */
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return dramsize;
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}
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/*****************************************************************************
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* print board identification
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*****************************************************************************/
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int checkboard (void)
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{
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puts ("Board: CANMB\n");
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return 0;
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}
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int board_early_init_r (void)
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{
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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*(vu_long *)MPC5XXX_BOOTCS_START =
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*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
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*(vu_long *)MPC5XXX_BOOTCS_STOP =
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*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
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return 0;
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}
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