ARM: DRA74-evm: Add iodelay values for SR2.0
Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Nishanth Menon
Tom Rini
parent
c1ea3bece2
commit
0358923409
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@ -80,17 +80,33 @@ void set_muxconf_regs_essential(void)
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#ifdef CONFIG_IODELAY_RECALIBRATION
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void recalibrate_iodelay(void)
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{
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if (is_dra72x()) {
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__recalibrate_iodelay(core_padconf_array_essential,
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ARRAY_SIZE(core_padconf_array_essential),
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iodelay_cfg_array,
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ARRAY_SIZE(iodelay_cfg_array));
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} else {
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__recalibrate_iodelay(dra74x_core_padconf_array,
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ARRAY_SIZE(dra74x_core_padconf_array),
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dra742_iodelay_cfg_array,
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ARRAY_SIZE(dra742_iodelay_cfg_array));
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struct pad_conf_entry const *pads;
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struct iodelay_cfg_entry const *iodelay;
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int npads, niodelays;
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switch (omap_revision()) {
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case DRA722_ES1_0:
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pads = core_padconf_array_essential;
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npads = ARRAY_SIZE(core_padconf_array_essential);
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iodelay = iodelay_cfg_array;
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niodelays = ARRAY_SIZE(iodelay_cfg_array);
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break;
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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pads = dra74x_core_padconf_array;
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npads = ARRAY_SIZE(dra74x_core_padconf_array);
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iodelay = dra742_es1_1_iodelay_cfg_array;
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niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
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break;
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default:
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case DRA752_ES2_0:
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pads = dra74x_core_padconf_array;
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npads = ARRAY_SIZE(dra74x_core_padconf_array);
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iodelay = dra742_es2_0_iodelay_cfg_array;
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niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
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break;
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}
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__recalibrate_iodelay(pads, npads, iodelay, niodelays);
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}
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#endif
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@ -376,7 +376,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
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};
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#ifdef CONFIG_IODELAY_RECALIBRATION
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const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
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const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
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{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
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{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
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{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
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@ -431,6 +431,62 @@ const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
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{0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
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{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
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};
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const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
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{0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
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{0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
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{0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
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{0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
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{0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
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{0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
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{0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
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{0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
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{0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
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{0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
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{0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
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{0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
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{0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
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{0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
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{0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
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{0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
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{0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
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{0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
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{0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
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{0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
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{0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
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{0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
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{0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
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{0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
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{0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
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{0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
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{0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
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{0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
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{0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
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{0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
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{0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
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{0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
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{0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
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{0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
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{0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
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{0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
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{0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
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{0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
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{0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
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{0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
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{0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
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{0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
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{0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
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{0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
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{0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
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{0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
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{0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
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{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
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{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
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{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
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{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
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{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
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{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
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};
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#endif
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#endif /* _MUX_DATA_DRA7XX_H_ */
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