MX31: Added support for the Casio COM57H5M10XRC to QONG

The patch adds setup to connect a CASIO COM57H5M10XRC
(640x480 TFT display) to the QONG module.

Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic 2010-05-13 10:26:40 +02:00
parent b4377e12e9
commit 03af5abd85
2 changed files with 32 additions and 17 deletions

View File

@ -56,22 +56,7 @@ void lcd_panel_disable(void)
#define msleep(a) udelay(a * 1000)
#ifndef CONFIG_DISPLAY_VBEST_VGG322403
#define XRES 240
#define YRES 320
#define PANEL_TYPE IPU_PANEL_TFT
#define PIXEL_CLK 185925
#define PIXEL_FMT IPU_PIX_FMT_RGB666
#define H_START_WIDTH 9 /* left_margin */
#define H_SYNC_WIDTH 1 /* hsync_len */
#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */
#define V_START_WIDTH 7 /* upper_margin */
#define V_SYNC_WIDTH 1 /* vsync_len */
#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
#else /* Display Vbest VGG322403 */
#if defined(CONFIG_DISPLAY_VBEST_VGG322403)
#define XRES 320
#define YRES 240
#define PANEL_TYPE IPU_PANEL_TFT
@ -86,6 +71,36 @@ void lcd_panel_disable(void)
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
#elif defined(CONFIG_DISPLAY_COM57H5M10XRC)
#define XRES 640
#define YRES 480
#define PANEL_TYPE IPU_PANEL_TFT
#define PIXEL_CLK 40000
#define PIXEL_FMT IPU_PIX_FMT_RGB666
#define H_START_WIDTH 120 /* left_margin */
#define H_SYNC_WIDTH 30 /* hsync_len */
#define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */
#define V_START_WIDTH 35 /* upper_margin */
#define V_SYNC_WIDTH 3 /* vsync_len */
#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
#else
#define XRES 240
#define YRES 320
#define PANEL_TYPE IPU_PANEL_TFT
#define PIXEL_CLK 185925
#define PIXEL_FMT IPU_PIX_FMT_RGB666
#define H_START_WIDTH 9 /* left_margin */
#define H_SYNC_WIDTH 1 /* hsync_len */
#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */
#define V_START_WIDTH 7 /* upper_margin */
#define V_SYNC_WIDTH 1 /* vsync_len */
#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
#endif
#define LCD_COLOR_IPU LCD_COLOR16

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@ -84,7 +84,7 @@
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_DISPLAY_VBEST_VGG322403
#define CONFIG_DISPLAY_COM57H5M10XRC
/*
* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the