Blackfin: br4: new board port
This adds support for the BR4 Appliance. It is a quad channel ISDN BRI board based on Blackfin BF537 CPU. Signed-off-by: Dimitar Penev <dpn@switchfin.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Dimitar Penev
Mike Frysinger
parent
dae2242ada
commit
051a5f30f1
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@ -1164,6 +1164,7 @@ Chong Huang <chuang@ucrobotics.com>
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Dimitar Penev <dpn@switchfin.org>
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BR4 Appliance BF537
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PR1 Appliance BF537
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#########################################################################
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@ -0,0 +1,50 @@
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#
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# U-boot - Makefile
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#
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# Copyright (c) Switchfin Org. <dpn@switchfin.org>
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#
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# Copyright (c) 2005-2007 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y := $(BOARD).o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,30 @@
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/*
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* U-boot - main board file
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*
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* Copyright (c) Switchfin Org. <dpn@switchfin.org>
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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int checkboard(void)
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{
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printf("Board: Switchvoice BR4 Appliance\n");
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printf(" Support: http://www.switchvoice.com/\n");
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return 0;
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}
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#ifdef CONFIG_BFIN_MAC
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int board_eth_init(bd_t *bis)
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{
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return bfin_EMAC_initialize(bis);
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}
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#endif
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@ -0,0 +1,30 @@
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#
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# Copyright (c) Switchfin Org. <dpn@switchfin.org>
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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CFLAGS_lib += -O2
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CFLAGS_lib/lzma += -O2
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CFLAGS_lib/zlib += -O2
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@ -280,6 +280,7 @@ bf561-acvilon blackfin blackfin
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bf561-ezkit blackfin blackfin
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blackstamp blackfin blackfin
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blackvme blackfin blackfin
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br4 blackfin blackfin
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cm-bf527 blackfin blackfin
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cm-bf533 blackfin blackfin
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cm-bf537e blackfin blackfin
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@ -0,0 +1,157 @@
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/*
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* U-boot - Configuration file for BR4 Appliance
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*
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* based on bf537-stamp.h
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* Copyright (c) Switchfin Org. <dpn@switchfin.org>
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*/
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#ifndef __CONFIG_BR4_H__
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#define __CONFIG_BR4_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf537-0.3
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 24
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_SDRRC_VAL 0x306
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#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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/*
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* Network Settings
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*/
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#ifndef __ADSPBF534__
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_BFIN_MAC
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#define CONFIG_NETCONSOLE
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#endif
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#define CONFIG_HOSTNAME br4
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#define CONFIG_TFTP_BLOCKSIZE 4404
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 5c:38:1a:80:a7:00 */
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/*
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* Flash Settings
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*/
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#define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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/*
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* Env Storage Settings
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*/
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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/*
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* I2C Settings
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*/
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#define CONFIG_BFIN_TWI_I2C
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#define CONFIG_HARD_I2C
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/*
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* NAND Settings
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*/
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#define CONFIG_NAND_PLAT
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#define CONFIG_SYS_NAND_BASE 0x20000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
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#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
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#define BFIN_NAND_WRITE(addr, cmd) \
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do { \
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bfin_write8(addr, cmd); \
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SSYNC(); \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9
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/*
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* Misc Settings
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_SYS_PROMPT "br4>"
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#define CONFIG_BOOTCOMMAND "run nandboot"
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_LOADADDR 0x2000000
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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/*
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* Overwrite some settings defined in bfin_adi_common.h
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*/
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#undef NAND_ENV_SETTINGS
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#define NAND_ENV_SETTINGS \
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"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
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"nandboot=" \
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"nand read $(loadaddr) 0x0 0x900000;" \
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"run nandargs;" \
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"bootm" \
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"\0"
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#endif
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