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Merge branch 'master' of /home/wd/git/u-boot/custodians

This commit is contained in:
Wolfgang Denk 2009-07-23 00:52:30 +02:00
parent 48677a1ef5 5a625149db
commit 05c3734018
31 changed files with 402 additions and 268 deletions
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78
board/freescale/common/pixis.c
View File

@ -39,7 +39,8 @@ static ulong strfractoint(uchar *strptr);
*/
void pixis_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
}
@ -49,6 +50,7 @@ void pixis_reset(void)
int set_px_sysclk(ulong sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) {
case 33:
@ -107,10 +109,10 @@ int set_px_sysclk(ulong sysclk)
vclkh = (sysclk_s << 5) | sysclk_r;
vclkl = sysclk_v;
out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
out_8(pixis_base + PIXIS_VCLKH, vclkh);
out_8(pixis_base + PIXIS_VCLKL, vclkl);
out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
out_8(pixis_base + PIXIS_AUX, sysclk_aux);
return 1;
}
@ -120,6 +122,7 @@ int set_px_mpxpll(ulong mpxpll)
{
u8 tmp;
u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (mpxpll) {
case 2:
@ -137,9 +140,9 @@ int set_px_mpxpll(ulong mpxpll)
return 0;
}
tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
tmp = in_8(pixis_base + PIXIS_VSPEED1);
tmp = (tmp & 0xF0) | (val & 0x0F);
out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
out_8(pixis_base + PIXIS_VSPEED1, tmp);
return 1;
}
@ -149,6 +152,7 @@ int set_px_corepll(ulong corepll)
{
u8 tmp;
u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch ((int)corepll) {
case 20:
@ -174,9 +178,9 @@ int set_px_corepll(ulong corepll)
return 0;
}
tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
tmp = in_8(pixis_base + PIXIS_VSPEED0);
tmp = (tmp & 0xE0) | (val & 0x1F);
out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
out_8(pixis_base + PIXIS_VSPEED0, tmp);
return 1;
}
@ -184,27 +188,29 @@ int set_px_corepll(ulong corepll)
void read_from_px_regs(int set)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
void read_from_px_regs_altbank(int set)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
tmp = tmp | mask;
else
tmp = tmp & ~mask;
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
@ -214,50 +220,54 @@ void read_from_px_regs_altbank(int set)
void clear_altbank(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
out_8(pixis_base + PIXIS_VBOOT, tmp);
}
void set_altbank(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
out_8(pixis_base + PIXIS_VBOOT, tmp);
}
void set_px_go(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E; /* clear GO bit */
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
}
void set_px_go_with_watchdog(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x09;
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
}
@ -265,15 +275,16 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
/* setting VCTL[WDEN] to 0 to disable watch dog */
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp &= ~0x08;
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
out_8(pixis_base + PIXIS_VCTL, tmp);
return 0;
}
@ -288,6 +299,7 @@ U_BOOT_CMD(
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int which_tsec = -1;
u8 *pixis_base = (u8 *)PIXIS_BASE;
uchar mask;
uchar switch_mask;
@ -328,17 +340,15 @@ int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* Toggle whether the switches or FPGA control the settings */
if (!strcmp(argv[argc - 1], "switch"))
clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
switch_mask);
clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
else
setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
switch_mask);
setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
/* If it's not the switches, enable or disable SGMII, as specified */
if (!strcmp(argv[argc - 1], "on"))
clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
else if (!strcmp(argv[argc - 1], "off"))
setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
setbits_8(pixis_base + PIXIS_VSPEED2, mask);
return 0;
}

61
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -60,10 +60,41 @@ int board_early_init_f (void)
int checkboard (void)
{
printf ("Board: MPC8536DS, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts("Board: MPC8536DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
case PIXIS_VBOOT_LBMAP_NOR0:
puts ("vBank: 0\n");
break;
case PIXIS_VBOOT_LBMAP_NOR1:
puts ("vBank: 1\n");
break;
case PIXIS_VBOOT_LBMAP_NOR2:
puts ("vBank: 2\n");
break;
case PIXIS_VBOOT_LBMAP_NOR3:
puts ("vBank: 3\n");
break;
case PIXIS_VBOOT_LBMAP_PJET:
puts ("Promjet\n");
break;
case PIXIS_VBOOT_LBMAP_NAND:
puts ("NAND\n");
break;
}
return 0;
}
@ -498,20 +529,24 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
unsigned long
get_board_sys_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in8(PIXIS_BASE + PIXIS_VSYSCLK0),
in8(PIXIS_BASE + PIXIS_VSYSCLK1),
in8(PIXIS_BASE + PIXIS_VSYSCLK2)
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long
get_board_ddr_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in8(PIXIS_BASE + PIXIS_VDDRCLK0),
in8(PIXIS_BASE + PIXIS_VDDRCLK1),
in8(PIXIS_BASE + PIXIS_VDDRCLK2)
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
@ -520,8 +555,9 @@ get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
@ -559,8 +595,9 @@ get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;

27
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -43,14 +43,22 @@ int checkboard (void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
}
printf ("Board: MPC8544DS, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
if (vboot & PIXIS_VBOOT_FMAP)
printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
else
puts ("Promjet\n");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
@ -383,11 +391,12 @@ get_board_sys_clk(ulong dummy)
{
u8 i, go_bit, rd_clks;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
go_bit = in_8(pixis_base + PIXIS_VCTL);
go_bit &= 0x01;
rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
@ -398,11 +407,11 @@ get_board_sys_clk(ulong dummy)
if (go_bit) {
if (rd_clks == 0x1c)
i = in8(PIXIS_BASE + PIXIS_AUX);
i = in_8(pixis_base + PIXIS_AUX);
else
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
} else {
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
}
i &= 0x07;

48
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -42,14 +42,34 @@ long int fixed_sdram(void);
int checkboard (void)
{
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts ("Board: MPC8572DS ");
#ifdef CONFIG_PHYS_64BIT
puts ("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
case PIXIS_VBOOT_LBMAP_NOR0:
puts ("vBank: 0\n");
break;
case PIXIS_VBOOT_LBMAP_PJET:
puts ("Promjet\n");
break;
case PIXIS_VBOOT_LBMAP_NAND:
puts ("NAND\n");
break;
case PIXIS_VBOOT_LBMAP_NOR1:
puts ("vBank: 1\n");
break;
}
return 0;
}
@ -412,19 +432,23 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
unsigned long get_board_sys_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in8(PIXIS_BASE + PIXIS_VSYSCLK0),
in8(PIXIS_BASE + PIXIS_VSYSCLK1),
in8(PIXIS_BASE + PIXIS_VSYSCLK2)
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long get_board_ddr_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in8(PIXIS_BASE + PIXIS_VDDRCLK0),
in8(PIXIS_BASE + PIXIS_VDDRCLK1),
in8(PIXIS_BASE + PIXIS_VDDRCLK2)
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
@ -432,8 +456,9 @@ unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
@ -470,8 +495,9 @@ unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;

29
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View File

@ -55,16 +55,17 @@ int board_early_init_f(void)
int misc_init_r(void)
{
u8 tmp_val, version;
u8 *pixis_base = (u8 *)PIXIS_BASE;
/*Do not use 8259PIC*/
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
version = in8(PIXIS_BASE + PIXIS_PVER);
version = in_8(pixis_base + PIXIS_PVER);
if(version >= 0x07) {
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
}
/* Using this for DIU init before the driver in linux takes over
@ -96,11 +97,12 @@ int checkboard(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
u8 *pixis_base = (u8 *)PIXIS_BASE;
printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
mcm->abcr |= 0x00010000; /* 0 */
mcm->hpmr3 = 0x80000008; /* 4c */
@ -154,7 +156,7 @@ phys_size_t fixed_sdram(void)
ddr->timing_cfg_0 = 0x00260802;
ddr->timing_cfg_1 = 0x3935d322;
ddr->timing_cfg_2 = 0x14904cc8;
ddr->sdram_mode_1 = 0x00480432;
ddr->sdram_mode = 0x00480432;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
ddr->sdram_data_init = 0xDEADBEEF;
@ -170,7 +172,7 @@ phys_size_t fixed_sdram(void)
udelay(500);
ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@ -438,10 +440,9 @@ get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
ulong a;
u8 *pixis_base = (u8 *)PIXIS_BASE;
a = PIXIS_BASE + PIXIS_SPD;
i = in8(a);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
@ -481,7 +482,9 @@ int board_eth_init(bd_t *bis)
void board_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
while (1)
;

13
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -69,9 +69,10 @@ void mpc8610hpcd_diu_init(void)
unsigned int pixel_format;
unsigned char tmp_val;
unsigned char pixis_arch;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
pixis_arch = in_8(pixis_base + PIXIS_VER);
monitor_port = getenv("monitor");
if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
@ -82,28 +83,28 @@ void mpc8610hpcd_diu_init(void)
else
pixel_format = 0x88883316;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
xres = 1280;
yres = 1024;
pixel_format = 0x88883316;
gamma_fix = 1;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
} else { /* DVI */
xres = 1280;
yres = 1024;
pixel_format = 0x88882317;
gamma_fix = 0;
out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
}
fsl_diu_init(xres, pixel_format, gamma_fix,

39
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -42,10 +42,20 @@ int board_early_init_f(void)
int checkboard(void)
{
printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
if (vboot & PIXIS_VBOOT_FMAP)
printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
else
puts ("Promjet\n");
#ifdef CONFIG_PHYS_64BIT
printf (" 36-bit physical address map\n");
#endif
@ -91,7 +101,7 @@ fixed_sdram(void)
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
@ -109,9 +119,9 @@ fixed_sdram(void)
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#endif
asm("sync; isync");
@ -300,11 +310,12 @@ get_board_sys_clk(ulong dummy)
{
u8 i, go_bit, rd_clks;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
go_bit = in_8(pixis_base + PIXIS_VCTL);
go_bit &= 0x01;
rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
@ -315,11 +326,11 @@ get_board_sys_clk(ulong dummy)
if (go_bit) {
if (rd_clks == 0x1c)
i = in8(PIXIS_BASE + PIXIS_AUX);
i = in_8(pixis_base + PIXIS_AUX);
else
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
} else {
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
}
i &= 0x07;
@ -363,7 +374,9 @@ int board_eth_init(bd_t *bis)
void board_reset(void)
{
out8(PIXIS_BASE + PIXIS_RST, 0);
u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
while (1)
;

45
board/freescale/p2020ds/p2020ds.c
View File

@ -47,14 +47,31 @@ phys_size_t fixed_sdram(void);
int checkboard(void)
{
u8 sw7;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
printf("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
sw7 = in_8(pixis_base + PIXIS_SW(7));
switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
case 0:
case 1:
printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
break;
case 2:
case 3:
puts ("Promjet\n");
break;
}
return 0;
}
@ -462,10 +479,12 @@ unsigned long
calculate_board_sys_clk(ulong dummy)
{
ulong val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
val = ics307_clk_freq(
in8(PIXIS_BASE + PIXIS_VSYSCLK0),
in8(PIXIS_BASE + PIXIS_VSYSCLK1),
in8(PIXIS_BASE + PIXIS_VSYSCLK2));
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2));
debug("sysclk val = %lu\n", val);
return val;
}
@ -474,10 +493,12 @@ unsigned long
calculate_board_ddr_clk(ulong dummy)
{
ulong val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
val = ics307_clk_freq(
in8(PIXIS_BASE + PIXIS_VDDRCLK0),
in8(PIXIS_BASE + PIXIS_VDDRCLK1),
in8(PIXIS_BASE + PIXIS_VDDRCLK2));
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2));
debug("ddrclk val = %lu\n", val);
return val;
}
@ -486,8 +507,9 @@ unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
@ -524,8 +546,9 @@ unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in8(PIXIS_BASE + PIXIS_SPD);
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;

12
board/sbc8641d/sbc8641d.c
View File

@ -127,9 +127,9 @@ long int fixed_sdram (void)
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
@ -140,7 +140,7 @@ long int fixed_sdram (void)
udelay (500);
ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
asm ("sync; isync");
udelay (500);
@ -158,9 +158,9 @@ long int fixed_sdram (void)
ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
@ -171,7 +171,7 @@ long int fixed_sdram (void)
udelay (500);
ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
asm ("sync; isync");
udelay (500);

33
board/tqc/tqm85xx/sdram.c
View File

@ -374,31 +374,6 @@ long int sdram_setup (int casl)
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
void board_add_ram_info (int use_default)
{
int casl;
if (use_default)
casl = CONFIG_DDR_DEFAULT_CL;
else
casl = cas_latency ();
puts (" (CL=");
switch (casl) {
case 20:
puts ("2)");
break;
case 25:
puts ("2.5)");
break;
case 30:
puts ("3)");
break;
}
}
phys_size_t initdram (int board_type)
{
long dram_size = 0;
@ -438,11 +413,9 @@ phys_size_t initdram (int board_type)
/*
* Try again with default CAS latency
*/
puts ("Problem with CAS lantency");
board_add_ram_info (1);
puts (", using default CL!\n");
casl = CONFIG_DDR_DEFAULT_CL;
dram_size = sdram_setup (casl);
printf ("Problem with CAS lantency, using default CL %d/10!\n",
CONFIG_DDR_DEFAULT_CL);
dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
puts (" ");
}

53
board/xes/common/fsl_8xxx_ddr.c
View File

@ -44,56 +44,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
void board_add_ram_info(int use_default)
{
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_MPC85xx)
volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#elif defined(CONFIG_MPC86xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
#endif
#endif
puts(" (");
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
/* Print interleaving information */
if (ddr1->cs0_config & 0x20000000) {
switch ((ddr1->cs0_config >> 24) & 0xf) {
case 0:
puts("cache line");
break;
case 1:
puts("page");
break;
case 2:
puts("bank");
break;
case 3:
puts("super-bank");
break;
default:
puts("invalid");
break;
}
} else {
puts("no");
}
puts(" interleaving");
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
puts(", ");
#endif
#if defined(CONFIG_DDR_ECC)
puts("ECC enabled");
#endif
puts(")");
}
#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */

4
board/xes/xpedite5370/xpedite5370.c
View File

@ -84,8 +84,8 @@ int board_early_init_r(void)
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited

4
cpu/mpc86xx/ddr-8641.c
View File

@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
udelay(200);
asm volatile("sync;isync");
out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/*
* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done

43
cpu/mpc8xxx/ddr/main.c
View File

@ -162,28 +162,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
j++;
}
}
if (j == 2) {
if (j == 2)
*memctl_interleaving = 1;
printf("\nMemory controller interleaving enabled: ");
switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
printf("Cache-line interleaving!\n");
break;
case FSL_DDR_PAGE_INTERLEAVING:
printf("Page interleaving!\n");
break;
case FSL_DDR_BANK_INTERLEAVING:
printf("Bank interleaving!\n");
break;
case FSL_DDR_SUPERBANK_INTERLEAVING:
printf("Super bank interleaving\n");
default:
break;
}
}
/* Check that all controllers are rank interleaving. */
j = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
@ -191,29 +172,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
j++;
}
}
if (j == 2) {
if (j == 2)
*rank_interleaving = 1;
printf("Bank(chip-select) interleaving enabled: ");
switch (pinfo->memctl_opts[0].ba_intlv_ctl &
FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
printf("CS0+CS1+CS2+CS3\n");
break;
case FSL_DDR_CS0_CS1:
printf("CS0+CS1\n");
break;
case FSL_DDR_CS2_CS3:
printf("CS2+CS3\n");
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
printf("CS0+CS1 and CS2+CS3\n");
default:
break;
}
}
if (*memctl_interleaving) {
unsigned long long addr, total_mem_per_ctlr = 0;
/*

96
cpu/mpc8xxx/ddr/util.c
View File

@ -107,3 +107,99 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#elif defined(CONFIG_MPC86xx)
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
uint32_t cs0_config = in_be32(&ddr->cs0_config);
#endif
uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
int cas_lat;
puts(" (DDR");
switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
SDRAM_CFG_SDRAM_TYPE_SHIFT) {
case SDRAM_TYPE_DDR1:
puts("1");
break;
case SDRAM_TYPE_DDR2:
puts("2");
break;
case SDRAM_TYPE_DDR3:
puts("3");
break;
default:
puts("?");
break;
}
if (sdram_cfg & SDRAM_CFG_32_BE)
puts(", 32-bit");
else
puts(", 64-bit");
/* Calculate CAS latency based on timing cfg values */
cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
cas_lat += (8 << 1);
printf(", CL=%d", cas_lat >> 1);
if (cas_lat & 0x1)
puts(".5");
if (sdram_cfg & SDRAM_CFG_ECC_EN)
puts(", ECC on)");
else
puts(", ECC off)");
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
if (cs0_config & 0x20000000) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
switch ((cs0_config >> 24) & 0xf) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
puts("cache line");
break;
case FSL_DDR_PAGE_INTERLEAVING:
puts("page");
break;
case FSL_DDR_BANK_INTERLEAVING:
puts("bank");
break;
case FSL_DDR_SUPERBANK_INTERLEAVING:
puts("super-bank");
break;
default:
puts("invalid");
break;
}
}
#endif
if ((sdram_cfg >> 8) & 0x7f) {
puts("\n");
puts(" DDR Chip-Select Interleaving Mode: ");
switch(sdram_cfg >> 8 & 0x7f) {
case FSL_DDR_CS0_CS1_CS2_CS3:
puts("CS0+CS1+CS2+CS3");
break;
case FSL_DDR_CS0_CS1:
puts("CS0+CS1");
break;
case FSL_DDR_CS2_CS3:
puts("CS2+CS3");
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
puts("CS0+CS1 and CS2+CS3");
break;
default:
puts("invalid");
break;
}
}
}

4
include/asm-ppc/immap_86xx.h
View File

@ -114,9 +114,9 @@ typedef struct ccsr_ddr {
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */

12
include/configs/MPC8536DS.h
View File

@ -45,6 +45,7 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@ -218,6 +219,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
@ -563,10 +571,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8540ADS.h
View File

@ -418,10 +418,10 @@
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8541CDS.h
View File

@ -440,10 +440,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

7
include/configs/MPC8544DS.h
View File

@ -44,6 +44,7 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@ -192,6 +193,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
@ -458,10 +461,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8548CDS.h
View File

@ -500,10 +500,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8555CDS.h
View File

@ -438,10 +438,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8560ADS.h
View File

@ -452,10 +452,10 @@
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8568MDS.h
View File

@ -456,10 +456,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

4
include/configs/MPC8569MDS.h
View File

@ -471,10 +471,10 @@ extern unsigned long get_clock_freq(void);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
/* Initial Memory map for Linux*/
/*

9
include/configs/MPC8572DS.h
View File

@ -237,6 +237,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
@ -607,10 +612,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

2
include/configs/MPC8641HPCN.h
View File

@ -224,6 +224,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */

9
include/configs/P2020DS.h
View File

@ -282,6 +282,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
#define PIXIS_SW(x) 0x20 + (x - 1) * 2
#define PIXIS_EN(x) 0x21 + (x - 1) * 2
#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
@ -636,10 +641,10 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions

1
include/configs/XPEDITE5170.h
View File

@ -579,6 +579,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags

2
include/configs/XPEDITE5200.h
View File

@ -129,6 +129,7 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
@ -369,6 +370,7 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags

11
include/configs/XPEDITE5370.h
View File

@ -124,6 +124,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
/*
* NOR flash configuration
@ -137,6 +143,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
@ -374,16 +381,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
/*
@ -412,6 +420,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags