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DMC: Exynos5: Enable update mode for DREX controller 

As per Exynos5800 UM ver 0.00 section 17.13.2.1
CONCONTROL register bit 3 [update_mode], Exynos5800 does not
support the PHY initiated update. And it is recommanded to
set this field to 1'b1 during initialization. This patch sets this bit.
Applying MC-initiated mode makes DDL tracking ON, that helps in
compensate MIF voltage variation.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Alim Akhtar 2014-11-13 22:38:18 +05:30 committed by Minkyu Kang
parent 79043d84da
commit 061091098a
2 changed files with 20 additions and 0 deletions
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19
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
View File

@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
/*
* As per Exynos5800 UM ver 0.00 section 17.13.2.1
* CONCONTROL register bit 3 [update_mode], Exynos5800 does not
* support the PHY initiated update. And it is recommended to set
* this field to 1'b1 during initialization
*
* When we apply PHY-initiated mode, DLL lock value is determined
* once at DMC init time and not updated later when we change the MIF
* voltage based on ASV group in kernel. Applying MC-initiated mode
* makes sure that DLL tracing is ON so that silicon is able to
* compensate the voltage variation.
*/
val = readl(&drex0->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex0->concontrol);
val = readl(&drex1->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex1->concontrol);
return 0;
}
#endif

1
arch/arm/include/asm/arch-exynos/dmc.h
View File

@ -450,6 +450,7 @@ enum mem_manuf {
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24