Blackfin: bct-brettl2: new board port
Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Peter Meerwald
Mike Frysinger
parent
56f0c57b4b
commit
063993299f
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@ -1041,6 +1041,10 @@ Brent Kandetzki <brentk@teleco.com>
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IP04 BF532
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Peter Meerwald <devel@bct-electronic.com>
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bct-brettl2 BF536
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#########################################################################
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# End of MAINTAINERS list #
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#########################################################################
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@ -0,0 +1,51 @@
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o
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COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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@ -0,0 +1,123 @@
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/*
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* U-boot - main board file for BCT brettl2
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*
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* Copyright (c) 2010 BCT Electronic GmbH
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <asm/blackfin.h>
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#include <asm/portmux.h>
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#include <asm/gpio.h>
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#include <asm/net.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include "../cm-bf537e/gpio_cfi_flash.h"
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#include "smsc9303.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: bct-brettl2 board\n");
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printf(" Support: http://www.bct-electronic.com/\n");
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return 0;
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}
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#ifdef CONFIG_BFIN_MAC
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static void board_init_enetaddr(uchar *mac_addr)
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{
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puts("Warning: Generating 'random' MAC address\n");
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bfin_gen_rand_mac(mac_addr);
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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int board_eth_init(bd_t *bis)
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{
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int retry = 3;
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int ret;
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ret = bfin_EMAC_initialize(bis);
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uchar enetaddr[6];
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if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
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printf("setting MAC %pM\n", enetaddr);
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}
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puts(" ");
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puts("initialize SMSC LAN9303i ethernet switch\n");
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while (retry-- > 0) {
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if (init_smsc9303i_mii())
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return ret;
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}
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return ret;
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}
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#endif
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static void init_tlv320aic31(void)
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{
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puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
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peripheral_request(P_TMR0, "tlv320aic31 clock");
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bfin_write_TIMER0_CONFIG(0x020d);
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bfin_write_TIMER0_PERIOD(0x0008);
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bfin_write_TIMER0_WIDTH(0x0008/2);
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bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
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SSYNC();
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udelay(10000);
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puts(" resetting tlv320aic31\n");
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gpio_request(GPIO_PF2, "tlv320aic31");
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gpio_direction_output(GPIO_PF2, 0);
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udelay(10000);
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gpio_direction_output(GPIO_PF2, 1);
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udelay(10000);
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gpio_free(GPIO_PF2);
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}
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static void init_mute_pin(void)
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{
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printf(" unmute class D amplifier\n");
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gpio_request(GPIO_PF5, "mute");
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gpio_direction_output(GPIO_PF5, 1);
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gpio_free(GPIO_PF5);
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}
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/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
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static void turn_leds_off(void)
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{
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printf(" turn LEDs off\n");
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gpio_request(GPIO_PF6, "led");
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gpio_direction_output(GPIO_PF6, 0);
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gpio_free(GPIO_PF6);
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gpio_request(GPIO_PF15, "led");
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gpio_direction_output(GPIO_PF15, 0);
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gpio_free(GPIO_PF15);
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}
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/* miscellaneous platform dependent initialisations */
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int misc_init_r(void)
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{
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#ifdef CONFIG_BFIN_MAC
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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board_init_enetaddr(enetaddr);
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#endif
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gpio_cfi_flash_init();
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init_tlv320aic31();
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init_mute_pin();
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turn_leds_off();
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return 0;
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}
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@ -0,0 +1,32 @@
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/*
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* cled.c - control color led
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*
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* Copyright (c) 2010 BCT Electronic GmbH
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/blackfin.h>
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#include <asm/io.h>
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int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr = 0x20000000 + 0x200000; // AMS2
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uchar data;
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if (argc < 2)
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return cmd_usage(cmdtp);
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data = simple_strtoul(argv[1], NULL, 10);
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outb(data, addr);
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printf("cled, write %02x\n", data);
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return 0;
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}
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U_BOOT_CMD(cled, 2, 0, do_cled,
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"set/clear color LED",
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"");
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@ -0,0 +1,35 @@
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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CONFIG_BFIN_CPU = bf536-0.3
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CFLAGS_lib += -O2
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CFLAGS_lib/lzma += -O2
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,4 @@
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#define GPIO_PIN_1 GPIO_PG5
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#define GPIO_PIN_2 GPIO_PG6
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#define GPIO_PIN_3 GPIO_PG7
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#include "../cm-bf537e/gpio_cfi_flash.c"
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@ -0,0 +1,176 @@
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/*
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* smsc9303.c - routines to initialize SMSC 9303 switch
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*
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* Copyright (c) 2010 BCT Electronic GmbH
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <config.h>
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#include <miiphy.h>
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#include <asm/blackfin.h>
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#include <asm/gpio.h>
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static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
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{
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const char *devname = miiphy_get_current_dev();
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if (!devname)
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return 0;
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if (miiphy_write(devname, addr, reg, data) != 0)
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return 0;
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return 1;
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}
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static int smc9303i_write_reg(unsigned short reg, unsigned int data)
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{
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const char *devname = miiphy_get_current_dev();
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unsigned char mii_addr = 0x10 | (reg >> 6);
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unsigned char mii_reg = (reg & 0x3c) >> 1;
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if (!devname)
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return 0;
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if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
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return 0;
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if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
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return 0;
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return 1;
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}
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static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
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{
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const char *devname = miiphy_get_current_dev();
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unsigned char mii_addr = 0x10 | (reg >> 6);
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unsigned char mii_reg = (reg & 0x3c) >> 1;
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unsigned short tmp1, tmp2;
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if (!devname)
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return 0;
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if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
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return 0;
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if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
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return 0;
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*data = (tmp2 << 16) | tmp1;
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return 1;
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}
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#if 0
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static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
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{
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const char *devname = miiphy_get_current_dev();
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if (!devname)
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return 0;
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if (miiphy_read(devname, addr, reg, data) != 0)
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return 0;
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return 1;
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}
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#endif
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typedef struct {
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unsigned short reg;
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unsigned int value;
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} smsc9303i_config_entry1_t;
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static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
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{
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{0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
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{0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
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{0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
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};
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typedef struct
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{
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unsigned char addr;
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unsigned char reg;
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unsigned short value;
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} smsc9303i_config_entry2_t;
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static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
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{
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{0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
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{0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
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{0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
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{0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
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{0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
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{0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
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{0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
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{0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
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{0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
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{0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
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{0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
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{0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
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{0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
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{0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
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{0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
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{0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
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{0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
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{0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
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};
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int init_smsc9303i_mii(void)
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{
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unsigned int data;
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unsigned int i;
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printf(" reset SMSC LAN9303i\n");
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gpio_request(GPIO_PG10, "smsc9303");
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gpio_direction_output(GPIO_PG10, 0);
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udelay(10000);
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gpio_direction_output(GPIO_PG10, 1);
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udelay(10000);
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gpio_free(GPIO_PG10);
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#if defined(CONFIG_MII_INIT)
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mii_init();
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#endif
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printf(" write SMSC LAN9303i configuration\n");
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if (!smc9303i_read_reg(0x50, &data))
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return 0;
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if ((data >> 16) != 0x9303) {
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/* chip id not found */
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printf(" error identifying SMSC LAN9303i\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
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const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
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if (!smc9303i_write_reg(entry->reg, entry->value)) {
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printf(" error writing SMSC LAN9303i configuration\n");
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return 0;
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}
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}
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for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
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const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
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if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
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printf(" error writing SMSC LAN9303i configuration\n");
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return 0;
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}
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}
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return 1;
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}
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@ -0,0 +1,9 @@
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/*
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* smsc9303.h - routines to initialize SMSC 9303 switch
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*
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* Copyright (c) 2010 BCT Electronic GmbH
|
||||
*
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* Licensed under the GPL-2 or later.
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||||
*/
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int init_smsc9303i_mii(void);
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@ -279,6 +279,7 @@ atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
|
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atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
|
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favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
|
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hammerhead avr32 at32ap - miromico at32ap700x
|
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bct-brettl2 blackfin blackfin
|
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bf518f-ezbrd blackfin blackfin
|
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bf526-ezbrd blackfin blackfin
|
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bf527-ad7160-eval blackfin blackfin
|
||||
|
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|
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|
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@ -0,0 +1,155 @@
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/*
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||||
* U-boot - Configuration file for BF536 brettl2 board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_BCT_BRETTL2_H__
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#define __CONFIG_BCT_BRETTL2_H__
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#include <asm/config-pre.h>
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|
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|
||||
/*
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||||
* Processor Settings
|
||||
*/
|
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
|
||||
|
||||
|
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/*
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||||
* Clock Settings
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||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
|
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
|
||||
*/
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */
|
||||
#define CONFIG_CLKIN_HZ 16384000
|
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
|
||||
/* 1 = CLKIN / 2 */
|
||||
#define CONFIG_CLKIN_HALF 0
|
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
|
||||
/* 1 = bypass PLL */
|
||||
#define CONFIG_PLL_BYPASS 0
|
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
|
||||
/* Values can range from 0-63 (where 0 means 64) */
|
||||
#define CONFIG_VCO_MULT 24
|
||||
/* CCLK_DIV controls the core clock divider */
|
||||
/* Values can be 1, 2, 4, or 8 ONLY */
|
||||
#define CONFIG_CCLK_DIV 1
|
||||
/* SCLK_DIV controls the system clock divider */
|
||||
/* Values can range from 1-15 */
|
||||
#define CONFIG_SCLK_DIV 3
|
||||
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
|
||||
|
||||
|
||||
/*
|
||||
* Memory Settings
|
||||
*/
|
||||
#define CONFIG_MEM_ADD_WDTH 9
|
||||
#define CONFIG_MEM_SIZE 32
|
||||
|
||||
|
||||
/*
|
||||
* SDRAM Settings
|
||||
*/
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x07f6
|
||||
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
|
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
|
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
|
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
|
||||
|
||||
|
||||
/*
|
||||
* Network Settings
|
||||
*/
|
||||
#ifndef __ADSPBF534__
|
||||
#define ADI_CMDS_NETWORK 1
|
||||
#define CONFIG_BFIN_MAC 1
|
||||
#define CONFIG_NETCONSOLE 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_HOSTNAME brettl2
|
||||
#define CONFIG_IPADDR 192.168.233.224
|
||||
#define CONFIG_GATEWAYIP 192.168.233.1
|
||||
#define CONFIG_SERVERIP 192.168.233.53
|
||||
#define CONFIG_ROOTPATH /romfs/brettl2
|
||||
/* Uncomment next line to use fixed MAC address */
|
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Flash Settings
|
||||
*/
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x4000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
|
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
|
||||
#define ENV_IS_EMBEDDED
|
||||
#else
|
||||
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
|
||||
#endif
|
||||
|
||||
#ifdef ENV_IS_EMBEDDED
|
||||
/* WARNING - the following is hand-optimized to fit within
|
||||
* the sector before the environment sector. If it throws
|
||||
* an error during compilation remove an object here to get
|
||||
* it linked after the configuration sector.
|
||||
*/
|
||||
# define LDS_BOARD_TEXT \
|
||||
arch/blackfin/cpu/traps.o (.text .text.*); \
|
||||
arch/blackfin/cpu/interrupt.o (.text .text.*); \
|
||||
arch/blackfin/cpu/serial.o (.text .text.*); \
|
||||
common/dlmalloc.o (.text .text.*); \
|
||||
lib/crc32.o (.text .text.*); \
|
||||
. = DEFINED(env_offset) ? env_offset : .; \
|
||||
common/env_embedded.o (.text .text.*);
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* I2C Settings
|
||||
*/
|
||||
#define CONFIG_BFIN_TWI_I2C 1
|
||||
#define CONFIG_HARD_I2C 1
|
||||
|
||||
|
||||
/*
|
||||
* Misc Settings
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_LOADADDR 0x800000
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_UART_CONSOLE 0
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup
|
||||
*/
|
||||
#include <configs/bfin_adi_common.h>
|
||||
|
||||
/* disable unnecessary features */
|
||||
#undef CONFIG_BOOTM_RTEMS
|
||||
#undef CONFIG_BZIP2
|
||||
#undef CONFIG_KALLSYMS
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue