Tegra114: Add/enable Dalmore build (T114 reference board)
This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Tom Warren
Tom Warren
parent
94829195ac
commit
07067145de
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#
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# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-dalmore.h"
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_table(tegra114_pinmux_common,
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ARRAY_SIZE(tegra114_pinmux_common));
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pinmux_config_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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}
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@ -0,0 +1,249 @@
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PINMUX_CONFIG_DALMORE_H_
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#define _PINMUX_CONFIG_DALMORE_H_
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#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_DEFAULT, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_##_od, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
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}
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static struct pingroup_config tegra114_pinmux_common[] = {
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/* SDMMC1 pinmux */
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DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_WP_N, SDMMC1, UP, NORMAL, INPUT),
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/* SDMMC3 pinmux */
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DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
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/* SDMMC4 pinmux */
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LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
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/* I2C1 pinmux */
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I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C2 pinmux */
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I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C3 pinmux */
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I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C4 pinmux */
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I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* Power I2C pinmux */
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I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
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/* KBC keys */
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DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PV1, RSVD1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_CS1_N, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_CS2_N, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
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/* GPIOs */
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/* SDMMC1 CD gpio */
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DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
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/* Touch RESET */
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DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
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/* Power rails GPIO */
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DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
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};
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static struct pingroup_config unused_pins_lowpower[] = {
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DEFAULT_PINMUX(GMI_CS0_N, NAND, UP, TRISTATE, OUTPUT),
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DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, TRISTATE, OUTPUT),
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DEFAULT_PINMUX(GMI_CS4_N, NAND, UP, TRISTATE, OUTPUT),
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DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
#endif /* _PINMUX_CONFIG_DALMORE_H_ */
|
||||
|
|
@ -294,6 +294,7 @@ seaboard arm armv7:arm720t seaboard nvidia
|
|||
ventana arm armv7:arm720t ventana nvidia tegra20
|
||||
whistler arm armv7:arm720t whistler nvidia tegra20
|
||||
cardhu arm armv7:arm720t cardhu nvidia tegra30
|
||||
dalmore arm armv7:arm720t dalmore nvidia tegra114
|
||||
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
|
||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||
snowball arm armv7 snowball st-ericsson u8500
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "tegra114-common.h"
|
||||
|
||||
/* Must be off for Dalmore to boot !?!? FIXME */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra114 (Dalmore) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA_ENABLE_UARTD
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_COMMON_H_
|
||||
#define _TEGRA114_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
|
||||
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
|
||||
#define CONFIG_SPL_STACK 0x800ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra114/u-boot-spl.lds"
|
||||
|
||||
#endif /* _TEGRA114_COMMON_H_ */
|
||||
Loading…
Reference in New Issue