gpio: add Tegra186 GPIO driver
Tegra186's GPIO controller register layout is significantly different from previous chips, so add a new driver for it. In fact, there are two different GPIO controllers in Tegra186 that share a similar register layout, but very different port mapping. This driver covers both. The DT binding is already present in the Linux kernel (in linux-next via the Tegra tree so far). Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> # v1 Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren
Tom Warren
parent
601800be22
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074a1fdd27
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@ -0,0 +1,161 @@
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NVIDIA Tegra186 GPIO controllers
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Tegra186 contains two GPIO controllers; a main controller and an "AON"
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controller. This binding document applies to both controllers. The register
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layouts for the controllers share many similarities, but also some significant
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differences. Hence, this document describes closely related but different
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bindings and compatible values.
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The Tegra186 GPIO controller allows software to set the IO direction of, and
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read/write the value of, numerous GPIO signals. Routing of GPIO signals to
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package balls is under the control of a separate pin controller HW block. Two
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major sets of registers exist:
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a) Security registers, which allow configuration of allowed access to the GPIO
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register set. These registers exist in a single contiguous block of physical
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address space. The size of this block, and the security features available,
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varies between the different GPIO controllers.
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Access to this set of registers is not necessary in all circumstances. Code
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that wishes to configure access to the GPIO registers needs access to these
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registers to do so. Code which simply wishes to read or write GPIO data does not
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need access to these registers.
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b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
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controllers, these registers are exposed via multiple "physical aliases" in
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address space, each of which access the same underlying state. See the hardware
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documentation for rationale. Any particular GPIO client is expected to access
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just one of these physical aliases.
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Tegra HW documentation describes a unified naming convention for all GPIOs
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implemented by the SoC. Each GPIO is assigned to a port, and a port may control
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a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
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name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
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or GPIO_PCC3.
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The number of ports implemented by each GPIO controller varies. The number of
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implemented GPIOs within each port varies. GPIO registers within a controller
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are grouped and laid out according to the port they affect.
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The mapping from port name to the GPIO controller that implements that port, and
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the mapping from port name to register offset within a controller, are both
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extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
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describes the port-level mapping. In that file, the naming convention for ports
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matches the HW documentation. The values chosen for the names are alphabetically
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sorted within a particular controller. Drivers need to map between the DT GPIO
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IDs and HW register offsets using a lookup table.
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Each GPIO controller can generate a number of interrupt signals. Each signal
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represents the aggregate status for all GPIOs within a set of ports. Thus, the
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number of interrupt signals generated by a controller varies as a rough function
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of the number of ports it implements. Note that the HW documentation refers to
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both the overall controller HW module and the sets-of-ports as "controllers".
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Each GPIO controller in fact generates multiple interrupts signals for each set
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of ports. Each GPIO may be configured to feed into a specific one of the
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interrupt signals generated by a set-of-ports. The intent is for each generated
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signal to be routed to a different CPU, thus allowing different CPUs to each
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handle subsets of the interrupts within a port. The status of each of these
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per-port-set signals is reported via a separate register. Thus, a driver needs
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to know which status register to observe. This binding currently defines no
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configuration mechanism for this. By default, drivers should use register
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GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
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define a property to configure this.
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Required properties:
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- compatible
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Array of strings.
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One of:
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- "nvidia,tegra186-gpio".
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- "nvidia,tegra186-gpio-aon".
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- reg-names
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Array of strings.
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Contains a list of names for the register spaces described by the reg
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property. May contain the following entries, in any order:
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- "gpio": Mandatory. GPIO control registers. This may cover either:
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a) The single physical alias that this OS should use.
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b) All physical aliases that exist in the controller. This is
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appropriate when the OS is responsible for managing assignment of
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the physical aliases.
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- "security": Optional. Security configuration registers.
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Users of this binding MUST look up entries in the reg property by name,
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using this reg-names property to do so.
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- reg
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Array of (physical base address, length) tuples.
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Must contain one entry per entry in the reg-names property, in a matching
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order.
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- interrupts
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Array of interrupt specifiers.
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The interrupt outputs from the HW block, one per set of ports, in the
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order the HW manual describes them. The number of entries required varies
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depending on compatible value:
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- "nvidia,tegra186-gpio": 6 entries.
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- "nvidia,tegra186-gpio-aon": 1 entry.
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- gpio-controller
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Boolean.
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Marks the device node as a GPIO controller/provider.
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- #gpio-cells
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Single-cell integer.
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Must be <2>.
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Indicates how many cells are used in a consumer's GPIO specifier.
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In the specifier:
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- The first cell is the pin number.
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See <dt-bindings/gpio/tegra186-gpio.h>.
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- The second cell contains flags:
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- Bit 0 specifies polarity
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- 0: Active-high (normal).
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- 1: Active-low (inverted).
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- interrupt-controller
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Boolean.
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Marks the device node as an interrupt controller/provider.
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- #interrupt-cells
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Single-cell integer.
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Must be <2>.
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Indicates how many cells are used in a consumer's interrupt specifier.
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In the specifier:
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- The first cell is the GPIO number.
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See <dt-bindings/gpio/tegra186-gpio.h>.
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- The second cell is contains flags:
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- Bits [3:0] indicate trigger type and level:
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- 1: Low-to-high edge triggered.
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- 2: High-to-low edge triggered.
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- 4: Active high level-sensitive.
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- 8: Active low level-sensitive.
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Valid combinations are 1, 2, 3, 4, 8.
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Example:
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#include <dt-bindings/interrupt-controller/irq.h>
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gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg =
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<0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts =
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<0 47 IRQ_TYPE_LEVEL_HIGH>,
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<0 50 IRQ_TYPE_LEVEL_HIGH>,
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<0 53 IRQ_TYPE_LEVEL_HIGH>,
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<0 56 IRQ_TYPE_LEVEL_HIGH>,
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<0 59 IRQ_TYPE_LEVEL_HIGH>,
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<0 180 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg =
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<0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts =
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<0 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -116,6 +116,14 @@ config TEGRA_GPIO
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Support for the GPIO controller contained in NVIDIA Tegra20 through
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Tegra210.
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config TEGRA186_GPIO
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bool "Tegra186 GPIO driver"
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depends on DM_GPIO
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help
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Support for the GPIO controller contained in NVIDIA Tegra186. This
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covers both the "main" and "AON" controller instances, even though
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they have slightly different register layout.
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config GPIO_UNIPHIER
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bool "UniPhier GPIO"
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depends on ARCH_UNIPHIER
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@ -31,6 +31,7 @@ obj-$(CONFIG_S5P) += s5p_gpio.o
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obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
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obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
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obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
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obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
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obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
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obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
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obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
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@ -8,7 +8,6 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/errno.h>
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/*
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* Copyright (c) 2010-2016, NVIDIA CORPORATION.
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* (based on tegra_gpio.c)
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include <asm/gpio.h>
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "tegra186_gpio_priv.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct tegra186_gpio_port_data {
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const char *name;
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uint32_t offset;
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};
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struct tegra186_gpio_ctlr_data {
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const struct tegra186_gpio_port_data *ports;
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uint32_t port_count;
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};
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struct tegra186_gpio_platdata {
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const char *name;
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uint32_t *regs;
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};
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static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
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uint32_t gpio)
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{
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struct tegra186_gpio_platdata *plat = dev->platdata;
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uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
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return &(plat->regs[index]);
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}
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static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
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bool output)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
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rval = readl(reg);
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if (output)
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rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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else
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rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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writel(rval, reg);
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (output)
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rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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else
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rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
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writel(rval, reg);
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return 0;
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}
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static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
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rval = readl(reg);
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if (val)
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rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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else
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rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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writel(rval, reg);
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return 0;
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}
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static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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return tegra186_gpio_set_out(dev, offset, false);
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}
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static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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int ret;
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ret = tegra186_gpio_set_val(dev, offset, value != 0);
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if (ret)
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return ret;
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return tegra186_gpio_set_out(dev, offset, true);
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}
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static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
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offset);
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else
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
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rval = readl(reg);
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return !!rval;
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}
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static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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return tegra186_gpio_set_val(dev, offset, value != 0);
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}
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static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct fdtdec_phandle_args *args)
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{
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int gpio, port, ret;
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gpio = args->args[0];
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port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
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ret = device_get_child(dev, port, &desc->dev);
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if (ret)
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return ret;
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desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops tegra186_gpio_ops = {
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.direction_input = tegra186_gpio_direction_input,
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.direction_output = tegra186_gpio_direction_output,
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.get_value = tegra186_gpio_get_value,
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.set_value = tegra186_gpio_set_value,
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.get_function = tegra186_gpio_get_function,
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.xlate = tegra186_gpio_xlate,
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};
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/**
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* We have a top-level GPIO device with no actual GPIOs. It has a child device
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* for each port within the controller.
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*/
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static int tegra186_gpio_bind(struct udevice *parent)
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{
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struct tegra186_gpio_platdata *parent_plat = parent->platdata;
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struct tegra186_gpio_ctlr_data *ctlr_data =
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(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
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uint32_t *regs;
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int port, ret;
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/* If this is a child device, there is nothing to do here */
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if (parent_plat)
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return 0;
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regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
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if (regs == (uint32_t *)FDT_ADDR_T_NONE)
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return -ENODEV;
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for (port = 0; port < ctlr_data->port_count; port++) {
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struct tegra186_gpio_platdata *plat;
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struct udevice *dev;
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plat = calloc(1, sizeof(*plat));
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if (!plat)
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return -ENOMEM;
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plat->name = ctlr_data->ports[port].name;
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plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
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ret = device_bind(parent, parent->driver, plat->name, plat,
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-1, &dev);
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if (ret)
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return ret;
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dev->of_offset = parent->of_offset;
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}
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return 0;
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}
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static int tegra186_gpio_probe(struct udevice *dev)
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{
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struct tegra186_gpio_platdata *plat = dev->platdata;
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Only child devices have ports */
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if (!plat)
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return 0;
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uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
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uc_priv->bank_name = plat->name;
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return 0;
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}
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static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
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{"A", 0x2000},
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{"B", 0x3000},
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{"C", 0x3200},
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{"D", 0x3400},
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{"E", 0x2200},
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{"F", 0x2400},
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{"G", 0x4200},
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{"H", 0x1000},
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{"I", 0x0800},
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{"J", 0x5000},
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{"K", 0x5200},
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{"L", 0x1200},
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{"M", 0x5600},
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{"N", 0x0000},
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{"O", 0x0200},
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{"P", 0x4000},
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{"Q", 0x0400},
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{"R", 0x0a00},
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{"T", 0x0600},
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{"X", 0x1400},
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{"Y", 0x1600},
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{"BB", 0x2600},
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{"CC", 0x5400},
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};
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static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
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.ports = tegra186_gpio_main_ports,
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.port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
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};
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static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
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{"S", 0x0200},
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||||
{"U", 0x0400},
|
||||
{"V", 0x0800},
|
||||
{"W", 0x0a00},
|
||||
{"Z", 0x0e00},
|
||||
{"AA", 0x0c00},
|
||||
{"EE", 0x0600},
|
||||
{"FF", 0x0000},
|
||||
};
|
||||
|
||||
static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
|
||||
.ports = tegra186_gpio_aon_ports,
|
||||
.port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
|
||||
};
|
||||
|
||||
static const struct udevice_id tegra186_gpio_ids[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra186-gpio",
|
||||
.data = (ulong)&tegra186_gpio_main_data,
|
||||
},
|
||||
{
|
||||
.compatible = "nvidia,tegra186-gpio-aon",
|
||||
.data = (ulong)&tegra186_gpio_aon_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tegra186_gpio) = {
|
||||
.name = "tegra186_gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.of_match = tegra186_gpio_ids,
|
||||
.bind = tegra186_gpio_bind,
|
||||
.probe = tegra186_gpio_probe,
|
||||
.ops = &tegra186_gpio_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA186_GPIO_PRIV_H_
|
||||
#define _TEGRA186_GPIO_PRIV_H_
|
||||
|
||||
/*
|
||||
* For each GPIO, there are a set of registers than affect it, all packed
|
||||
* back-to-back.
|
||||
*/
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
|
||||
#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
|
||||
|
||||
#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
|
||||
|
||||
#define TEGRA186_GPIO_INPUT 0x08
|
||||
|
||||
#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
|
||||
#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
|
||||
|
||||
#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
|
||||
#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
|
||||
|
||||
#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
|
||||
|
||||
/*
|
||||
* 8 GPIOs are packed into a port. Their registers appear back-to-back in the
|
||||
* port's address space.
|
||||
*/
|
||||
#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
|
||||
#define TEGRA186_GPIO_PER_GPIO_COUNT 8
|
||||
|
||||
/*
|
||||
* Per-port registers are packed immediately following all of a port's
|
||||
* per-GPIO registers.
|
||||
*/
|
||||
#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
|
||||
#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
|
||||
#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
|
||||
|
||||
/*
|
||||
* The registers for multiple ports are packed together back-to-back to form
|
||||
* the overall controller.
|
||||
*/
|
||||
#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* This header provides constants for binding nvidia,tegra186-gpio*.
|
||||
*
|
||||
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
|
||||
* provide names for this.
|
||||
*
|
||||
* The second cell contains standard flag values specified in gpio.h.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
|
||||
#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/* GPIOs implemented by main GPIO controller */
|
||||
#define TEGRA_MAIN_GPIO_PORT_A 0
|
||||
#define TEGRA_MAIN_GPIO_PORT_B 1
|
||||
#define TEGRA_MAIN_GPIO_PORT_C 2
|
||||
#define TEGRA_MAIN_GPIO_PORT_D 3
|
||||
#define TEGRA_MAIN_GPIO_PORT_E 4
|
||||
#define TEGRA_MAIN_GPIO_PORT_F 5
|
||||
#define TEGRA_MAIN_GPIO_PORT_G 6
|
||||
#define TEGRA_MAIN_GPIO_PORT_H 7
|
||||
#define TEGRA_MAIN_GPIO_PORT_I 8
|
||||
#define TEGRA_MAIN_GPIO_PORT_J 9
|
||||
#define TEGRA_MAIN_GPIO_PORT_K 10
|
||||
#define TEGRA_MAIN_GPIO_PORT_L 11
|
||||
#define TEGRA_MAIN_GPIO_PORT_M 12
|
||||
#define TEGRA_MAIN_GPIO_PORT_N 13
|
||||
#define TEGRA_MAIN_GPIO_PORT_O 14
|
||||
#define TEGRA_MAIN_GPIO_PORT_P 15
|
||||
#define TEGRA_MAIN_GPIO_PORT_Q 16
|
||||
#define TEGRA_MAIN_GPIO_PORT_R 17
|
||||
#define TEGRA_MAIN_GPIO_PORT_T 18
|
||||
#define TEGRA_MAIN_GPIO_PORT_X 19
|
||||
#define TEGRA_MAIN_GPIO_PORT_Y 20
|
||||
#define TEGRA_MAIN_GPIO_PORT_BB 21
|
||||
#define TEGRA_MAIN_GPIO_PORT_CC 22
|
||||
|
||||
#define TEGRA_MAIN_GPIO(port, offset) \
|
||||
((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
/* GPIOs implemented by AON GPIO controller */
|
||||
#define TEGRA_AON_GPIO_PORT_S 0
|
||||
#define TEGRA_AON_GPIO_PORT_U 1
|
||||
#define TEGRA_AON_GPIO_PORT_V 2
|
||||
#define TEGRA_AON_GPIO_PORT_W 3
|
||||
#define TEGRA_AON_GPIO_PORT_Z 4
|
||||
#define TEGRA_AON_GPIO_PORT_AA 5
|
||||
#define TEGRA_AON_GPIO_PORT_EE 6
|
||||
#define TEGRA_AON_GPIO_PORT_FF 7
|
||||
|
||||
#define TEGRA_AON_GPIO(port, offset) \
|
||||
((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue