arm: socfpga: Actually enable L2 cache
The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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@ -54,14 +54,23 @@ void enable_caches(void)
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void v7_outer_cache_enable(void)
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void v7_outer_cache_enable(void)
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{
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{
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/* disable the L2 cache */
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/* Disable the L2 cache */
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writel(0, &pl310->pl310_ctrl);
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void v7_outer_cache_disable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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}
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/*
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/*
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