powerpc/85xx: Support for Freescale P1024/P1025 processor
Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors. P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core. Added comments in config_mpc85xx.h to denote single core versions of processors. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala
parent
298f8af17b
commit
093cffbe9a
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@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
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COBJS-$(CONFIG_P1012) += ddr-gen3.o
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COBJS-$(CONFIG_P1013) += ddr-gen3.o
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COBJS-$(CONFIG_P1014) += ddr-gen3.o
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COBJS-$(CONFIG_P1015) += ddr-gen3.o
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COBJS-$(CONFIG_P1016) += ddr-gen3.o
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COBJS-$(CONFIG_P1020) += ddr-gen3.o
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COBJS-$(CONFIG_P1021) += ddr-gen3.o
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COBJS-$(CONFIG_P1022) += ddr-gen3.o
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COBJS-$(CONFIG_P1024) += ddr-gen3.o
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COBJS-$(CONFIG_P1025) += ddr-gen3.o
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COBJS-$(CONFIG_P2010) += ddr-gen3.o
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COBJS-$(CONFIG_P2020) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
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@ -92,11 +96,15 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o
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COBJS-$(CONFIG_P1012) += p1021_serdes.o
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COBJS-$(CONFIG_P1013) += p1022_serdes.o
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COBJS-$(CONFIG_P1014) += p1010_serdes.o
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COBJS-$(CONFIG_P1015) += p1021_serdes.o
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COBJS-$(CONFIG_P1016) += p1021_serdes.o
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COBJS-$(CONFIG_P1017) += p1023_serdes.o
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COBJS-$(CONFIG_P1020) += p1021_serdes.o
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COBJS-$(CONFIG_P1021) += p1021_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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COBJS-$(CONFIG_P1023) += p1023_serdes.o
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COBJS-$(CONFIG_P1024) += p1021_serdes.o
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COBJS-$(CONFIG_P1025) += p1021_serdes.o
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COBJS-$(CONFIG_P2010) += p2020_serdes.o
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COBJS-$(CONFIG_P2020) += p2020_serdes.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
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@ -74,6 +74,10 @@ struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(P1013, P1013_E, 1),
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CPU_TYPE_ENTRY(P1014, P1014_E, 1),
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CPU_TYPE_ENTRY(P1014, P1014, 1),
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CPU_TYPE_ENTRY(P1015, P1015_E, 1),
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CPU_TYPE_ENTRY(P1015, P1015, 1),
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CPU_TYPE_ENTRY(P1016, P1016_E, 1),
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CPU_TYPE_ENTRY(P1016, P1016, 1),
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CPU_TYPE_ENTRY(P1017, P1017, 1),
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CPU_TYPE_ENTRY(P1017, P1017, 1),
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CPU_TYPE_ENTRY(P1020, P1020, 2),
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@ -84,6 +88,10 @@ struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(P1022, P1022_E, 2),
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CPU_TYPE_ENTRY(P1023, P1023, 2),
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CPU_TYPE_ENTRY(P1023, P1023_E, 2),
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CPU_TYPE_ENTRY(P1024, P1024, 2),
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CPU_TYPE_ENTRY(P1024, P1024_E, 2),
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CPU_TYPE_ENTRY(P1025, P1025, 2),
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CPU_TYPE_ENTRY(P1025, P1025_E, 2),
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CPU_TYPE_ENTRY(P2010, P2010, 1),
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CPU_TYPE_ENTRY(P2010, P2010_E, 1),
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CPU_TYPE_ENTRY(P2020, P2020, 2),
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@ -92,20 +92,27 @@
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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/* P1011 is single core version of P1020 */
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#elif defined(CONFIG_P1011)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1012 is single core version of P1021 */
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#elif defined(CONFIG_P1012)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1013 is single core version of P1022 */
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#elif defined(CONFIG_P1013)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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@ -121,6 +128,27 @@
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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/* P1015 is single core version of P1024 */
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#elif defined(CONFIG_P1015)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1016 is single core version of P1025 */
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#elif defined(CONFIG_P1016)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1017 is single core version of P1023 */
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#elif defined(CONFIG_P1017)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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@ -137,6 +165,8 @@
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#elif defined(CONFIG_P1021)
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#define CONFIG_MAX_CPUS 2
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@ -144,6 +174,8 @@
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#elif defined(CONFIG_P1022)
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#define CONFIG_MAX_CPUS 2
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@ -164,6 +196,27 @@
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_P1024)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_P1025)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P2010 is single core version of P2020 */
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#elif defined(CONFIG_P2010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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@ -220,6 +273,7 @@
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#define CONFIG_SYS_P4080_ERRATUM_CPU22
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#define CONFIG_SYS_P4080_ERRATUM_SERDES8
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/* P5010 is single core version of P5020 */
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#elif defined(CONFIG_PPC_P5010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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@ -1048,6 +1048,10 @@
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#define SVR_P1013_E 0x80EF00
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#define SVR_P1014 0x80F101
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#define SVR_P1014_E 0x80F901
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#define SVR_P1015 0x80E502
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#define SVR_P1015_E 0x80ED02
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#define SVR_P1016 0x80E503
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#define SVR_P1016_E 0x80ED03
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#define SVR_P1017 0x80F700
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#define SVR_P1017_E 0x80FF00
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#define SVR_P1020 0x80E400
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@ -1058,6 +1062,10 @@
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#define SVR_P1022_E 0x80EE00
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#define SVR_P1023 0x80F600
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#define SVR_P1023_E 0x80FE00
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#define SVR_P1024 0x80E402
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#define SVR_P1024_E 0x80EC02
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#define SVR_P1025 0x80E403
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#define SVR_P1025_E 0x80EC03
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#define SVR_P2010 0x80E300
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#define SVR_P2010_E 0x80EB00
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#define SVR_P2020 0x80E200
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