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Merge branch 'master' of git://git.denx.de/u-boot-arm 

* 'master' of git://git.denx.de/u-boot-arm:
  arm, davinci: add DAVINCI_MMC_CLKID
  arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
  arm, davinci: da850/dm365 lowlevel cleanup
  omap5: Add omap5_evm board build support.
  omap4/5: Add support for booting with CH.
  omap5: emif: Add emif/ddr configurations required for omap5 evm
  omap5: clocks: Add clocks support for omap5 platform.
  omap5: Add minimal support for omap5430.
  omap: Checkpatch fixes
  omap4: make omap4 code common for future reuse
  GCC4.6: Squash warnings in onenand_base.c
  GCC4.6: Fix common/usb.c on xscale
  OneNAND: Add simple OneNAND SPL
  PXA: vpac270: Enable the new generic MMC driver
  PXA: Cleanup serial_pxa
  PXA: Drop csb226 and innokom boards (unmaintained)
  m28evk: Fix comment about the number of RAM banks
  mx31: Fix checkpatch warnings in generic.c
  mx31: Use proper IO accessor for GPR register
  mx31: Remove duplicate definition for GPR register
  qong: Use generic function for configuring GPR register
  M28EVK: Enable USB HOST support
  iMX28: Add USB HOST driver
  iMX28: Add USB and USB PHY register definitions
  M28: Add memory detection into SPL
  iMX28: Fix ARM vector handling
  M28: Add doc/README.m28 documentation
  M28: Add MMC SPL
  iMX28: Add support for DENX M28EVK board
  iMX28: Add u-boot.sb target to Makefile
  iMX28: Add image header generator tool
  iMX28: Add driver for internal RTC
  iMX28: Add GPMI NAND driver
  iMX28: Add APBH DMA driver
  iMX28: Add SPI driver
  iMX28: Add GPIO control
  iMX28: Add I2C bus driver
  iMX28: Add PINMUX control
  FEC: Add support for iMX28 quirks
  iMX28: Add SSP MMC driver
  iMX28: Initial support for iMX28 CPU
  MX25: zmx25: GCC4.6 fix build warnings
  da850: add new config file for AM18xx
  BeagleBoard: config: Switch to ttyO2
  OMAP3: Change omap3_evm maintainer
  devkit8000: Fix NAND SPL on boards with 256MB NAND
  integrator: enable Vpp and disable flash protection
  integrator: add system controller header
  integrator: make flash writeable on boot
  integrator: use io-accessors for board init
  integrator: move text offset to config
  integrator: pass configs for core modules
  ARM: remove superfluous setting of arch_number in board specific code.
  SPL: Allow ARM926EJS to avoid compiling in the CPU support code
  integrator: do not test first part of the memory
  arm: a320: fix broken timer
  ARM: define CONFIG_MACH_TYPE for all ronetix boards
  dm646x: pass board revision info to kernel
  dm646x: add new configuration for dm6467T
  arm, davinci: Fix setting of the SDRAM configuration register
  arm, davinci: Remove the duplication of LPSC functions
  arm, davinci: Rename AM1808 lowlevel functions to DA850
  da8xxevm: fix build error
  ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
This commit is contained in:
Wolfgang Denk 2011-11-16 20:24:41 +01:00
parent 3844d1c782 75acc4d7c1
commit 0c2dd9a05b
167 changed files with 21369 additions and 6502 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -36,6 +36,7 @@
/u-boot.lds
/u-boot.ubl
/u-boot.dtb
/u-boot.sb
#
# Generated files

15
MAINTAINERS
View File

@ -775,10 +775,6 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
Manikandan Pillai <mani.pillai@ti.com>
omap3_evm ARM ARMV7 (OMAP3xx SoC)
Stelian Pop <stelian.pop@leadtechdesign.com>
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
@ -786,6 +782,10 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Tom Rini <trini@ti.com>
omap3_evm ARM ARMV7 (OMAP3xx SoC)
Tom Rix <Tom.Rix@windriver.com>
omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
@ -817,11 +817,6 @@ Heiko Schocher <hs@denx.de>
magnesium i.MX27
mgcoge3un ARM926EJS (Kirkwood SoC)
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale/pxa
innokom xscale/pxa
Michael Schwingen <michael@schwingen.org>
actux1 xscale/ixp
@ -850,6 +845,7 @@ Aneesh V <aneesh@ti.com>
omap4_panda ARM ARMV7 (OMAP4xx SoC)
omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
omap5_evm ARM ARMV7 (OMAP5xx Soc)
Marek Vasut <marek.vasut@gmail.com>
@ -859,6 +855,7 @@ Marek Vasut <marek.vasut@gmail.com>
palmtc xscale/pxa
vpac270 xscale/pxa
zipitz2 xscale/pxa
m28evk i.MX28
efikamx i.MX51
efikasb i.MX51

14
Makefile
View File

@ -290,16 +290,9 @@ LIBS += lib/libfdt/libfdt.o
LIBS += api/libapi.o
LIBS += post/libpost.o
ifeq ($(SOC),am33xx)
ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),omap3)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),omap4)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
@ -424,6 +417,10 @@ $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
rm $(obj)u-boot-ubl.bin
rm $(obj)spl/u-boot-spl-pad.bin
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@ -791,6 +788,7 @@ clobber: clean
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm

6
README
View File

@ -1027,6 +1027,12 @@ The following options need to be configured:
Define this to use i/o functions instead of macros
(some hardware wont work with macros)
CONFIG_DRIVER_TI_EMAC
Support for davinci emac
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
Define this if you have more then 3 PHYs.
CONFIG_FTGMAC100
Support for Faraday's FTGMAC100 Gigabit SoC Ethernet

11
arch/arm/cpu/arm1136/mx31/generic.c
View File

@ -27,8 +27,6 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#define IOMUXGPR (IOMUXC_BASE + 0x008)
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = GET_PLL_MFI(reg);
@ -89,7 +87,7 @@ static u32 mx31_get_hsp_clk(void)
void mx31_dump_clocks(void)
{
u32 cpufreq = mx31_get_mcu_main_clk();
printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
printf("hsp clock : %dHz\n", mx31_get_hsp_clk());
}
@ -146,14 +144,15 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
void mx31_set_gpr(enum iomux_gp_func gp, char en)
{
u32 l;
struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
l = readl(IOMUXGPR);
l = readl(&iomuxc->gpr);
if (en)
l |= gp;
else
l &= ~gp;
writel(l, IOMUXGPR);
writel(l, &iomuxc->gpr);
}
void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
@ -216,7 +215,7 @@ static char *get_reset_cause(void)
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();

150
arch/arm/cpu/arm920t/a320/timer.c
View File

@ -18,20 +18,35 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
#include <faraday/fttmr010.h>
static ulong timestamp;
static ulong lastdec;
static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_CLOCK 32768
#define TIMER_LOAD_VAL 0xffffffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
int timer_init(void)
{
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
@ -59,106 +74,57 @@ int timer_init(void)
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
/* init the timestamp and lastdec value */
reset_timer_masked();
gd->timer_rate_hz = TIMER_CLOCK;
gd->tbu = gd->tbl = 0;
return 0;
}
/*
* timer without interrupts
*/
/*
* reset time
*/
void reset_timer_masked(void)
{
/* capure current decrementer value time */
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
timestamp = 0; /* start "advancing" time stamp from 0 */
debug("%s(): lastdec = %lx\n", __func__, lastdec);
}
/*
* return timer ticks
*/
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
if (lastdec >= now) {
/*
* normal mode (non roll)
* move stamp fordward with absoulte diff ticks
*/
timestamp += lastdec - now;
} else {
/*
* we have overflow of the count down timer
*
* nts = ts + ld + (TLV - now)
* ts=old stamp, ld=time that passed before passing through -1
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and
* cause problems.
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
debug("%s() returns %lx\n", __func__, timestamp);
return timestamp;
}
/*
* return difference between timer ticks and base
*/
ulong get_timer(ulong base)
{
debug("%s(%lx)\n", __func__, base);
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&tmr->timer3_counter);
debug("%s(%lu)\n", __func__, usec);
while (tmo > 0) {
now = readl(&tmr->timer3_counter);
if (now > last) /* count down timer overflow */
tmo -= TIMER_LOAD_VAL + last - now;
else
tmo -= last - now;
last = now;
}
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
debug("%s()\n", __func__);
return get_timer(0);
struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
gd->tbu++;
gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
{
unsigned long long start;
ulong tmo;
start = get_ticks(); /* get current timestamp */
tmo = usec_to_tick(usec); /* convert usecs to ticks */
while ((get_ticks() - start) < tmo)
; /* loop till time has passed */
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
* get_timer(base) can be used to check for timeouts or
* to measure elasped time relative to an event:
*
* ulong start_time = get_timer(0) sets start_time to the current
* time value.
* get_timer(start_time) returns the time elapsed since then.
*
* The time is used in CONFIG_SYS_HZ units!
*/
ulong get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
}
/*
* Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
debug("%s()\n", __func__);
return CONFIG_SYS_HZ;
return gd->timer_rate_hz;
}

6
arch/arm/cpu/arm926ejs/Makefile
View File

@ -28,6 +28,12 @@ LIB = $(obj)lib$(CPU).o
START = start.o
COBJS = cpu.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE
START :=
endif
endif
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))

2
arch/arm/cpu/arm926ejs/davinci/Makefile
View File

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o timer.o psc.o
COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o
COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o

428
arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c
View File

@ -1,428 +0,0 @@
/*
* SoC-specific lowlevel code for AM1808 and similar chips
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/arch/am1808_lowlevel.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
void am1808_waitloop(unsigned long loopcnt)
{
unsigned long i;
for (i = 0; i < loopcnt; i++)
asm(" NOP");
}
int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
if (reg == davinci_pllc0_regs)
/* Unlock PLL registers. */
clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
/*
* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
* through MMR
*/
clrbits_le32(&reg->pllctl, 0x00000020);
/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
clrbits_le32(&reg->pllctl, 0x00000200);
/* Set PLLEN=0 => PLL BYPASS MODE */
clrbits_le32(&reg->pllctl, 0x00000001);
am1808_waitloop(150);
if (reg == davinci_pllc0_regs) {
/*
* Select the Clock Mode bit 8 as External Clock or On Chip
* Oscilator
*/
dv_maskbits(&reg->pllctl, 0xFFFFFEFF);
setbits_le32(&reg->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
}
/* Clear PLLRST bit to reset the PLL */
clrbits_le32(&reg->pllctl, 0x00000008);
/* Disable the PLL output */
setbits_le32(&reg->pllctl, 0x00000010);
/* PLL initialization sequence */
/*
* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
* power down bit
*/
clrbits_le32(&reg->pllctl, 0x00000002);
/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
clrbits_le32(&reg->pllctl, 0x00000010);
/* Program the required multiplier value in PLLM */
writel(pllmult, &reg->pllm);
/* program the postdiv */
if (reg == davinci_pllc0_regs)
writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
&reg->postdiv);
else
writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
&reg->postdiv);
/*
* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
* no GO operation is currently in progress
*/
while ((readl(&reg->pllstat) & 0x1) == 1)
;
if (reg == davinci_pllc0_regs) {
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, &reg->plldiv1);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, &reg->plldiv2);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, &reg->plldiv3);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, &reg->plldiv4);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, &reg->plldiv5);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, &reg->plldiv6);
writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, &reg->plldiv7);
} else {
writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, &reg->plldiv1);
writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, &reg->plldiv2);
writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, &reg->plldiv3);
}
/*
* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
* transition.
*/
setbits_le32(&reg->pllcmd, 0x01);
/*
* Wait for the GOSTAT bit in PLLSTAT to clear to 0
* (completion of phase alignment).
*/
while ((readl(&reg->pllstat) & 0x1) == 1)
;
/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
am1808_waitloop(200);
/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
setbits_le32(&reg->pllctl, 0x00000008);
/* Wait for PLL to lock. See PLL spec for PLL lock time */
am1808_waitloop(2400);
/*
* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
* mode
*/
setbits_le32(&reg->pllctl, 0x00000001);
/*
* clear EMIFA and EMIFB clock source settings, let them
* run off SYSCLK
*/
if (reg == davinci_pllc0_regs)
dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
return 0;
}
void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state)
{
struct davinci_psc_regs *reg;
dv_reg_p mdstat, mdctl;
if (pscnum == 0) {
reg = davinci_psc0_regs;
mdstat = &reg->psc0.mdstat[module];
mdctl = &reg->psc0.mdctl[module];
} else {
reg = davinci_psc1_regs;
mdstat = &reg->psc1.mdstat[module];
mdctl = &reg->psc1.mdctl[module];
}
/* Wait for any outstanding transition to complete */
while ((readl(&reg->ptstat) & (0x00000001 << domain)))
;
/* If we are already in that state, just return */
if ((readl(mdstat) & 0x1F) == state)
return;
/* Perform transition */
writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
setbits_le32(&reg->ptcmd, (0x00000001 << domain));
/* Wait for transition to complete */
while (readl(&reg->ptstat) & (0x00000001 << domain))
;
/* Wait and verify the state */
while ((readl(mdstat) & 0x1F) != state)
;
}
int am1808_ddr_setup(unsigned int freq)
{
unsigned long tmp;
/* Enable the Clock to DDR2/mDDR */
am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
/* Begin VTP Calibration */
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
/* Polling READY bit to see when VTP calibration is done */
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
while ((tmp & VTP_READY) != VTP_READY)
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
}
writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_CMOSEN_BIT));
setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
(readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
&dv_ddr2_regs_ctrl->sdbcr);
writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
/*
* LPMODEN and MCLKSTOPEN must be set!
* Without this bits set, PSC don;t switch states !!
*/
writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
&dv_ddr2_regs_ctrl->sdrcr);
/* SyncReset the Clock to EMIF3A SDRAM */
am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
/* Enable the Clock to EMIF3A SDRAM */
am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
}
static void am1808_set_mdctl(dv_reg_p mdctl)
{
if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
}
void am1808_psc_init(void)
{
struct davinci_psc_regs *reg;
int i;
/* PSC 0 domain 0 init */
reg = davinci_psc0_regs;
while ((readl(&reg->ptstat) & 0x00000001))
;
for (i = 3; i <= 4 ; i++)
am1808_set_mdctl(&reg->psc0.mdctl[i]);
for (i = 7; i <= 12 ; i++)
am1808_set_mdctl(&reg->psc0.mdctl[i]);
/* Do Always-On Power Domain Transitions */
setbits_le32(&reg->ptcmd, 0x00000001);
while (readl(&reg->ptstat) & 0x00000001)
;
/* PSC1, domain 1 init */
reg = davinci_psc1_regs;
while ((readl(&reg->ptstat) & 0x00000001))
;
am1808_set_mdctl(&reg->psc1.mdctl[3]);
am1808_set_mdctl(&reg->psc1.mdctl[6]);
/* UART1 + UART2 */
for (i = 12 ; i <= 13 ; i++)
am1808_set_mdctl(&reg->psc1.mdctl[i]);
am1808_set_mdctl(&reg->psc1.mdctl[26]);
am1808_set_mdctl(&reg->psc1.mdctl[31]);
/* Do Always-On Power Domain Transitions */
setbits_le32(&reg->ptcmd, 0x00000001);
while (readl(&reg->ptstat) & 0x00000001)
;
}
void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value)
{
clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
}
__attribute__((weak))
void board_gpio_init(void)
{
return;
}
#if defined(CONFIG_NAND_SPL)
void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
/* copy image from NOR to RAM */
memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
(void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE);
/* and jump to it ... */
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
#endif
#if defined(CONFIG_NAND_SPL)
void board_init_f(ulong bootflag)
#else
int arch_cpu_init(void)
#endif
{
/*
* copied from arch/arm/cpu/arm926ejs/start.S
*
* flush v4 I/D caches
*/
asm("mov r0, #0");
asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
asm("mrc p15, 0, r0, c1, c0, 0");
/* clear bits 13, 9:8 (--V- --RS) */
asm("bic r0, r0, #0x00002300");
/* clear bits 7, 2:0 (B--- -CAM) */
asm("bic r0, r0, #0x00000087");
/* set bit 2 (A) Align */
asm("orr r0, r0, #0x00000002");
/* set bit 12 (I) I-Cache */
asm("orr r0, r0, #0x00001000");
asm("mcr p15, 0, r0, c1, c0, 0");
/* Unlock kick registers */
writel(0x83e70b13, &davinci_syscfg_regs->kick0);
writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc,
((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
/* System PSC setup - enable all */
am1808_psc_init();
/* Setup Pinmux */
am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
/* PLL setup */
am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
/* GPIO setup */
board_gpio_init();
/* setup CSn config */
writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
/*
* Fix Power and Emulation Management Register
* see sprufw3a.pdf page 37 Table 24
*/
writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
(CONFIG_SYS_NS16550_COM1 + 0x30));
#if defined(CONFIG_NAND_SPL)
puts("ddr init\n");
am1808_ddr_setup(132);
puts("boot u-boot ...\n");
nand_boot();
#else
am1808_ddr_setup(132);
return 0;
#endif
}

311
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c Normal file
View File

@ -0,0 +1,311 @@
/*
* SoC-specific lowlevel code for DA850
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/pll_defs.h>
void da850_waitloop(unsigned long loopcnt)
{
unsigned long i;
for (i = 0; i < loopcnt; i++)
asm(" NOP");
}
int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
if (reg == davinci_pllc0_regs)
/* Unlock PLL registers. */
clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
/*
* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
* through MMR
*/
clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
/* Set PLLEN=0 => PLL BYPASS MODE */
clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
da850_waitloop(150);
if (reg == davinci_pllc0_regs) {
/*
* Select the Clock Mode bit 8 as External Clock or On Chip
* Oscilator
*/
dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
setbits_le32(&reg->pllctl,
(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
}
/* Clear PLLRST bit to reset the PLL */
clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
/* Disable the PLL output */
setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
/* PLL initialization sequence */
/*
* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
* power down bit
*/
clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
/* Program the required multiplier value in PLLM */
writel(pllmult, &reg->pllm);
/* program the postdiv */
if (reg == davinci_pllc0_regs)
writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
&reg->postdiv);
else
writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
&reg->postdiv);
/*
* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
* no GO operation is currently in progress
*/
while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
;
if (reg == davinci_pllc0_regs) {
writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
} else {
writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
}
/*
* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
* transition.
*/
setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
/*
* Wait for the GOSTAT bit in PLLSTAT to clear to 0
* (completion of phase alignment).
*/
while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
;
/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
da850_waitloop(200);
/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
/* Wait for PLL to lock. See PLL spec for PLL lock time */
da850_waitloop(2400);
/*
* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
* mode
*/
setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
/*
* clear EMIFA and EMIFB clock source settings, let them
* run off SYSCLK
*/
if (reg == davinci_pllc0_regs)
dv_maskbits(&davinci_syscfg_regs->cfgchip3,
~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
return 0;
}
int da850_ddr_setup(void)
{
unsigned long tmp;
/* Enable the Clock to DDR2/mDDR */
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
/* Begin VTP Calibration */
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
/* Polling READY bit to see when VTP calibration is done */
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
while ((tmp & VTP_READY) != VTP_READY)
tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
}
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_CMOSEN_BIT));
/*
* SDRAM Configuration Register (SDCR):
* First set the BOOTUNLOCK bit to make configuration bits
* writeable.
*/
setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
/*
* Write the new value of these bits and clear BOOTUNLOCK.
* At the same time, set the TIMUNLOCK bit to allow changing
* the timing registers
*/
tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
tmp &= ~DV_DDR_BOOTUNLOCK;
tmp |= DV_DDR_TIMUNLOCK;
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* clear the TIMUNLOCK bit and write the value of the CL field */
tmp &= ~DV_DDR_TIMUNLOCK;
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/*
* LPMODEN and MCLKSTOPEN must be set!
* Without this bits set, PSC don;t switch states !!
*/
writel(CONFIG_SYS_DA850_DDR2_SDRCR |
(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
&dv_ddr2_regs_ctrl->sdrcr);
/* SyncReset the Clock to EMIF3A SDRAM */
lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
/* Enable the Clock to EMIF3A SDRAM */
lpsc_on(DAVINCI_LPSC_DDR_EMIF);
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
}
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value)
{
clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
}
__attribute__((weak))
void board_gpio_init(void)
{
return;
}
int arch_cpu_init(void)
{
/* Unlock kick registers */
writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc,
CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
/* Setup Pinmux */
da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
/* PLL setup */
da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
/* GPIO setup */
board_gpio_init();
/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
#endif
#if defined(CONFIG_SYS_DA850_CS3CFG)
writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
#endif
lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
/*
* Fix Power and Emulation Management Register
* see sprufw3a.pdf page 37 Table 24
*/
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart2_ctrl_regs->pwremu_mgmt);
da850_ddr_setup();
return 0;
}

73
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
View File

@ -45,7 +45,8 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
setbits_le32(&dv_pll0_regs->pllctl,
clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@ -82,7 +83,7 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
/* Program the PostDiv for PLL1 */
writel(0x8000, &dv_pll0_regs->postdiv);
writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
/* Post divider setting for PLL1 */
writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
@ -126,7 +127,8 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
* VDB has input on MXI pin
*/
clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
setbits_le32(&dv_pll1_regs->pllctl,
clksrc << PLLCTL_CLOCK_MODE_SHIFT);
/*
* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@ -151,7 +153,7 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
writel(pllm, &dv_pll1_regs->pllm);
writel(prediv, &dv_pll1_regs->prediv);
writel(0x8000, &dv_pll1_regs->postdiv);
writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
@ -261,21 +263,23 @@ void dm365_vpss_sync_reset(void)
VPSS_CLK_CTL_VPSS_CLKMD);
/* LPSC SyncReset DDR Clock Enable */
writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
writel((1 << PdNum), &dv_psc_regs->ptcmd);
while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
;
while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) ==
PSC_SYNCRESET))
while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
PSC_MD_STATE_MSK) == PSC_SYNCRESET))
;
}
void dm365_por_reset(void)
{
if (readl(&dv_pll0_regs->rstype) & 3)
if (readl(&dv_pll0_regs->rstype) &
(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
dm365_vpss_sync_reset();
}
@ -291,19 +295,20 @@ void dm365_psc_init(void)
for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
if (lpscgroup == 0) {
lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
lpsc_end = 28;
/* Enabling LPSC 3 to 28 SCR first */
lpsc_start = DAVINCI_LPSC_VPSSMSTR;
lpsc_end = DAVINCI_LPSC_TIMER1;
} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
lpsc_start = 38;
lpsc_end = 47;
lpsc_start = DAVINCI_LPSC_CFG5;
lpsc_end = DAVINCI_LPSC_VPSSMASTER;
} else {
lpsc_start = 50;
lpsc_end = 51;
lpsc_start = DAVINCI_LPSC_MJCP;
lpsc_end = DAVINCI_LPSC_HDVICP;
}
/* NEXT=0x3, Enable LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
/*
* Program goctl to start transition sequence for LPSCs
@ -322,7 +327,7 @@ void dm365_psc_init(void)
/* Wait for MODSTAT = ENABLE from LPSC's */
for (i = lpsc_start; i <= lpsc_end; i++)
while (!((readl(&dv_psc_regs->mdstat[i]) &
PSC_MD_STATE_MSK) == 0x3))
PSC_MD_STATE_MSK) == PSC_ENABLE))
;
}
}
@ -332,7 +337,7 @@ static void dm365_emif_init(void)
writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
setbits_le32(&davinci_emif_regs->nandfcr, 1);
setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
@ -361,31 +366,12 @@ int post_log(char *format, ...)
void dm36x_lowlevel_init(ulong bootflag)
{
/*
* copied from arch/arm/cpu/arm926ejs/start.S
*
* flush v4 I/D caches
*/
asm("mov r0, #0");
asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
asm("mrc p15, 0, r0, c1, c0, 0");
/* clear bits 13, 9:8 (--V- --RS) */
asm("bic r0, r0, #0x00002300");
/* clear bits 7, 2:0 (B--- -CAM) */
asm("bic r0, r0, #0x00000087");
/* set bit 2 (A) Align */
asm("orr r0, r0, #0x00000002");
/* set bit 12 (I) I-Cache */
asm("orr r0, r0, #0x00001000");
asm("mcr p15, 0, r0, c1, c0, 0");
struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
DAVINCI_UART_CTRL_BASE);
/* Mask all interrupts */
writel(0x04, &dv_aintc_regs->intctl);
writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
writel(0x0, &dv_aintc_regs->eabase);
writel(0x0, &dv_aintc_regs->eint0);
writel(0x0, &dv_aintc_regs->eint1);
@ -422,7 +408,10 @@ void dm36x_lowlevel_init(ulong bootflag)
* Fix Power and Emulation Management Register
* see sprufh2.pdf page 38 Table 22
*/
writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart_ctrl_regs->pwremu_mgmt);
puts("ddr init\n");
dm365_ddr_setup();

11
board/csb226/Makefile → arch/arm/cpu/arm926ejs/mx28/Makefile
View File

@ -23,14 +23,17 @@
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
LIB = $(obj)lib$(SOC).o
COBJS := csb226.o flash.o
COBJS = clock.o mx28.o iomux.o timer.o
SRCS := $(COBJS:.o=.c)
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
START := $(addprefix $(obj),$(START))
$(LIB): $(obj).depend $(OBJS)
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################

355
arch/arm/cpu/arm926ejs/mx28/clock.c Normal file
View File

@ -0,0 +1,355 @@
/*
* Freescale i.MX28 clock setup code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
#define PLL_FREQ_KHZ 480000
#define PLL_FREQ_COEF 18
/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
#define XTAL_FREQ_KHZ 24000
#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
static uint32_t mx28_get_pclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, clkfrac;
uint32_t frac, div;
clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
/* No support of fractional divider calculation */
if (clkctrl &
(CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
return 0;
}
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
/* XTAL Path */
if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
CLKCTRL_CPU_DIV_XTAL_OFFSET;
return XTAL_FREQ_MHZ / div;
}
/* REF Path */
clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_hclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
uint32_t clkctrl;
clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
/* No support of fractional divider calculation */
if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
return 0;
div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
return mx28_get_pclk() / div;
}
static uint32_t mx28_get_emiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t frac, div;
uint32_t clkctrl, clkseq, clkfrac;
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
/* XTAL Path */
if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
CLKCTRL_EMI_DIV_XTAL_OFFSET;
return XTAL_FREQ_MHZ / div;
}
clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
/* REF Path */
frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
CLKCTRL_FRAC0_EMIFRAC_OFFSET;
div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_gpmiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t frac, div;
uint32_t clkctrl, clkseq, clkfrac;
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
/* XTAL Path */
if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return XTAL_FREQ_MHZ / div;
}
clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
/* REF Path */
frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
/*
* Set IO clock frequency, in kHz
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
if (freq == 0)
return;
if (io > MXC_IOCLK1)
return;
div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
if (div < 18)
div = 18;
if (div > 35)
div = 35;
if (io == MXC_IOCLK0) {
writel(CLKCTRL_FRAC0_CLKGATEIO0,
&clkctrl_regs->hw_clkctrl_frac0_set);
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
CLKCTRL_FRAC0_IO0FRAC_MASK,
div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
writel(CLKCTRL_FRAC0_CLKGATEIO0,
&clkctrl_regs->hw_clkctrl_frac0_clr);
} else {
writel(CLKCTRL_FRAC0_CLKGATEIO1,
&clkctrl_regs->hw_clkctrl_frac0_set);
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
CLKCTRL_FRAC0_IO1FRAC_MASK,
div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
writel(CLKCTRL_FRAC0_CLKGATEIO1,
&clkctrl_regs->hw_clkctrl_frac0_clr);
}
}
/*
* Get IO clock, returns IO clock in kHz
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t tmp, ret;
if (io > MXC_IOCLK1)
return 0;
tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
if (io == MXC_IOCLK0)
ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
CLKCTRL_FRAC0_IO0FRAC_OFFSET;
else
ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
CLKCTRL_FRAC0_IO1FRAC_OFFSET;
return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
}
/*
* Configure SSP clock frequency, in kHz
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK3)
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
(ssp * sizeof(struct mx28_register));
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
;
if (xtal)
clk = XTAL_FREQ_KHZ;
else
clk = mx28_get_ioclk(ssp >> 1);
if (freq > clk)
return;
/* Calculate the divider and cap it if necessary */
clk /= freq;
if (clk > CLKCTRL_SSP_DIV_MASK)
clk = CLKCTRL_SSP_DIV_MASK;
clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
while (readl(clkreg) & CLKCTRL_SSP_BUSY)
;
if (xtal)
writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
&clkctrl_regs->hw_clkctrl_clkseq_set);
else
writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
}
/*
* Return SSP frequency, in kHz
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;
if (ssp > MXC_SSPCLK3)
return 0;
tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
return XTAL_FREQ_KHZ;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
(ssp * sizeof(struct mx28_register));
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
if (tmp == 0)
return 0;
clk = mx28_get_ioclk(ssp >> 1);
return clk / tmp;
}
/*
* Set SSP/MMC bus frequency, in kHz)
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mx28_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
for (divide = 2; divide < 254; divide += 2) {
rate = sspclk / freq / divide;
if (rate <= 256)
break;
}
tgtclk = sspclk / divide / rate;
while (tgtclk > freq) {
rate++;
tgtclk = sspclk / divide / rate;
}
if (rate > 256)
rate = 256;
/* Always set timeout the maximum */
reg = SSP_TIMING_TIMEOUT_MASK |
(divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
writel(reg, &ssp_regs->hw_ssp_timing);
debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
bus, tgtclk, freq);
}
uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return mx28_get_pclk() * 1000000;
case MXC_GPMI_CLK:
return mx28_get_gpmiclk() * 1000000;
case MXC_AHB_CLK:
case MXC_IPG_CLK:
return mx28_get_hclk() * 1000000;
case MXC_EMI_CLK:
return mx28_get_emiclk();
case MXC_IO0_CLK:
return mx28_get_ioclk(MXC_IOCLK0);
case MXC_IO1_CLK:
return mx28_get_ioclk(MXC_IOCLK1);
case MXC_SSP0_CLK:
return mx28_get_sspclk(MXC_SSPCLK0);
case MXC_SSP1_CLK:
return mx28_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK:
return mx28_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mx28_get_sspclk(MXC_SSPCLK3);
}
return 0;
}

109
arch/arm/cpu/arm926ejs/mx28/iomux.c Normal file
View File

@ -0,0 +1,109 @@
/*
* Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#if defined(CONFIG_MX23)
#define DRIVE_OFFSET 0x200
#define PULL_OFFSET 0x400
#elif defined(CONFIG_MX28)
#define DRIVE_OFFSET 0x300
#define PULL_OFFSET 0x600
#else
#error "Please select CONFIG_MX23 or CONFIG_MX28"
#endif
/*
* configures a single pad in the iomuxer
*/
int mxs_iomux_setup_pad(iomux_cfg_t pad)
{
u32 reg, ofs, bp, bm;
void *iomux_base = (void *)MXS_PINCTRL_BASE;
struct mx28_register *mxs_reg;
/* muxsel */
ofs = 0x100;
ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
bp = PAD_PIN(pad) % 16 * 2;
bm = 0x3 << bp;
reg = readl(iomux_base + ofs);
reg &= ~bm;
reg |= PAD_MUXSEL(pad) << bp;
writel(reg, iomux_base + ofs);
/* drive */
ofs = DRIVE_OFFSET;
ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
/* mA */
if (PAD_MA_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4;
bm = 0x3 << bp;
reg = readl(iomux_base + ofs);
reg &= ~bm;
reg |= PAD_MA(pad) << bp;
writel(reg, iomux_base + ofs);
}
/* vol */
if (PAD_VOL_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4 + 2;
mxs_reg = (struct mx28_register *)(iomux_base + ofs);
if (PAD_VOL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
writel(1 << bp, &mxs_reg->reg_clr);
}
/* pull */
if (PAD_PULL_VALID(pad)) {
ofs = PULL_OFFSET;
ofs += PAD_BANK(pad) * 0x10;
bp = PAD_PIN(pad);
mxs_reg = (struct mx28_register *)(iomux_base + ofs);
if (PAD_PULL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
writel(1 << bp, &mxs_reg->reg_clr);
}
return 0;
}
int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
{
const iomux_cfg_t *p = pad_list;
int i;
int ret;
for (i = 0; i < count; i++) {
ret = mxs_iomux_setup_pad(*p);
if (ret)
return ret;
p++;
}
return 0;
}

221
arch/arm/cpu/arm926ejs/mx28/mx28.c Normal file
View File

@ -0,0 +1,221 @@
/*
* Freescale i.MX28 common code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000
#define MX28_BLOCK_SFTRST (1 << 31)
#define MX28_BLOCK_CLKGATE (1 << 30)
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(ulong ignored)
{
struct mx28_rtc_regs *rtc_regs =
(struct mx28_rtc_regs *)MXS_RTC_BASE;
/* Wait 1 uS before doing the actual watchdog reset */
writel(1, &rtc_regs->hw_rtc_watchdog);
writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
/* Endless loop, reset will exit from here */
for (;;)
;
}
int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(&reg->reg) & mask) == mask)
break;
udelay(1);
}
return !timeout;
}
int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(&reg->reg) & mask) == 0)
break;
udelay(1);
}
return !timeout;
}
int mx28_reset_block(struct mx28_register *reg)
{
/* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
/* Set SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_set);
/* Wait for CLKGATE being set */
if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
/* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
return 0;
}
void mx28_fixup_vt(uint32_t start_addr)
{
uint32_t *vt = (uint32_t *)0x20;
int i;
for (i = 0; i < 8; i++)
vt[i] = start_addr + (4 * i);
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
mx28_fixup_vt(gd->relocaddr);
return 0;
}
#endif
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
extern uint32_t _start;
mx28_fixup_vt((uint32_t)&_start);
/*
* Enable NAND clock
*/
/* Clear bypass bit */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* Set GPMI clock to ref_gpmi / 12 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
udelay(1000);
/*
* Configure GPIO unit
*/
mxs_gpio_init();
return 0;
}
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
printf("Freescale i.MX28 family\n");
return 0;
}
#endif
int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
return 0;
}
/*
* Initializes on-chip ethernet controllers.
*/
#ifdef CONFIG_CMD_NET
int cpu_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Turn on ENET clocks */
clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
/* Set up ENET PLL for 50 MHz */
/* Power on ENET PLL */
writel(CLKCTRL_PLL2CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
udelay(10);
/* Gate on ENET PLL */
writel(CLKCTRL_PLL2CTRL0_CLKGATE,
&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
/* Enable pad output */
setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
return 0;
}
#endif
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
"display clocks",
""
);

141
arch/arm/cpu/arm926ejs/mx28/timer.c Normal file
View File

@ -0,0 +1,141 @@
/*
* Freescale i.MX28 timer driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
/* Maximum fixed count */
#define TIMER_LOAD_VAL 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->tbl)
#define lastdec (gd->lastinc)
/*
* This driver uses 1kHz clock source.
*/
#define MX28_INCREMENTER_HZ 1000
static inline unsigned long tick_to_time(unsigned long tick)
{
return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
static inline unsigned long time_to_tick(unsigned long time)
{
return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
/* Calculate how many ticks happen in "us" microseconds */
static inline unsigned long us_to_tick(unsigned long us)
{
return (us * MX28_INCREMENTER_HZ) / 1000000;
}
int timer_init(void)
{
struct mx28_timrot_regs *timrot_regs =
(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
/* Reset Timers and Rotary Encoder module */
mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */
writel(0, &timrot_regs->hw_timrot_fixed_count0);
/* Set UPDATE bit and 1Khz frequency */
writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
&timrot_regs->hw_timrot_timctrl0);
/* Set fixed_count to maximal value */
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
return 0;
}
ulong get_timer(ulong base)
{
struct mx28_timrot_regs *timrot_regs =
(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
/* Current tick value */
uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
if (lastdec >= now) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (lastdec - now);
} else {
/* we have rollover of decrementer */
timestamp += (TIMER_LOAD_VAL - now) + lastdec;
}
lastdec = now;
return tick_to_time(timestamp) - base;
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
void __udelay(unsigned long usec)
{
uint32_t old, new, incr;
uint32_t counter = 0;
old = readl(MX28_HW_DIGCTL_MICROSECONDS);
while (counter < usec) {
new = readl(MX28_HW_DIGCTL_MICROSECONDS);
/* Check if the timer wrapped. */
if (new < old) {
incr = 0xffffffff - old;
incr += new;
} else {
incr = new - old;
}
/*
* Check if we are close to the maximum time and the counter
* would wrap if incremented. If that's the case, break out
* from the loop as the requested delay time passed.
*/
if (counter + incr < counter)
break;
counter += incr;
old = new;
}
}

13
arch/arm/cpu/armv7/omap-common/Makefile
View File

@ -33,6 +33,13 @@ ifdef CONFIG_OMAP
COBJS += gpio.o
endif
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
COBJS += hwinit-common.o
COBJS += clocks-common.o
COBJS += emif-common.o
SOBJS += lowlevel_init.o
endif
ifdef CONFIG_SPL_BUILD
COBJS += spl.o
ifdef CONFIG_SPL_NAND_SUPPORT
@ -43,6 +50,12 @@ COBJS += spl_mmc.o
endif
endif
ifndef CONFIG_SPL_BUILD
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
COBJS += mem-common.o
endif
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

609
arch/arm/cpu/armv7/omap-common/clocks-common.c Normal file
View File

@ -0,0 +1,609 @@
/*
*
* Clock initialization for OMAP4
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
* correct for any board over-ride this function in board file
* From ES2.0 onwards you will get this information from
* CM_SYS_CLKSEL
*/
if (omap_revision() == OMAP4430_ES1_0)
ind = OMAP_SYS_CLK_IND_38_4_MHZ;
else {
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl(&prcm->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
}
return ind;
}
u32 get_sys_clk_index(void)
__attribute__ ((weak, alias("__get_sys_clk_index")));
u32 get_sys_clk_freq(void)
{
u8 index = get_sys_clk_index();
return sys_clk_array[index];
}
static inline void do_bypass_dpll(u32 *const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_FAST_RELOCK_BYPASS <<
CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_bypass(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
LDELAY)) {
printf("Bypassing DPLL failed %p\n", base);
}
}
static inline void do_lock_dpll(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_lock(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
&dpll_regs->cm_idlest_dpll, LDELAY)) {
printf("DPLL locking failed for %p\n", base);
hang();
}
}
inline u32 check_for_lock(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
return lock;
}
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
/*
* The Dpll has already been locked by rom code using CH.
* Check if M,N are matching with Ideal nominal opp values.
* If matches, skip the rest otherwise relock.
*/
M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
if ((M != (params->m)) || (N != (params->n))) {
debug("\n %s Dpll locked, but not for ideal M = %d,"
"N = %d values, current values are M = %d,"
"N= %d" , dpll, params->m, params->n,
M, N);
} else {
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
goto setup_post_dividers;
}
}
bypass_dpll(base);
/* Set M & N */
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
temp &= ~CM_CLKSEL_DPLL_N_MASK;
temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
writel(temp, &dpll_regs->cm_clksel_dpll);
/* Lock */
if (lock)
do_lock_dpll(base);
setup_post_dividers:
setup_post_dividers(base, params);
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
}
u32 omap_ddr_clk(void)
{
u32 ddr_clk, sys_clk_khz, omap_rev, divider;
const struct dpll_params *core_dpll_params;
omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
core_dpll_params = get_core_dpll_params();
debug("sys_clk %d\n ", sys_clk_khz * 1000);
/* Find Core DPLL locked frequency first */
ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
(core_dpll_params->n + 1);
if (omap_rev < OMAP5430_ES1_0) {
/*
* DDR frequency is PHY_ROOT_CLK/2
* PHY_ROOT_CLK = Fdpll/2/M2
*/
divider = 4;
} else {
/*
* DDR frequency is PHY_ROOT_CLK
* PHY_ROOT_CLK = Fdpll/2/M2
*/
divider = 2;
}
ddr_clk = ddr_clk / divider / core_dpll_params->m2;
ddr_clk *= 1000; /* convert to Hz */
debug("ddr_clk %d\n ", ddr_clk);
return ddr_clk;
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
void configure_mpu_dpll(void)
{
const struct dpll_params *params;
struct dpll_regs *mpu_dpll_regs;
u32 omap_rev;
omap_rev = omap_revision();
/*
* DCC and clock divider settings for 4460.
* DCC is required, if more than a certain frequency is required.
* For, 4460 > 1GHZ.
* 5430 > 1.4GHZ.
*/
if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
params = get_mpu_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
static void setup_dplls(void)
{
u32 sysclk_ind, temp;
const struct dpll_params *params;
debug("setup_dplls\n");
sysclk_ind = get_sys_clk_index();
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
"core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
writel(temp, &prcm->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
params = get_per_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
/* MPU dpll */
configure_mpu_dpll();
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
static void setup_non_essential_dplls(void)
{
u32 sys_clk_khz, abe_ref_clk;
u32 sysclk_ind, sd_div, num, den;
const struct dpll_params *params;
sysclk_ind = get_sys_clk_index();
sys_clk_khz = get_sys_clk_freq() / 1000;
/* IVA */
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
params = get_iva_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/*
* USB:
* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
* - where CLKINP is sys_clk in MHz
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
params = get_usb_dpll_params();
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
sd_div = num / den;
clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
/* Configure ABE dpll */
params = get_abe_dpll_params();
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
* We need to enable some additional options to achieve
* 196.608MHz from 32768 Hz
*/
setbits_le32(&prcm->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
/* Spend 4 REFCLK cycles at each stage */
clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
#endif
/* Select the right reference clk */
clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
}
#endif
void do_scale_tps62361(u32 reg, u32 volt_mv)
{
u32 temp, step;
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
/*
* Select SET1 in TPS62361:
* VSEL1 is grounded on board. So the following selects
* VSEL1 = 0 and VSEL0 = 1
*/
gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
gpio_set_value(TPS62361_VSEL0_GPIO, 1);
temp = TPS62361_I2C_SLAVE_ADDR |
(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
PRM_VC_VAL_BYPASS_VALID_BIT;
debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
writel(temp, &prcm->prm_vc_val_bypass);
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
&prcm->prm_vc_val_bypass, LDELAY)) {
puts("Scaling voltage failed for vdd_mpu from TPS\n");
}
}
void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
{
u32 temp, offset_code;
u32 step = 12660; /* 12.66 mV represented in uV */
u32 offset = volt_mv;
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
if (omap_revision() == OMAP4430_ES1_0)
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
else
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
offset_code = (offset + step - 1) / step;
/* The code starts at 1 not 0 */
offset_code++;
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
temp = SMPS_I2C_SLAVE_ADDR |
(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
(offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
PRM_VC_VAL_BYPASS_VALID_BIT;
writel(temp, &prcm->prm_vc_val_bypass);
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
&prcm->prm_vc_val_bypass, LDELAY)) {
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
}
}
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
debug("Enable clock domain - %p\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
u32 bound = LDELAY;
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(clkctrl_addr);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
printf("Clock enable failed for 0x%p idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
u32 wait_for_enable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
debug("Enable clock module - %p\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
void freq_update_core(void)
{
u32 freq_config1 = 0;
const struct dpll_params *core_dpll_params;
core_dpll_params = get_core_dpll_params();
/* Put EMIF clock domain in sw wakeup mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
freq_config1 |= (core_dpll_params->m2 <<
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
writel(freq_config1, &prcm->cm_shadow_freq_config1);
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
&prcm->cm_shadow_freq_config1, LDELAY)) {
puts("FREQ UPDATE procedure failed!!");
hang();
}
/* Put EMIF clock domain back in hw auto mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
}
void bypass_dpll(u32 *const base)
{
do_bypass_dpll(base);
wait_for_bypass(base);
}
void lock_dpll(u32 *const base)
{
do_lock_dpll(base);
wait_for_lock(base);
}
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable all UARTs - console will be on one of them */
clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
void setup_sri2c(void)
{
u32 sys_clk_khz, cycles_hi, cycles_low, temp;
sys_clk_khz = get_sys_clk_freq() / 1000;
/*
* Setup the dedicated I2C controller for Voltage Control
* I2C clk - high period 40% low period 60%
*/
cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
/* values to be set in register - less by 5 & 7 respectively */
cycles_hi -= 5;
cycles_low -= 7;
temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
writel(temp, &prcm->prm_vc_cfg_i2c_clk);
/* Disable high speed mode and all advanced features */
writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
}
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
u8 wait_for_enable)
{
u32 i, max = 100;
/* Put the clock domains in SW_WKUP mode */
for (i = 0; (i < max) && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
/* Clock modules that need to be put in HW_AUTO */
for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
enable_clock_module(clk_modules_hw_auto[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
};
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
};
/* Put the clock domains in HW_AUTO mode now */
for (i = 0; (i < max) && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
}
}
void prcm_init(void)
{
switch (omap_hw_init_context()) {
case OMAP_INIT_CONTEXT_SPL:
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
scale_vcores();
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();
enable_non_essential_clocks();
#endif
break;
default:
break;
}
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}

1140
arch/arm/cpu/armv7/omap-common/emif-common.c Normal file
View File

File diff suppressed because it is too large Load Diff

267
arch/arm/cpu/armv7/omap-common/hwinit-common.c Normal file
View File

@ -0,0 +1,267 @@
/*
*
* Common functions for OMAP4/5 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* This is used to verify if the configuration header
* was executed by rom code prior to control of transfer
* to the bootloader. SPL is responsible for saving and
* passing the boot_params pointer to the u-boot.
*/
struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap_bootmode = MMCSD_MODE_FAT;
u32 omap_boot_device(void)
{
return (u32) (boot_params.omap_bootdevice);
}
u32 omap_boot_mode(void)
{
return omap_bootmode;
}
#endif
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
{
int i;
struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
for (i = 0; i < size; i++, pad++)
writew(pad->val, base + pad->offset);
}
static void set_mux_conf_regs(void)
{
switch (omap_hw_init_context()) {
case OMAP_INIT_CONTEXT_SPL:
set_muxconf_regs_essential();
break;
case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
#ifdef CONFIG_SYS_ENABLE_PADS_ALL
set_muxconf_regs_non_essential();
#endif
break;
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
set_muxconf_regs_essential();
#ifdef CONFIG_SYS_ENABLE_PADS_ALL
set_muxconf_regs_non_essential();
#endif
break;
}
}
u32 cortex_rev(void)
{
unsigned int rev;
/* Read Main ID Register (MIDR) */
asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
return rev;
}
void omap_rev_string(char *omap_rev_string)
{
u32 omap_rev = omap_revision();
u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev,
minor_rev);
}
#ifdef CONFIG_SPL_BUILD
static void init_boot_params(void)
{
boot_params_ptr = (u32 *) &boot_params;
}
#endif
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
* Watchdog disable is done always. For the rest what gets done
* depends on the boot mode in which this function is executed
* 1. s_init of SPL running from SRAM
* 2. s_init of U-Boot running from FLASH
* 3. s_init of U-Boot loaded to SDRAM by SPL
* 4. s_init of U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
* Please have a look at the respective functions to see what gets
* done in each of these cases
* This function is called with SRAM stack.
*/
void s_init(void)
{
init_omap_revision();
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
setup_clocks_for_console();
preloader_console_init();
do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
init_boot_params();
#endif
}
/*
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
*/
void wait_for_command_complete(struct watchdog *wd_base)
{
int pending = 1;
do {
pending = readl(&wd_base->wwps);
} while (pending);
}
/*
* Routine: watchdog_init
* Description: Shut down watch dogs
*/
void watchdog_init(void)
{
struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
writel(WD_UNLOCK1, &wd2_base->wspr);
wait_for_command_complete(wd2_base);
writel(WD_UNLOCK2, &wd2_base->wspr);
}
/*
* This function finds the SDRAM size available in the system
* based on DMM section configurations
* This is needed because the size of memory installed may be
* different on different versions of the board
*/
u32 omap_sdram_size(void)
{
u32 section, i, total_size = 0, size, addr;
for (i = 0; i < 4; i++) {
section = __raw_readl(DMM_BASE + i*4);
addr = section & EMIF_SYS_ADDR_MASK;
/* See if the address is valid */
if ((addr >= DRAM_ADDR_SPACE_START) &&
(addr < DRAM_ADDR_SPACE_END)) {
size = ((section & EMIF_SYS_SIZE_MASK) >>
EMIF_SYS_SIZE_SHIFT);
size = 1 << size;
size *= SZ_16M;
total_size += size;
}
}
return total_size;
}
/*
* Routine: dram_init
* Description: sets uboots idea of sdram size
*/
int dram_init(void)
{
sdram_init();
gd->ram_size = omap_sdram_size();
return 0;
}
/*
* Print board information
*/
int checkboard(void)
{
puts(sysinfo.board_string);
return 0;
}
/*
* This function is called by start_armboot. You can reliably use static
* data. Any boot-time function that require static data should be
* called from here
*/
int arch_cpu_init(void)
{
return 0;
}
/*
* get_device_type(): tell if GP/HS/EMU/TST
*/
u32 get_device_type(void)
{
return 0;
}
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
char rev_string_buffer[50];
omap_rev_string(rev_string_buffer);
printf("CPU : %s\n", rev_string_buffer);
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

37
arch/arm/cpu/armv7/omap4/lowlevel_init.S → arch/arm/cpu/armv7/omap-common/lowlevel_init.S
View File

@ -26,8 +26,8 @@
* MA 02111-1307 USA
*/
#include <asm/arch/omap4.h>
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/omap.h>
.global save_boot_params
save_boot_params:
/*
@ -43,21 +43,40 @@ save_boot_params:
cmp r2, r0
blt 1f
/* Store the boot device in omap4_boot_device */
ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
/*
* store the boot params passed from rom code or saved
* and passed by SPL
*/
cmp r0, #0
beq 1f
ldr r1, =boot_params
str r0, [r1]
#ifdef CONFIG_SPL_BUILD
/* Store the boot device in omap_boot_device */
ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
and r2, #BOOT_DEVICE_MASK
ldr r3, =omap4_boot_device
str r2, [r3] @ omap4_boot_device <- r1
ldr r3, =boot_params
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ omap_boot_device <- r1
/* Store the boot mode (raw/FAT) in omap4_boot_mode */
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #2
blt 2f
cmp r2, #7
bgt 2f
/* Store the boot mode (raw/FAT) in omap_boot_mode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
ldr r3, =omap4_boot_mode
ldr r3, =omap_bootmode
str r2, [r3]
#endif
2:
ldrb r2, [r0, #CH_FLAGS_OFFSET]
ldr r3, =boot_params
strb r2, [r3, #CH_FLAGS_OFFSET]
1:
bx lr
#endif
.globl lowlevel_init
lowlevel_init:

0
arch/arm/cpu/armv7/omap4/mem.c → arch/arm/cpu/armv7/omap-common/mem-common.c
View File

9
arch/arm/cpu/armv7/omap-common/spl.c
View File

@ -38,6 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
u32* boot_params_ptr = NULL;
struct spl_image_info spl_image;
/* Define global data structure pointer to it*/
@ -92,12 +93,16 @@ void spl_parse_image_header(const struct image_header *header)
static void jump_to_image_no_args(void)
{
typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
image_entry_noargs_t image_entry =
(image_entry_noargs_t) spl_image.entry_point;
debug("image entry point: 0x%X\n", spl_image.entry_point);
image_entry();
/* Pass the saved boot_params from rom code */
#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU)
image_entry = 0x80100000;
#endif
image_entry((u32 *)&boot_params_ptr);
}
void jump_to_image_no_args(void) __attribute__ ((noreturn));

11
arch/arm/cpu/armv7/omap4/Makefile
View File

@ -25,17 +25,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS += lowlevel_init.o
COBJS += board.o
COBJS += sdram_elpida.o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += sdram_elpida.o
ifndef CONFIG_SPL_BUILD
COBJS += mem.o
COBJS += sys_info.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

384
arch/arm/cpu/armv7/omap4/board.c
View File

@ -1,384 +0,0 @@
/*
*
* Common functions for OMAP4 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/arch/emif.h>
#include <asm/arch/gpio.h>
#include "omap4_mux_data.h"
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap4_boot_device = BOOT_DEVICE_MMC1;
u32 omap4_boot_mode = MMCSD_MODE_FAT;
u32 omap_boot_device(void)
{
return omap4_boot_device;
}
u32 omap_boot_mode(void)
{
return omap4_boot_mode;
}
/*
* Some tuning of IOs for optimal power and performance
*/
static void do_io_settings(void)
{
u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
struct omap4_sys_ctrl_regs *const ctrl =
(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
if (omap4_rev == OMAP4430_ES1_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
else if (omap4_rev == OMAP4430_ES2_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
else
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
/* EMIF2 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
* in turn programmed in the eFuse at manufacturing time after
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_core_voltage_ctrl);
}
if (!readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
if (!readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
}
#endif
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
{
int i;
struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
for (i = 0; i < size; i++, pad++)
writew(pad->val, base + pad->offset);
}
static void set_muxconf_regs_essential(void)
{
do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() >= OMAP4460_ES1_0)
do_set_mux(CONTROL_PADCONF_WKUP,
wkup_padconf_array_essential_4460,
sizeof(wkup_padconf_array_essential_4460) /
sizeof(struct pad_conf_entry));
}
static void set_mux_conf_regs(void)
{
switch (omap4_hw_init_context()) {
case OMAP_INIT_CONTEXT_SPL:
set_muxconf_regs_essential();
break;
case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
set_muxconf_regs_non_essential();
break;
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
set_muxconf_regs_essential();
set_muxconf_regs_non_essential();
break;
}
}
static u32 cortex_a9_rev(void)
{
unsigned int rev;
/* Read Main ID Register (MIDR) */
asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
return rev;
}
static void init_omap4_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int arm_rev = cortex_a9_rev();
switch (arm_rev) {
case MIDR_CORTEX_A9_R0P1:
*omap4_revision = OMAP4430_ES1_0;
break;
case MIDR_CORTEX_A9_R1P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4430_CONTROL_ID_CODE_ES2_0:
*omap4_revision = OMAP4430_ES2_0;
break;
case OMAP4430_CONTROL_ID_CODE_ES2_1:
*omap4_revision = OMAP4430_ES2_1;
break;
case OMAP4430_CONTROL_ID_CODE_ES2_2:
*omap4_revision = OMAP4430_ES2_2;
break;
default:
*omap4_revision = OMAP4430_ES2_0;
break;
}
break;
case MIDR_CORTEX_A9_R1P3:
*omap4_revision = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4460_CONTROL_ID_CODE_ES1_0:
*omap4_revision = OMAP4460_ES1_0;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap4_revision = OMAP4460_ES1_1;
break;
default:
*omap4_revision = OMAP4460_ES1_0;
break;
}
break;
default:
*omap4_revision = OMAP4430_SILICON_ID_INVALID;
break;
}
}
void omap_rev_string(char *omap4_rev_string)
{
u32 omap4_rev = omap_revision();
u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
minor_rev);
}
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
* Watchdog disable is done always. For the rest what gets done
* depends on the boot mode in which this function is executed
* 1. s_init of SPL running from SRAM
* 2. s_init of U-Boot running from FLASH
* 3. s_init of U-Boot loaded to SDRAM by SPL
* 4. s_init of U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
* Please have a look at the respective functions to see what gets
* done in each of these cases
* This function is called with SRAM stack.
*/
void s_init(void)
{
init_omap4_revision();
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
setup_clocks_for_console();
preloader_console_init();
do_io_settings();
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
}
/*
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
*/
void wait_for_command_complete(struct watchdog *wd_base)
{
int pending = 1;
do {
pending = readl(&wd_base->wwps);
} while (pending);
}
/*
* Routine: watchdog_init
* Description: Shut down watch dogs
*/
void watchdog_init(void)
{
struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
writel(WD_UNLOCK1, &wd2_base->wspr);
wait_for_command_complete(wd2_base);
writel(WD_UNLOCK2, &wd2_base->wspr);
}
/*
* This function finds the SDRAM size available in the system
* based on DMM section configurations
* This is needed because the size of memory installed may be
* different on different versions of the board
*/
u32 omap4_sdram_size(void)
{
u32 section, i, total_size = 0, size, addr;
for (i = 0; i < 4; i++) {
section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
addr = section & OMAP44XX_SYS_ADDR_MASK;
/* See if the address is valid */
if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
(addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
size = ((section & OMAP44XX_SYS_SIZE_MASK) >>
OMAP44XX_SYS_SIZE_SHIFT);
size = 1 << size;
size *= SZ_16M;
total_size += size;
}
}
return total_size;
}
/*
* Routine: dram_init
* Description: sets uboots idea of sdram size
*/
int dram_init(void)
{
sdram_init();
gd->ram_size = omap4_sdram_size();
return 0;
}
/*
* Print board information
*/
int checkboard(void)
{
puts(sysinfo.board_string);
return 0;
}
/*
* This function is called by start_armboot. You can reliably use static
* data. Any boot-time function that require static data should be
* called from here
*/
int arch_cpu_init(void)
{
return 0;
}
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
set_pl310_ctrl_reg(1);
}
void v7_outer_cache_disable(void)
{
set_pl310_ctrl_reg(0);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

628
arch/arm/cpu/armv7/omap4/clocks.c
View File

@ -50,7 +50,7 @@
struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
static const u32 sys_clk_array[8] = {
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
@ -79,14 +79,14 @@ static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
{66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
@ -168,7 +168,6 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
@ -179,98 +178,10 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
* correct for any board over-ride this function in board file
* From ES2.0 onwards you will get this information from
* CM_SYS_CLKSEL
*/
if (omap_revision() == OMAP4430_ES1_0)
ind = OMAP_SYS_CLK_IND_38_4_MHZ;
else {
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl(&prcm->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
}
return ind;
}
u32 get_sys_clk_index(void)
__attribute__ ((weak, alias("__get_sys_clk_index")));
u32 get_sys_clk_freq(void)
{
u8 index = get_sys_clk_index();
return sys_clk_array[index];
}
static inline void do_bypass_dpll(u32 *const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_FAST_RELOCK_BYPASS <<
CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_bypass(u32 *const base)
void setup_post_dividers(u32 *const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
LDELAY)) {
printf("Bypassing DPLL failed %p\n", base);
}
}
static inline void do_lock_dpll(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_lock(u32 *const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
&dpll_regs->cm_idlest_dpll, LDELAY)) {
printf("DPLL locking failed for %p\n", base);
hang();
}
}
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
u8 lock)
{
u32 temp;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
bypass_dpll(base);
/* Set M & N */
temp = readl(&dpll_regs->cm_clksel_dpll);
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
temp &= ~CM_CLKSEL_DPLL_N_MASK;
temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
writel(temp, &dpll_regs->cm_clksel_dpll);
/* Lock */
if (lock)
do_lock_dpll(base);
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
@ -284,10 +195,29 @@ static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
writel(params->m6, &dpll_regs->cm_div_m6_dpll);
if (params->m7 >= 0)
writel(params->m7, &dpll_regs->cm_div_m7_dpll);
}
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 omap_rev, sysclk_ind;
omap_rev = omap_revision();
sysclk_ind = get_sys_clk_index();
if (omap_rev == OMAP4430_ES1_0)
return &mpu_dpll_params_1200mhz[sysclk_ind];
else if (omap_rev < OMAP4460_ES1_0)
return &mpu_dpll_params_1600mhz[sysclk_ind];
else
return &mpu_dpll_params_1840mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
@ -306,228 +236,33 @@ const struct dpll_params *get_core_dpll_params(void)
}
}
u32 omap4_ddr_clk(void)
const struct dpll_params *get_per_dpll_params(void)
{
u32 ddr_clk, sys_clk_khz;
const struct dpll_params *core_dpll_params;
sys_clk_khz = get_sys_clk_freq() / 1000;
core_dpll_params = get_core_dpll_params();
debug("sys_clk %d\n ", sys_clk_khz * 1000);
/* Find Core DPLL locked frequency first */
ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
(core_dpll_params->n + 1);
/*
* DDR frequency is PHY_ROOT_CLK/2
* PHY_ROOT_CLK = Fdpll/2/M2
*/
ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
ddr_clk *= 1000; /* convert to Hz */
debug("ddr_clk %d\n ", ddr_clk);
return ddr_clk;
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_1536mhz[sysclk_ind];
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
void configure_mpu_dpll(void)
const struct dpll_params *get_iva_dpll_params(void)
{
const struct dpll_params *params;
struct dpll_regs *mpu_dpll_regs;
u32 omap4_rev, sysclk_ind;
omap4_rev = omap_revision();
sysclk_ind = get_sys_clk_index();
if (omap4_rev == OMAP4430_ES1_0)
params = &mpu_dpll_params_1200mhz[sysclk_ind];
else if (omap4_rev < OMAP4460_ES1_0)
params = &mpu_dpll_params_1584mhz[sysclk_ind];
else
params = &mpu_dpll_params_1840mhz[sysclk_ind];
/* DCC and clock divider settings for 4460 */
if (omap4_rev >= OMAP4460_ES1_0) {
mpu_dpll_regs =
(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
debug("MPU DPLL locked\n");
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_1862mhz[sysclk_ind];
}
static void setup_dplls(void)
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind, temp;
const struct dpll_params *params;
debug("setup_dplls\n");
sysclk_ind = get_sys_clk_index();
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
writel(temp, &prcm->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
debug("PER DPLL locked\n");
/* MPU dpll */
configure_mpu_dpll();
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
static void setup_non_essential_dplls(void)
const struct dpll_params *get_abe_dpll_params(void)
{
u32 sys_clk_khz, abe_ref_clk;
u32 sysclk_ind, sd_div, num, den;
const struct dpll_params *params;
sysclk_ind = get_sys_clk_index();
sys_clk_khz = get_sys_clk_freq() / 1000;
/* IVA */
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
/*
* USB:
* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
* - where CLKINP is sys_clk in MHz
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
params = &usb_dpll_params_1920mhz[sysclk_ind];
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
sd_div = num / den;
clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
params = &abe_dpll_params_32k_196608khz;
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
* We need to enable some additional options to achieve
* 196.608MHz from 32768 Hz
*/
setbits_le32(&prcm->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
/* Spend 4 REFCLK cycles at each stage */
clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
return &abe_dpll_params_32k_196608khz;
#endif
/* Select the right reference clk */
clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
}
static void do_scale_tps62361(u32 reg, u32 volt_mv)
{
u32 temp, step;
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
/*
* Select SET1 in TPS62361:
* VSEL1 is grounded on board. So the following selects
* VSEL1 = 0 and VSEL0 = 1
*/
gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
gpio_set_value(TPS62361_VSEL0_GPIO, 1);
temp = TPS62361_I2C_SLAVE_ADDR |
(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
PRM_VC_VAL_BYPASS_VALID_BIT;
debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
writel(temp, &prcm->prm_vc_val_bypass);
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
&prcm->prm_vc_val_bypass, LDELAY)) {
puts("Scaling voltage failed for vdd_mpu from TPS\n");
}
}
static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
{
u32 temp, offset_code;
u32 step = 12660; /* 12.66 mV represented in uV */
u32 offset = volt_mv;
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
if (omap_revision() == OMAP4430_ES1_0)
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
else
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
offset_code = (offset + step - 1) / step;
/* The code starts at 1 not 0 */
offset_code++;
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
temp = SMPS_I2C_SLAVE_ADDR |
(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
(offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
PRM_VC_VAL_BYPASS_VALID_BIT;
writel(temp, &prcm->prm_vc_val_bypass);
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
&prcm->prm_vc_val_bypass, LDELAY)) {
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
}
}
/*
@ -536,32 +271,16 @@ static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
static void scale_vcores(void)
void scale_vcores(void)
{
u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
u32 volt, omap_rev;
sys_clk_khz = get_sys_clk_freq() / 1000;
setup_sri2c();
/*
* Setup the dedicated I2C controller for Voltage Control
* I2C clk - high period 40% low period 60%
*/
cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
/* values to be set in register - less by 5 & 7 respectively */
cycles_hi -= 5;
cycles_low -= 7;
temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
writel(temp, &prcm->prm_vc_cfg_i2c_clk);
/* Disable high speed mode and all advanced features */
writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
omap4_rev = omap_revision();
omap_rev = omap_revision();
/* TPS - supplies vdd_mpu on 4460 */
if (omap4_rev >= OMAP4460_ES1_0) {
volt = 1430;
if (omap_rev >= OMAP4460_ES1_0) {
volt = 1313;
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
}
@ -576,8 +295,8 @@ static void scale_vcores(void)
*
* 4460 : supplies vdd_core
*/
if (omap4_rev < OMAP4460_ES1_0) {
volt = 1417;
if (omap_rev < OMAP4460_ES1_0) {
volt = 1325;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
} else {
volt = 1200;
@ -593,55 +312,18 @@ static void scale_vcores(void)
* 4430 : supplies vdd_core
* 4460 : not connected
*/
if (omap4_rev < OMAP4460_ES1_0) {
if (omap_rev < OMAP4460_ES1_0) {
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
}
}
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
debug("Enable clock domain - %p\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
u32 bound = LDELAY;
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(clkctrl_addr);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
printf("Clock enable failed for 0x%p idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
u32 wait_for_enable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
debug("Enable clock module - %p\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
static void enable_basic_clocks(void)
void enable_basic_clocks(void)
{
u32 i, max = 100, wait_for_enable = 1;
u32 *const clk_domains_essential[] = {
&prcm->cm_l4per_clkstctrl,
&prcm->cm_l3init_clkstctrl,
@ -651,30 +333,23 @@ static void enable_basic_clocks(void)
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
0
@ -698,40 +373,45 @@ static void enable_basic_clocks(void)
setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
/* Put the clock domains in SW_WKUP mode */
for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
enable_clock_domain(clk_domains_essential[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/* Clock modules that need to be put in HW_AUTO */
for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
enable_clock_module(clk_modules_hw_auto_essential[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
enable_clock_module(clk_modules_explicit_en_essential[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
0
};
/* Put the clock domains in HW_AUTO mode now */
for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
enable_clock_domain(clk_domains_essential[i],
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
}
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
static void enable_non_essential_clocks(void)
void enable_non_essential_clocks(void)
{
u32 i, max = 100, wait_for_enable = 0;
u32 *const clk_domains_non_essential[] = {
&prcm->cm_mpu_m3_clkstctrl,
&prcm->cm_ivahd_clkstctrl,
@ -807,135 +487,13 @@ static void enable_non_essential_clocks(void)
/* Enable all optional functional clocks of DSS */
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
/* Put the clock domains in SW_WKUP mode */
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
enable_clock_domain(clk_domains_non_essential[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
/* Clock modules that need to be put in HW_AUTO */
for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
enable_clock_module(clk_modules_hw_auto_non_essential[i],
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
wait_for_enable);
};
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
i++) {
enable_clock_module(clk_modules_explicit_en_non_essential[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
};
/* Put the clock domains in HW_AUTO mode now */
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
enable_clock_domain(clk_domains_non_essential[i],
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
}
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
void freq_update_core(void)
{
u32 freq_config1 = 0;
const struct dpll_params *core_dpll_params;
core_dpll_params = get_core_dpll_params();
/* Put EMIF clock domain in sw wakeup mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
freq_config1 |= (core_dpll_params->m2 <<
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
writel(freq_config1, &prcm->cm_shadow_freq_config1);
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
&prcm->cm_shadow_freq_config1, LDELAY)) {
puts("FREQ UPDATE procedure failed!!");
hang();
}
/* Put EMIF clock domain back in hw auto mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
}
void bypass_dpll(u32 *const base)
{
do_bypass_dpll(base);
wait_for_bypass(base);
}
void lock_dpll(u32 *const base)
{
do_lock_dpll(base);
wait_for_lock(base);
}
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable all UARTs - console will be on one of them */
clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
void prcm_init(void)
{
switch (omap4_hw_init_context()) {
case OMAP_INIT_CONTEXT_SPL:
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
scale_vcores();
setup_dplls();
setup_non_essential_dplls();
enable_non_essential_clocks();
break;
default:
break;
}
}

1135
arch/arm/cpu/armv7/omap4/emif.c
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File diff suppressed because it is too large Load Diff

167
arch/arm/cpu/armv7/omap4/hwinit.c Normal file
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@ -0,0 +1,167 @@
/*
*
* Common functions for OMAP4 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
#ifdef CONFIG_SPL_BUILD
/*
* Some tuning of IOs for optimal power and performance
*/
void do_io_settings(void)
{
u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
struct omap4_sys_ctrl_regs *const ctrl =
(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
if (omap4_rev == OMAP4430_ES1_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
else if (omap4_rev == OMAP4430_ES2_0)
lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
else
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
/* EMIF2 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
* in turn programmed in the eFuse at manufacturing time after
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_core_voltage_ctrl);
}
if (!readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
if (!readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
}
#endif
void init_omap_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int arm_rev = cortex_rev();
switch (arm_rev) {
case MIDR_CORTEX_A9_R0P1:
*omap4_revision = OMAP4430_ES1_0;
break;
case MIDR_CORTEX_A9_R1P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4_CONTROL_ID_CODE_ES2_0:
*omap4_revision = OMAP4430_ES2_0;
break;
case OMAP4_CONTROL_ID_CODE_ES2_1:
*omap4_revision = OMAP4430_ES2_1;
break;
case OMAP4_CONTROL_ID_CODE_ES2_2:
*omap4_revision = OMAP4430_ES2_2;
break;
default:
*omap4_revision = OMAP4430_ES2_0;
break;
}
break;
case MIDR_CORTEX_A9_R1P3:
*omap4_revision = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
*omap4_revision = OMAP4460_ES1_0;
break;
default:
*omap4_revision = OMAP4430_SILICON_ID_INVALID;
break;
}
}
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
set_pl310_ctrl_reg(1);
}
void v7_outer_cache_disable(void)
{
set_pl310_ctrl_reg(0);
}
#endif

83
arch/arm/cpu/armv7/omap4/omap4_mux_data.h
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@ -1,83 +0,0 @@
/*
* (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com>
*
* Balaji Krishnamoorthy <balajitk@ti.com>
* Aneesh V <aneesh@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _OMAP4_MUX_DATA_H_
#define _OMAP4_MUX_DATA_H_
#include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)} /* uart3_tx */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
};
const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
};
#endif /* _OMAP4_MUX_DATA_H_ */

2
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View File

@ -26,7 +26,7 @@
* MA 02111-1307 USA
*/
#include <asm/arch/emif.h>
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
/*

48
arch/arm/cpu/armv7/omap5/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += sdram_elpida.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

432
arch/arm/cpu/armv7/omap5/clocks.c Normal file
View File

@ -0,0 +1,432 @@
/*
*
* Clock initialization for OMAP5
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif
struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
0, /* NA */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
0, /* NA */
38400000, /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
{665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
{532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
void setup_post_dividers(u32 *const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->h11 >= 0)
writel(params->h11, &dpll_regs->cm_div_h11_dpll);
if (params->h12 >= 0)
writel(params->h12, &dpll_regs->cm_div_h12_dpll);
if (params->h13 >= 0)
writel(params->h13, &dpll_regs->cm_div_h13_dpll);
if (params->h14 >= 0)
writel(params->h14, &dpll_regs->cm_div_h14_dpll);
if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
}
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &mpu_dpll_params_1100mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
/* Configuring the DDR to be at 532mhz */
return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
}
const struct dpll_params *get_per_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_768mhz[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_2330mhz[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(void)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
return &abe_dpll_params_32k_196608khz;
#endif
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(void)
{
u32 volt;
setup_sri2c();
/* Enable 1.22V from TPS for vdd_mpu */
volt = 1220;
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
/* VCORE 1 - for vdd_core */
volt = 1000;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
/* VCORE 2 - for vdd_MM */
volt = 1125;
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 *const clk_domains_essential[] = {
&prcm->cm_l4per_clkstctrl,
&prcm->cm_l3init_clkstctrl,
&prcm->cm_memif_clkstctrl,
&prcm->cm_l4cfg_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
u32 *const clk_modules_hw_auto_essential[] = {
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 *const clk_domains_non_essential[] = {
&prcm->cm_mpu_m3_clkstctrl,
&prcm->cm_ivahd_clkstctrl,
&prcm->cm_dsp_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sgx_clkstctrl,
&prcm->cm1_abe_clkstctrl,
&prcm->cm_c2c_clkstctrl,
&prcm->cm_cam_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sdma_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_non_essential[] = {
&prcm->cm_mpu_m3_mpu_m3_clkctrl,
&prcm->cm_ivahd_ivahd_clkctrl,
&prcm->cm_ivahd_sl2_clkctrl,
&prcm->cm_dsp_dsp_clkctrl,
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
&prcm->cm_l3init_hsusbtll_clkctrl,
0
};
u32 *const clk_modules_explicit_en_non_essential[] = {
&prcm->cm1_abe_aess_clkctrl,
&prcm->cm1_abe_pdm_clkctrl,
&prcm->cm1_abe_dmic_clkctrl,
&prcm->cm1_abe_mcasp_clkctrl,
&prcm->cm1_abe_mcbsp1_clkctrl,
&prcm->cm1_abe_mcbsp2_clkctrl,
&prcm->cm1_abe_mcbsp3_clkctrl,
&prcm->cm1_abe_slimbus_clkctrl,
&prcm->cm1_abe_timer5_clkctrl,
&prcm->cm1_abe_timer6_clkctrl,
&prcm->cm1_abe_timer7_clkctrl,
&prcm->cm1_abe_timer8_clkctrl,
&prcm->cm1_abe_wdt3_clkctrl,
&prcm->cm_l4per_gptimer9_clkctrl,
&prcm->cm_l4per_gptimer10_clkctrl,
&prcm->cm_l4per_gptimer11_clkctrl,
&prcm->cm_l4per_gptimer3_clkctrl,
&prcm->cm_l4per_gptimer4_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
&prcm->cm_l4per_mcspi2_clkctrl,
&prcm->cm_l4per_mcspi3_clkctrl,
&prcm->cm_l4per_mcspi4_clkctrl,
&prcm->cm_l4per_mmcsd3_clkctrl,
&prcm->cm_l4per_mmcsd4_clkctrl,
&prcm->cm_l4per_mmcsd5_clkctrl,
&prcm->cm_l4per_uart1_clkctrl,
&prcm->cm_l4per_uart2_clkctrl,
&prcm->cm_l4per_uart4_clkctrl,
&prcm->cm_wkup_keyboard_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_cam_iss_clkctrl,
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
&prcm->cm_l3init_fsusb_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

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#
# Copyright 2011 Linaro Limited
# See file CREDITS for list of people who contributed to this
# project.
#
# Aneesh V <annesh@ti.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
else
ALL-y += $(obj)u-boot.img
endif

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/*
* EMIF programming
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com> for OMAP4
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
.RL = 8,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
/*
* Min tCK values specified by JESD209-2
* Min tCK specifies the minimum duration of some AC timing parameters in terms
* of the number of cycles. If the calculated number of cycles based on the
* absolute time value is less than the min tCK value, min tCK value should
* be used instead. This typically happens at low frequencies.
*/
static const struct lpddr2_min_tck min_tck_jedec = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings const*
jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_532_mhz
};
static const struct lpddr2_device_timings jedec_default_timings = {
.ac_timings = jedec_ac_timings,
.min_tck = &min_tck_jedec
};
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
/* Assume Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &jedec_default_timings;
*cs1_device_timings = NULL;
}
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */

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/*
*
* Functions for omap5 based boards.
*
* (C) Copyright 2011
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
* Sricharan <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
static struct gpio_bank gpio_bank_54xx[6] = {
{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD
/*
* Some tuning of IOs for optimal power and performance
*/
void do_io_settings(void)
{
}
#endif
void init_omap_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int rev = cortex_rev();
switch (rev) {
case MIDR_CORTEX_A15_R0P0:
*omap5_revision = OMAP5430_ES1_0;
default:
*omap5_revision = OMAP5430_SILICON_ID_INVALID;
}
}

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/*
* Timing and Organization details of the Elpida parts used in OMAP5
* EVM
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
/*
* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
* EVM. Since the parts used and geometry are identical for
* evm for a given OMAP5 revision, this information is kept
* here instead of being in board directory. However the key functions
* exported are weakly linked so that they can be over-ridden in the board
* directory if there is a OMAP5 board in the future that uses a different
* memory device or geometry.
*
* For any new board with different memory devices over-ride one or more
* of the following functions as per the CONFIG flags you intend to enable:
* - emif_get_reg_dump()
* - emif_get_dmm_regs()
* - emif_get_device_details()
* - emif_get_device_timings()
*/
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
const struct emif_regs emif_regs_elpida_532_mhz_1cs = {
.sdram_config_init = 0x80801aB2,
.sdram_config = 0x808022B2,
.ref_ctrl = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304A129A,
.sdram_tim3 = 0x02F7E45F,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x000B3215,
.temp_alert_config = 0x08000A05,
.emif_ddr_phy_ctlr_1_init = 0x0E38200D,
.emif_ddr_phy_ctlr_1 = 0x0E38200D
};
const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80640300
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
*regs = &emif_regs_elpida_532_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
*dmm_lisa_regs = &lisa_map_4G_x_1_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
#else
static const struct lpddr2_device_details elpida_4G_S4_details = {
.type = LPDDR2_TYPE_S4,
.density = LPDDR2_DENSITY_4Gb,
.io_width = LPDDR2_IO_WIDTH_32,
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
static void emif_get_device_details_sdp(u32 emif_nr,
struct lpddr2_device_details *cs0_device_details,
struct lpddr2_device_details *cs1_device_details)
{
/* EMIF1 & EMIF2 have identical configuration */
*cs0_device_details = elpida_4G_S4_details;
/* Nothing is conected on cs1 */
cs1_device_details = NULL;
}
void emif_get_device_details(u32 emif_nr,
struct lpddr2_device_details *cs0_device_details,
struct lpddr2_device_details *cs1_device_details)
__attribute__((weak, alias("emif_get_device_details_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
.RL = 8,
.tRPab = 21,
.tRCD = 18,
.tWR = 15,
.tRASmin = 42,
.tRRD = 10,
.tWTRx2 = 15,
.tXSR = 140,
.tXPx2 = 15,
.tRFCab = 130,
.tRTPx2 = 15,
.tCKE = 3,
.tCKESR = 15,
.tZQCS = 90,
.tZQCL = 360,
.tZQINIT = 1000,
.tDQSCKMAXx2 = 11,
.tRASmax = 70,
.tFAW = 50
};
static const struct lpddr2_min_tck min_tck_elpida = {
.tRL = 3,
.tRP_AB = 3,
.tRCD = 3,
.tWR = 3,
.tRAS_MIN = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
&timings_jedec_532_mhz
};
static const struct lpddr2_device_timings elpida_4G_S4_timings = {
.ac_timings = elpida_ac_timings,
.min_tck = &min_tck_elpida,
};
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
{
/* Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &elpida_4G_S4_timings;
*cs1_device_timings = NULL;
}
void emif_get_device_timings(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */

2
arch/arm/include/asm/arch-davinci/aintc_defs.h
View File

@ -47,4 +47,6 @@ struct dv_aintc_regs {
#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
#define DV_AINTC_INTCTL_IDMODE (1 << 2)
#endif /* _DV_AINTC_DEFS_H_ */

26
arch/arm/include/asm/arch-davinci/am1808_lowlevel.h → arch/arm/include/asm/arch-davinci/da850_lowlevel.h
View File

@ -1,5 +1,5 @@
/*
* SoC-specific lowlevel code for AM1808 and similar chips
* SoC-specific lowlevel code for DA850
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
@ -21,24 +21,24 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __AM1808_LOWLEVEL_H
#define __AM1808_LOWLEVEL_H
#ifndef __DA850_LOWLEVEL_H
#define __DA850_LOWLEVEL_H
/* NOR Boot Configuration Word Field Descriptions */
#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8)
#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4)
#define AM1808_NORBOOT_16BIT (1 << 0)
#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
#define DA850_NORBOOT_16BIT (1 << 0)
#define dv_maskbits(addr, val) \
writel((readl(addr) & val), addr)
void am1808_waitloop(unsigned long loopcnt);
int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
void da850_waitloop(unsigned long loopcnt);
int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
void da850_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state);
int am1808_ddr_setup(unsigned int freq);
void am1808_psc_init(void);
void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
int da850_ddr_setup(void);
void da850_psc_init(void);
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value);
#endif /* #ifndef __AM1808_LOWLEVEL_H */
#endif /* #ifndef __DA850_LOWLEVEL_H */

4
arch/arm/include/asm/arch-davinci/ddr2_defs.h
View File

@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl {
#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
#define DV_DDR_SDTMR2_XP_SHIFT 25
#define DV_DDR_SDTMR2_ODT_SHIFT 23
#define DV_DDR_SDTMR2_XSNR_SHIFT 16
#define DV_DDR_SDTMR2_XSRD_SHIFT 8
#define DV_DDR_SDTMR2_RTP_SHIFT 5
@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl {
#define DV_DDR_SDCR_IBANK_SHIFT 4
#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
#define DV_DDR_SDRCR_LPMODEN (1 << 31)
#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
#define DV_DDR_SRCR_LPMODEN_SHIFT 31
#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30

1
arch/arm/include/asm/arch-davinci/emif_defs.h
View File

@ -70,6 +70,7 @@ struct davinci_emif_regs {
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)

22
arch/arm/include/asm/arch-davinci/hardware.h
View File

@ -230,6 +230,9 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_LPSC_CFG5 38
#define DAVINCI_LPSC_GEM 39
#define DAVINCI_LPSC_IMCOP 40
#define DAVINCI_LPSC_VPSSMASTER 47
#define DAVINCI_LPSC_MJCP 50
#define DAVINCI_LPSC_HDVICP 51
#define DAVINCI_DM646X_LPSC_EMAC 14
#define DAVINCI_DM646X_LPSC_UART0 26
@ -385,6 +388,20 @@ struct davinci_psc_regs {
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
struct davinci_uart_ctrl_regs {
dv_reg revid1;
dv_reg res;
dv_reg pwremu_mgmt;
dv_reg mdr;
};
#define DAVINCI_UART_CTRL_BASE 0x28
/* UART PWREMU_MGMT definitions */
#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
#else /* CONFIG_SOC_DA8XX */
struct davinci_pllc_regs {
@ -431,6 +448,7 @@ struct davinci_pllc_regs {
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
DAVINCI_ARM_CLKID = 6,
DAVINCI_PLLM_CLKID = 0xff,
@ -468,6 +486,7 @@ struct davinci_syscfg_regs {
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
struct davinci_syscfg1_regs {
@ -491,6 +510,9 @@ struct davinci_syscfg1_regs {
#define VTP_READY (1 << 15)
#define VTP_IOPWRDWN (1 << 14)
#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
/* Interrupt controller */
struct davinci_aintc_regs {
dv_reg revid;

14
arch/arm/include/asm/arch-davinci/pll_defs.h
View File

@ -57,11 +57,24 @@ struct dv_pll_regs {
unsigned int plldiv9; /* 0x174 */
};
#define PLL_MASTER_LOCK (1 << 4)
#define PLLCTL_CLOCK_MODE_SHIFT 8
#define PLLCTL_PLLEN (1 << 0)
#define PLLCTL_PLLPWRDN (1 << 1)
#define PLLCTL_PLLRST (1 << 3)
#define PLLCTL_PLLDIS (1 << 4)
#define PLLCTL_PLLENSRC (1 << 5)
#define PLLCTL_RES_9 (1 << 8)
#define PLLCTL_EXTCLKSRC (1 << 9)
#define PLL_POSTDEN (1 << 15)
#define PLL_SCSCFG3_DIV45PENA (1 << 2)
#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
#define PLL_RSTYPE_POR (1 << 0)
#define PLL_RSTYPE_XWRST (1 << 1)
#define PLLSECCTL_TINITZ (1 << 16)
#define PLLSECCTL_TENABLE (1 << 17)
@ -69,6 +82,7 @@ struct dv_pll_regs {
#define PLLSECCTL_STOPMODE (1 << 22)
#define PLLCMD_GOSET (1 << 0)
#define PLLCMD_GOSTAT (1 << 0)
#define PLL0_LOCK 0x07000000
#define PLL1_LOCK 0x07000000

61
arch/arm/include/asm/arch-mx28/clock.h Normal file
View File

@ -0,0 +1,61 @@
/*
* Freescale i.MX28 Clock
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __CLOCK_H__
#define __CLOCK_H__
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_EMI_CLK,
MXC_GPMI_CLK,
MXC_IO0_CLK,
MXC_IO1_CLK,
MXC_SSP0_CLK,
MXC_SSP1_CLK,
MXC_SSP2_CLK,
MXC_SSP3_CLK,
};
enum mxs_ioclock {
MXC_IOCLK0 = 0,
MXC_IOCLK1,
};
enum mxs_sspclock {
MXC_SSPCLK0 = 0,
MXC_SSPCLK1,
MXC_SSPCLK2,
MXC_SSPCLK3,
};
uint32_t mxc_get_clock(enum mxc_clock clk);
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
#endif /* __CLOCK_H__ */

170
arch/arm/include/asm/arch-mx28/dma.h Normal file
View File

@ -0,0 +1,170 @@
/*
* Freescale i.MX28 APBH DMA
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __DMA_H__
#define __DMA_H__
#include <linux/list.h>
#ifndef CONFIG_ARCH_DMA_PIO_WORDS
#define DMA_PIO_WORDS 15
#else
#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
#endif
#define MXS_DMA_ALIGNMENT 32
/*
* MXS DMA channels
*/
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_SSP2,
MXS_DMA_CHANNEL_AHB_APBH_SSP3,
MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
MXS_DMA_CHANNEL_AHB_APBH_SSP,
MXS_MAX_DMA_CHANNELS,
};
/*
* MXS DMA hardware command.
*
* This structure describes the in-memory layout of an entire DMA command,
* including space for the maximum number of PIO accesses. See the appropriate
* reference manual for a detailed description of what these fields mean to the
* DMA hardware.
*/
#define MXS_DMA_DESC_COMMAND_MASK 0x3
#define MXS_DMA_DESC_COMMAND_OFFSET 0
#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
#define MXS_DMA_DESC_CHAIN (1 << 2)
#define MXS_DMA_DESC_IRQ (1 << 3)
#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
#define MXS_DMA_DESC_DEC_SEM (1 << 6)
#define MXS_DMA_DESC_WAIT4END (1 << 7)
#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
#define MXS_DMA_DESC_BYTES_OFFSET 16
struct mxs_dma_cmd {
unsigned long next;
unsigned long data;
union {
dma_addr_t address;
unsigned long alternate;
};
unsigned long pio_words[DMA_PIO_WORDS];
};
/*
* MXS DMA command descriptor.
*
* This structure incorporates an MXS DMA hardware command structure, along
* with metadata.
*/
#define MXS_DMA_DESC_FIRST (1 << 0)
#define MXS_DMA_DESC_LAST (1 << 1)
#define MXS_DMA_DESC_READY (1 << 31)
struct mxs_dma_desc {
struct mxs_dma_cmd cmd;
unsigned int flags;
dma_addr_t address;
void *buffer;
struct list_head node;
};
/**
* MXS DMA channel
*
* This structure represents a single DMA channel. The MXS platform code
* maintains an array of these structures to represent every DMA channel in the
* system (see mxs_dma_channels).
*/
#define MXS_DMA_FLAGS_IDLE 0
#define MXS_DMA_FLAGS_BUSY (1 << 0)
#define MXS_DMA_FLAGS_FREE 0
#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
#define MXS_DMA_FLAGS_VALID (1 << 31)
struct mxs_dma_chan {
const char *name;
unsigned long dev;
struct mxs_dma_device *dma;
unsigned int flags;
unsigned int active_num;
unsigned int pending_num;
struct list_head active;
struct list_head done;
};
/* Hardware management ops */
int mxs_dma_enable(int channel);
int mxs_dma_disable(int channel);
int mxs_dma_reset(int channel);
int mxs_dma_freeze(int channel);
int mxs_dma_unfreeze(int channel);
int mxs_dma_read_semaphore(int channel);
int mxs_dma_enable_irq(int channel, int enable);
int mxs_dma_irq_is_pending(int channel);
int mxs_dma_ack_irq(int channel);
/* Channel management ops */
int mxs_dma_request(int channel);
int mxs_dma_release(int channel);
/* Descriptor management ops */
struct mxs_dma_desc *mxs_dma_desc_alloc(void);
void mxs_dma_desc_free(struct mxs_dma_desc *);
unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc);
int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
int mxs_dma_get_finished(int channel, struct list_head *head);
int mxs_dma_finish(int channel, struct list_head *head);
int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan);
int mxs_dma_go(int chan);
int mxs_dma_init(void);
#endif /* __DMA_H__ */

32
arch/arm/include/asm/arch-mx28/gpio.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Freescale i.MX28 GPIO
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_GPIO_H__
#define __MX28_GPIO_H__
#ifdef CONFIG_MXS_GPIO
void mxs_gpio_init(void);
#else
inline void mxs_gpio_init(void) {}
#endif
#endif /* __MX28_GPIO_H__ */

39
arch/arm/include/asm/arch-mx28/imx-regs.h Normal file
View File

@ -0,0 +1,39 @@
/*
* Freescale i.MX28 Registers
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
#include <asm/arch/regs-apbh.h>
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-bch.h>
#include <asm/arch/regs-clkctrl.h>
#include <asm/arch/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-ocotp.h>
#include <asm/arch/regs-pinctrl.h>
#include <asm/arch/regs-power.h>
#include <asm/arch/regs-rtc.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
#endif /* __IMX_REGS_H__ */

537
arch/arm/include/asm/arch-mx28/iomux-mx28.h Normal file
View File

@ -0,0 +1,537 @@
/*
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_IOMUX_MX28_H__
#define __MACH_IOMUX_MX28_H__
#include <asm/arch/iomux.h>
/*
* The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
* See also iomux.h
*
* BANK PIN MUX
*/
/* MUXSEL_0 */
#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
/* MUXSEL_1 */
#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
/* MUXSEL_2 */
#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
/* MUXSEL_GPIO */
#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
#endif /* __MACH_IOMUX_MX28_H__ */

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arch/arm/include/asm/arch-mx28/iomux.h Normal file
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/*
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_MXS_IOMUX_H__
#define __MACH_MXS_IOMUX_H__
/*
* IOMUX/PAD Bit field definitions
*
* PAD_BANK: 0..2 (3)
* PAD_PIN: 3..7 (5)
* PAD_MUXSEL: 8..9 (2)
* PAD_MA: 10..11 (2)
* PAD_MA_VALID: 12 (1)
* PAD_VOL: 13 (1)
* PAD_VOL_VALID: 14 (1)
* PAD_PULL: 15 (1)
* PAD_PULL_VALID: 16 (1)
* RESERVED: 17..31 (15)
*/
typedef u32 iomux_cfg_t;
#define MXS_PAD_BANK_SHIFT 0
#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
#define MXS_PAD_PIN_SHIFT 3
#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
#define MXS_PAD_MUXSEL_SHIFT 8
#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
#define MXS_PAD_MA_SHIFT 10
#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
#define MXS_PAD_MA_VALID_SHIFT 12
#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
#define MXS_PAD_VOL_SHIFT 13
#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
#define MXS_PAD_VOL_VALID_SHIFT 14
#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
#define MXS_PAD_PULL_SHIFT 15
#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
#define MXS_PAD_PULL_VALID_SHIFT 16
#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
#define PAD_MUXSEL_0 0
#define PAD_MUXSEL_1 1
#define PAD_MUXSEL_2 2
#define PAD_MUXSEL_GPIO 3
#define PAD_4MA 0
#define PAD_8MA 1
#define PAD_12MA 2
#define PAD_16MA 3
#define PAD_1V8 0
#define PAD_3V3 1
#define PAD_NOPULL 0
#define PAD_PULLUP 1
#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
MXS_PAD_MA_VALID_MASK)
#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
MXS_PAD_MA_VALID_MASK)
#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
MXS_PAD_MA_VALID_MASK)
#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
MXS_PAD_MA_VALID_MASK)
#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
MXS_PAD_VOL_VALID_MASK)
#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
MXS_PAD_VOL_VALID_MASK)
#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
MXS_PAD_PULL_VALID_MASK)
#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
MXS_PAD_PULL_VALID_MASK)
/* generic pad control used in most cases */
#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
(((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \
((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \
((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \
((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
/*
* A pad becomes naked, when none of mA, vol or pull
* validity bits is set.
*/
#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
static inline unsigned int PAD_BANK(iomux_cfg_t pad)
{
return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
}
static inline unsigned int PAD_PIN(iomux_cfg_t pad)
{
return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
}
static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
{
return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
}
static inline unsigned int PAD_MA(iomux_cfg_t pad)
{
return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
}
static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
{
return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
}
static inline unsigned int PAD_VOL(iomux_cfg_t pad)
{
return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
}
static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
{
return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
}
static inline unsigned int PAD_PULL(iomux_cfg_t pad)
{
return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
}
static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
{
return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
}
/*
* configures a single pad in the iomuxer
*/
int mxs_iomux_setup_pad(iomux_cfg_t pad);
/*
* configures multiple pads
* convenient way to call the above function with tables
*/
int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
#endif /* __MACH_MXS_IOMUX_H__*/

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arch/arm/include/asm/arch-mx28/regs-apbh.h Normal file
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/*
* Freescale i.MX28 APBH Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_apbh_regs {
mx28_reg(hw_apbh_ctrl0)
mx28_reg(hw_apbh_ctrl1)
mx28_reg(hw_apbh_ctrl2)
mx28_reg(hw_apbh_channel_ctrl)
mx28_reg(hw_apbh_devsel)
mx28_reg(hw_apbh_dma_burst_size)
mx28_reg(hw_apbh_debug)
uint32_t reserved[36];
union {
struct {
mx28_reg(hw_apbh_ch_curcmdar)
mx28_reg(hw_apbh_ch_nxtcmdar)
mx28_reg(hw_apbh_ch_cmd)
mx28_reg(hw_apbh_ch_bar)
mx28_reg(hw_apbh_ch_sema)
mx28_reg(hw_apbh_ch_debug1)
mx28_reg(hw_apbh_ch_debug2)
} ch[16];
struct {
mx28_reg(hw_apbh_ch0_curcmdar)
mx28_reg(hw_apbh_ch0_nxtcmdar)
mx28_reg(hw_apbh_ch0_cmd)
mx28_reg(hw_apbh_ch0_bar)
mx28_reg(hw_apbh_ch0_sema)
mx28_reg(hw_apbh_ch0_debug1)
mx28_reg(hw_apbh_ch0_debug2)
mx28_reg(hw_apbh_ch1_curcmdar)
mx28_reg(hw_apbh_ch1_nxtcmdar)
mx28_reg(hw_apbh_ch1_cmd)
mx28_reg(hw_apbh_ch1_bar)
mx28_reg(hw_apbh_ch1_sema)
mx28_reg(hw_apbh_ch1_debug1)
mx28_reg(hw_apbh_ch1_debug2)
mx28_reg(hw_apbh_ch2_curcmdar)
mx28_reg(hw_apbh_ch2_nxtcmdar)
mx28_reg(hw_apbh_ch2_cmd)
mx28_reg(hw_apbh_ch2_bar)
mx28_reg(hw_apbh_ch2_sema)
mx28_reg(hw_apbh_ch2_debug1)
mx28_reg(hw_apbh_ch2_debug2)
mx28_reg(hw_apbh_ch3_curcmdar)
mx28_reg(hw_apbh_ch3_nxtcmdar)
mx28_reg(hw_apbh_ch3_cmd)
mx28_reg(hw_apbh_ch3_bar)
mx28_reg(hw_apbh_ch3_sema)
mx28_reg(hw_apbh_ch3_debug1)
mx28_reg(hw_apbh_ch3_debug2)
mx28_reg(hw_apbh_ch4_curcmdar)
mx28_reg(hw_apbh_ch4_nxtcmdar)
mx28_reg(hw_apbh_ch4_cmd)
mx28_reg(hw_apbh_ch4_bar)
mx28_reg(hw_apbh_ch4_sema)
mx28_reg(hw_apbh_ch4_debug1)
mx28_reg(hw_apbh_ch4_debug2)
mx28_reg(hw_apbh_ch5_curcmdar)
mx28_reg(hw_apbh_ch5_nxtcmdar)
mx28_reg(hw_apbh_ch5_cmd)
mx28_reg(hw_apbh_ch5_bar)
mx28_reg(hw_apbh_ch5_sema)
mx28_reg(hw_apbh_ch5_debug1)
mx28_reg(hw_apbh_ch5_debug2)
mx28_reg(hw_apbh_ch6_curcmdar)
mx28_reg(hw_apbh_ch6_nxtcmdar)
mx28_reg(hw_apbh_ch6_cmd)
mx28_reg(hw_apbh_ch6_bar)
mx28_reg(hw_apbh_ch6_sema)
mx28_reg(hw_apbh_ch6_debug1)
mx28_reg(hw_apbh_ch6_debug2)
mx28_reg(hw_apbh_ch7_curcmdar)
mx28_reg(hw_apbh_ch7_nxtcmdar)
mx28_reg(hw_apbh_ch7_cmd)
mx28_reg(hw_apbh_ch7_bar)
mx28_reg(hw_apbh_ch7_sema)
mx28_reg(hw_apbh_ch7_debug1)
mx28_reg(hw_apbh_ch7_debug2)
mx28_reg(hw_apbh_ch8_curcmdar)
mx28_reg(hw_apbh_ch8_nxtcmdar)
mx28_reg(hw_apbh_ch8_cmd)
mx28_reg(hw_apbh_ch8_bar)
mx28_reg(hw_apbh_ch8_sema)
mx28_reg(hw_apbh_ch8_debug1)
mx28_reg(hw_apbh_ch8_debug2)
mx28_reg(hw_apbh_ch9_curcmdar)
mx28_reg(hw_apbh_ch9_nxtcmdar)
mx28_reg(hw_apbh_ch9_cmd)
mx28_reg(hw_apbh_ch9_bar)
mx28_reg(hw_apbh_ch9_sema)
mx28_reg(hw_apbh_ch9_debug1)
mx28_reg(hw_apbh_ch9_debug2)
mx28_reg(hw_apbh_ch10_curcmdar)
mx28_reg(hw_apbh_ch10_nxtcmdar)
mx28_reg(hw_apbh_ch10_cmd)
mx28_reg(hw_apbh_ch10_bar)
mx28_reg(hw_apbh_ch10_sema)
mx28_reg(hw_apbh_ch10_debug1)
mx28_reg(hw_apbh_ch10_debug2)
mx28_reg(hw_apbh_ch11_curcmdar)
mx28_reg(hw_apbh_ch11_nxtcmdar)
mx28_reg(hw_apbh_ch11_cmd)
mx28_reg(hw_apbh_ch11_bar)
mx28_reg(hw_apbh_ch11_sema)
mx28_reg(hw_apbh_ch11_debug1)
mx28_reg(hw_apbh_ch11_debug2)
mx28_reg(hw_apbh_ch12_curcmdar)
mx28_reg(hw_apbh_ch12_nxtcmdar)
mx28_reg(hw_apbh_ch12_cmd)
mx28_reg(hw_apbh_ch12_bar)
mx28_reg(hw_apbh_ch12_sema)
mx28_reg(hw_apbh_ch12_debug1)
mx28_reg(hw_apbh_ch12_debug2)
mx28_reg(hw_apbh_ch13_curcmdar)
mx28_reg(hw_apbh_ch13_nxtcmdar)
mx28_reg(hw_apbh_ch13_cmd)
mx28_reg(hw_apbh_ch13_bar)
mx28_reg(hw_apbh_ch13_sema)
mx28_reg(hw_apbh_ch13_debug1)
mx28_reg(hw_apbh_ch13_debug2)
mx28_reg(hw_apbh_ch14_curcmdar)
mx28_reg(hw_apbh_ch14_nxtcmdar)
mx28_reg(hw_apbh_ch14_cmd)
mx28_reg(hw_apbh_ch14_bar)
mx28_reg(hw_apbh_ch14_sema)
mx28_reg(hw_apbh_ch14_debug1)
mx28_reg(hw_apbh_ch14_debug2)
mx28_reg(hw_apbh_ch15_curcmdar)
mx28_reg(hw_apbh_ch15_nxtcmdar)
mx28_reg(hw_apbh_ch15_cmd)
mx28_reg(hw_apbh_ch15_bar)
mx28_reg(hw_apbh_ch15_sema)
mx28_reg(hw_apbh_ch15_debug1)
mx28_reg(hw_apbh_ch15_debug2)
};
};
mx28_reg(hw_apbh_version)
};
#endif
#define APBH_CTRL0_SFTRST (1 << 31)
#define APBH_CTRL0_CLKGATE (1 << 30)
#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
#define APBH_CTRL0_APB_BURST_EN (1 << 28)
#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
#define APBH_CTRL0_RSVD0_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
#define APBH_DEVSEL_CH15_OFFSET 30
#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
#define APBH_DEVSEL_CH14_OFFSET 28
#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
#define APBH_DEVSEL_CH13_OFFSET 26
#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
#define APBH_DEVSEL_CH12_OFFSET 24
#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
#define APBH_DEVSEL_CH11_OFFSET 22
#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
#define APBH_DEVSEL_CH10_OFFSET 20
#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
#define APBH_DEVSEL_CH9_OFFSET 18
#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
#define APBH_DEVSEL_CH8_OFFSET 16
#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
#define APBH_DEVSEL_CH7_OFFSET 14
#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
#define APBH_DEVSEL_CH6_OFFSET 12
#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
#define APBH_DEVSEL_CH5_OFFSET 10
#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
#define APBH_DEVSEL_CH4_OFFSET 8
#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
#define APBH_DEVSEL_CH3_OFFSET 6
#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
#define APBH_DEVSEL_CH2_OFFSET 4
#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
#define APBH_DEVSEL_CH1_OFFSET 2
#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
#define APBH_CHn_CMD_NANDLOCK (1 << 4)
#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
#define APBH_CHn_CMD_CHAIN (1 << 2)
#define APBH_CHn_CMD_COMMAND_MASK 0x3
#define APBH_CHn_CMD_COMMAND_OFFSET 0
#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
#define APBH_CHn_BAR_ADDRESS_OFFSET 0
#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
#define APBH_CHn_SEMA_RSVD2_OFFSET 24
#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
#define APBH_CHn_SEMA_PHORE_OFFSET 16
#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
#define APBH_CHn_SEMA_RSVD1_OFFSET 8
#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
#define APBH_CHn_DEBUG1_REQ (1 << 31)
#define APBH_CHn_DEBUG1_BURST (1 << 30)
#define APBH_CHn_DEBUG1_KICK (1 << 29)
#define APBH_CHn_DEBUG1_END (1 << 28)
#define APBH_CHn_DEBUG1_SENSE (1 << 27)
#define APBH_CHn_DEBUG1_READY (1 << 26)
#define APBH_CHn_DEBUG1_LOCK (1 << 25)
#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
#define APBH_VERSION_MAJOR_MASK (0xff << 24)
#define APBH_VERSION_MAJOR_OFFSET 24
#define APBH_VERSION_MINOR_MASK (0xff << 16)
#define APBH_VERSION_MINOR_OFFSET 16
#define APBH_VERSION_STEP_MASK 0xffff
#define APBH_VERSION_STEP_OFFSET 0
#endif /* __REGS_APBH_H__ */

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/*
* Freescale i.MX28 Peripheral Base Addresses
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright (C) 2008 Embedded Alley Solutions Inc.
*
* (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_BASE_H__
#define __MX28_REGS_BASE_H__
/*
* Register base address
*/
#define MXS_ICOL_BASE 0x80000000
#define MXS_HSADC_BASE 0x80002000
#define MXS_APBH_BASE 0x80004000
#define MXS_PERFMON_BASE 0x80006000
#define MXS_BCH_BASE 0x8000A000
#define MXS_GPMI_BASE 0x8000C000
#define MXS_SSP0_BASE 0x80010000
#define MXS_SSP1_BASE 0x80012000
#define MXS_SSP2_BASE 0x80014000
#define MXS_SSP3_BASE 0x80016000
#define MXS_PINCTRL_BASE 0x80018000
#define MXS_DIGCTL_BASE 0x8001C000
#define MXS_ETM_BASE 0x80022000
#define MXS_APBX_BASE 0x80024000
#define MXS_DCP_BASE 0x80028000
#define MXS_PXP_BASE 0x8002A000
#define MXS_OCOTP_BASE 0x8002C000
#define MXS_AXI_AHB0_BASE 0x8002E000
#define MXS_LCDIF_BASE 0x80030000
#define MXS_CAN0_BASE 0x80032000
#define MXS_CAN1_BASE 0x80034000
#define MXS_SIMDBG_BASE 0x8003C000
#define MXS_SIMGPMISEL_BASE 0x8003C200
#define MXS_SIMSSPSEL_BASE 0x8003C300
#define MXS_SIMMEMSEL_BASE 0x8003C400
#define MXS_GPIOMON_BASE 0x8003C500
#define MXS_SIMENET_BASE 0x8003C700
#define MXS_ARMJTAG_BASE 0x8003C800
#define MXS_CLKCTRL_BASE 0x80040000
#define MXS_SAIF0_BASE 0x80042000
#define MXS_POWER_BASE 0x80044000
#define MXS_SAIF1_BASE 0x80046000
#define MXS_LRADC_BASE 0x80050000
#define MXS_SPDIF_BASE 0x80054000
#define MXS_RTC_BASE 0x80056000
#define MXS_I2C0_BASE 0x80058000
#define MXS_I2C1_BASE 0x8005A000
#define MXS_PWM_BASE 0x80064000
#define MXS_TIMROT_BASE 0x80068000
#define MXS_UARTAPP0_BASE 0x8006A000
#define MXS_UARTAPP1_BASE 0x8006C000
#define MXS_UARTAPP2_BASE 0x8006E000
#define MXS_UARTAPP3_BASE 0x80070000
#define MXS_UARTAPP4_BASE 0x80072000
#define MXS_UARTDBG_BASE 0x80074000
#define MXS_USBPHY0_BASE 0x8007C000
#define MXS_USBPHY1_BASE 0x8007E000
#define MXS_USBCTRL0_BASE 0x80080000
#define MXS_USBCTRL1_BASE 0x80090000
#define MXS_DFLPT_BASE 0x800C0000
#define MXS_DRAM_BASE 0x800E0000
#define MXS_ENET0_BASE 0x800F0000
#define MXS_ENET1_BASE 0x800F4000
#endif /* __MX28_REGS_BASE_H__ */

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/*
* Freescale i.MX28 BCH Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_BCH_H__
#define __MX28_REGS_BCH_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_bch_regs {
mx28_reg(hw_bch_ctrl)
mx28_reg(hw_bch_status0)
mx28_reg(hw_bch_mode)
mx28_reg(hw_bch_encodeptr)
mx28_reg(hw_bch_dataptr)
mx28_reg(hw_bch_metaptr)
uint32_t reserved[4];
mx28_reg(hw_bch_layoutselect)
mx28_reg(hw_bch_flash0layout0)
mx28_reg(hw_bch_flash0layout1)
mx28_reg(hw_bch_flash1layout0)
mx28_reg(hw_bch_flash1layout1)
mx28_reg(hw_bch_flash2layout0)
mx28_reg(hw_bch_flash2layout1)
mx28_reg(hw_bch_flash3layout0)
mx28_reg(hw_bch_flash3layout1)
mx28_reg(hw_bch_dbgkesread)
mx28_reg(hw_bch_dbgcsferead)
mx28_reg(hw_bch_dbgsyndegread)
mx28_reg(hw_bch_dbgahbmread)
mx28_reg(hw_bch_blockname)
mx28_reg(hw_bch_version)
};
#endif
#define BCH_CTRL_SFTRST (1 << 31)
#define BCH_CTRL_CLKGATE (1 << 30)
#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
#define BCH_CTRL_M2M_ENCODE (1 << 17)
#define BCH_CTRL_M2M_ENABLE (1 << 16)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
#define BCH_STATUS0_HANDLE_OFFSET 20
#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
#define BCH_STATUS0_ALLONES (1 << 4)
#define BCH_STATUS0_CORRECTED (1 << 3)
#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
#define BCH_ENCODEPTR_ADDR_OFFSET 0
#define BCH_DATAPTR_ADDR_MASK 0xffffffff
#define BCH_DATAPTR_ADDR_OFFSET 0
#define BCH_METAPTR_ADDR_MASK 0xffffffff
#define BCH_METAPTR_ADDR_OFFSET 0
#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
#define BCH_DEBUG0_RSVD1_OFFSET 27
#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
#define BCH_DEBUG0_RSVD0_OFFSET 6
#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
#define BCH_DBGKESREAD_VALUES_OFFSET 0
#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
#define BCH_BLOCKNAME_NAME_OFFSET 0
#define BCH_VERSION_MAJOR_MASK (0xff << 24)
#define BCH_VERSION_MAJOR_OFFSET 24
#define BCH_VERSION_MINOR_MASK (0xff << 16)
#define BCH_VERSION_MINOR_OFFSET 16
#define BCH_VERSION_STEP_MASK 0xffff
#define BCH_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_BCH_H__ */

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/*
* Freescale i.MX28 CLKCTRL Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_CLKCTRL_H__
#define __MX28_REGS_CLKCTRL_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_clkctrl_regs {
mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */
mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */
mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */
mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */
mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */
mx28_reg(hw_clkctrl_cpu) /* 0x50 */
mx28_reg(hw_clkctrl_hbus) /* 0x60 */
mx28_reg(hw_clkctrl_xbus) /* 0x70 */
mx28_reg(hw_clkctrl_xtal) /* 0x80 */
mx28_reg(hw_clkctrl_ssp0) /* 0x90 */
mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */
mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */
mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */
mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */
mx28_reg(hw_clkctrl_spdif) /* 0xe0 */
mx28_reg(hw_clkctrl_emi) /* 0xf0 */
mx28_reg(hw_clkctrl_saif0) /* 0x100 */
mx28_reg(hw_clkctrl_saif1) /* 0x110 */
mx28_reg(hw_clkctrl_lcdif) /* 0x120 */
mx28_reg(hw_clkctrl_etm) /* 0x130 */
mx28_reg(hw_clkctrl_enet) /* 0x140 */
mx28_reg(hw_clkctrl_hsadc) /* 0x150 */
mx28_reg(hw_clkctrl_flexcan) /* 0x160 */
uint32_t reserved[16];
mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */
mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */
mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */
mx28_reg(hw_clkctrl_reset) /* 0x1e0 */
mx28_reg(hw_clkctrl_status) /* 0x1f0 */
mx28_reg(hw_clkctrl_version) /* 0x200 */
};
#endif
#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
#define CLKCTRL_PLL0CTRL0_POWER (1 << 17)
#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31)
#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24)
#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24
#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24)
#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20)
#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20
#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20)
#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20)
#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18)
#define CLKCTRL_PLL1CTRL0_POWER (1 << 17)
#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31)
#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30)
#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff
#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0
#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31)
#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26)
#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24)
#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24
#define CLKCTRL_PLL2CTRL0_POWER (1 << 23)
#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
#define CLKCTRL_HBUS_ASM_BUSY (1 << 31)
#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30)
#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29)
#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27)
#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20)
#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19)
#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
#define CLKCTRL_HBUS_DIV_MASK 0x1f
#define CLKCTRL_HBUS_DIV_OFFSET 0
#define CLKCTRL_XBUS_BUSY (1 << 31)
#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11)
#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_XBUS_DIV_MASK 0x3ff
#define CLKCTRL_XBUS_DIV_OFFSET 0
#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
#define CLKCTRL_SSP_CLKGATE (1 << 31)
#define CLKCTRL_SSP_BUSY (1 << 29)
#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
#define CLKCTRL_SSP_DIV_MASK 0x1ff
#define CLKCTRL_SSP_DIV_OFFSET 0
#define CLKCTRL_GPMI_CLKGATE (1 << 31)
#define CLKCTRL_GPMI_BUSY (1 << 29)
#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_GPMI_DIV_MASK 0x3ff
#define CLKCTRL_GPMI_DIV_OFFSET 0
#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
#define CLKCTRL_EMI_CLKGATE (1 << 31)
#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
#define CLKCTRL_SAIF0_BUSY (1 << 29)
#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
#define CLKCTRL_SAIF0_DIV_MASK 0xffff
#define CLKCTRL_SAIF0_DIV_OFFSET 0
#define CLKCTRL_SAIF1_CLKGATE (1 << 31)
#define CLKCTRL_SAIF1_BUSY (1 << 29)
#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16)
#define CLKCTRL_SAIF1_DIV_MASK 0xffff
#define CLKCTRL_SAIF1_DIV_OFFSET 0
#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31)
#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29)
#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13)
#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff
#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0
#define CLKCTRL_ETM_CLKGATE (1 << 31)
#define CLKCTRL_ETM_BUSY (1 << 29)
#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7)
#define CLKCTRL_ETM_DIV_MASK 0x7f
#define CLKCTRL_ETM_DIV_OFFSET 0
#define CLKCTRL_ENET_SLEEP (1 << 31)
#define CLKCTRL_ENET_DISABLE (1 << 30)
#define CLKCTRL_ENET_STATUS (1 << 29)
#define CLKCTRL_ENET_BUSY_TIME (1 << 27)
#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21)
#define CLKCTRL_ENET_DIV_TIME_OFFSET 21
#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19)
#define CLKCTRL_ENET_TIME_SEL_OFFSET 19
#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19)
#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19)
#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19)
#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19)
#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18)
#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17)
#define CLKCTRL_ENET_RESET_BY_SW (1 << 16)
#define CLKCTRL_HSADC_RESETB (1 << 30)
#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
#define CLKCTRL_HSADC_FREQDIV_OFFSET 28
#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30)
#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29)
#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)
#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27)
#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31)
#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30)
#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24)
#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24
#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23)
#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22)
#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16)
#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16
#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15)
#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14)
#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8)
#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8
#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7)
#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6)
#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f
#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0
#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23)
#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22)
#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16)
#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16
#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15)
#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14)
#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8)
#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8
#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7)
#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6)
#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f
#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18)
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14)
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14)
#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14)
#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7)
#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6)
#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5)
#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4)
#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3)
#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2)
#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1)
#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0)
#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5)
#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4)
#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3)
#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2)
#define CLKCTRL_RESET_CHIP (1 << 1)
#define CLKCTRL_RESET_DIG (1 << 0)
#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
#define CLKCTRL_VERSION_MAJOR_OFFSET 24
#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
#define CLKCTRL_VERSION_MINOR_OFFSET 16
#define CLKCTRL_VERSION_STEP_MASK 0xffff
#define CLKCTRL_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_CLKCTRL_H__ */

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/*
* Freescale i.MX28 Register Accessors
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_COMMON_H__
#define __MX28_REGS_COMMON_H__
/*
* The i.MX28 has interesting feature when it comes to register access. There
* are four kinds of access to one particular register. Those are:
*
* 1) Common read/write access. To use this mode, just write to the address of
* the register.
* 2) Set bits only access. To set bits, write which bits you want to set to the
* address of the register + 0x4.
* 3) Clear bits only access. To clear bits, write which bits you want to clear
* to the address of the register + 0x8.
* 4) Toggle bits only access. To toggle bits, write which bits you want to
* toggle to the address of the register + 0xc.
*
* IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
* can be set/cleared by pure write as in access type 1, some need to be
* explicitly set/cleared by using access type 2-3.
*
* The following macros and structures allow the user to either access the
* register in all aforementioned modes (by accessing reg_name, reg_name_set,
* reg_name_clr, reg_name_tog) or pass the register structure further into
* various functions with correct type information (by accessing reg_name_reg).
*
*/
#define __mx28_reg(name) \
uint32_t name; \
uint32_t name##_set; \
uint32_t name##_clr; \
uint32_t name##_tog;
struct mx28_register {
__mx28_reg(reg)
};
#define mx28_reg(name) \
union { \
struct { __mx28_reg(name) }; \
struct mx28_register name##_reg; \
};
#endif /* __MX28_REGS_COMMON_H__ */

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/*
* Freescale i.MX28 GPMI Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_GPMI_H__
#define __MX28_REGS_GPMI_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_gpmi_regs {
mx28_reg(hw_gpmi_ctrl0)
mx28_reg(hw_gpmi_compare)
mx28_reg(hw_gpmi_eccctrl)
mx28_reg(hw_gpmi_ecccount)
mx28_reg(hw_gpmi_payload)
mx28_reg(hw_gpmi_auxiliary)
mx28_reg(hw_gpmi_ctrl1)
mx28_reg(hw_gpmi_timing0)
mx28_reg(hw_gpmi_timing1)
uint32_t reserved[4];
mx28_reg(hw_gpmi_data)
mx28_reg(hw_gpmi_stat)
mx28_reg(hw_gpmi_debug)
mx28_reg(hw_gpmi_version)
};
#endif
#define GPMI_CTRL0_SFTRST (1 << 31)
#define GPMI_CTRL0_CLKGATE (1 << 30)
#define GPMI_CTRL0_RUN (1 << 29)
#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
#define GPMI_CTRL0_LOCK_CS (1 << 27)
#define GPMI_CTRL0_UDMA (1 << 26)
#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
#define GPMI_CTRL0_CS_MASK (0x7 << 20)
#define GPMI_CTRL0_CS_OFFSET 20
#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
#define GPMI_CTRL0_ADDRESS_OFFSET 17
#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
#define GPMI_COMPARE_MASK_OFFSET 16
#define GPMI_COMPARE_REFERENCE_MASK 0xffff
#define GPMI_COMPARE_REFERENCE_OFFSET 0
#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
#define GPMI_ECCCTRL_HANDLE_OFFSET 16
#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
#define GPMI_ECCCOUNT_COUNT_OFFSET 0
#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
#define GPMI_CTRL1_BCH_MODE (1 << 18)
#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
#define GPMI_CTRL1_DEV_IRQ (1 << 10)
#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
#define GPMI_CTRL1_BURST_EN (1 << 8)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
#define GPMI_CTRL1_DEV_RESET (1 << 3)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
#define GPMI_CTRL1_GPMI_MODE (1 << 0)
#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
#define GPMI_DATA_DATA_MASK 0xffffffff
#define GPMI_DATA_DATA_OFFSET 0
#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
#define GPMI_STAT_READY_BUSY_OFFSET 24
#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
#define GPMI_STAT_DEV7_ERROR (1 << 15)
#define GPMI_STAT_DEV6_ERROR (1 << 14)
#define GPMI_STAT_DEV5_ERROR (1 << 13)
#define GPMI_STAT_DEV4_ERROR (1 << 12)
#define GPMI_STAT_DEV3_ERROR (1 << 11)
#define GPMI_STAT_DEV2_ERROR (1 << 10)
#define GPMI_STAT_DEV1_ERROR (1 << 9)
#define GPMI_STAT_DEV0_ERROR (1 << 8)
#define GPMI_STAT_ATA_IRQ (1 << 4)
#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
#define GPMI_STAT_FIFO_EMPTY (1 << 2)
#define GPMI_STAT_FIFO_FULL (1 << 1)
#define GPMI_STAT_PRESENT (1 << 0)
#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
#define GPMI_DEBUG_DMAREQ_OFFSET 8
#define GPMI_DEBUG_CMD_END_MASK 0xff
#define GPMI_DEBUG_CMD_END_OFFSET 0
#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
#define GPMI_VERSION_MAJOR_OFFSET 24
#define GPMI_VERSION_MINOR_MASK (0xff << 16)
#define GPMI_VERSION_MINOR_OFFSET 16
#define GPMI_VERSION_STEP_MASK 0xffff
#define GPMI_VERSION_STEP_OFFSET 0
#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
#define GPMI_DEBUG2_BUSY (1 << 23)
#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
#endif /* __MX28_REGS_GPMI_H__ */

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/*
* Freescale i.MX28 I2C Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_I2C_H__
#define __MX28_REGS_I2C_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_i2c_regs {
mx28_reg(hw_i2c_ctrl0)
mx28_reg(hw_i2c_timing0)
mx28_reg(hw_i2c_timing1)
mx28_reg(hw_i2c_timing2)
mx28_reg(hw_i2c_ctrl1)
mx28_reg(hw_i2c_stat)
mx28_reg(hw_i2c_queuectrl)
mx28_reg(hw_i2c_queuestat)
mx28_reg(hw_i2c_queuecmd)
mx28_reg(hw_i2c_queuedata)
mx28_reg(hw_i2c_data)
mx28_reg(hw_i2c_debug0)
mx28_reg(hw_i2c_debug1)
mx28_reg(hw_i2c_version)
};
#endif
#define I2C_CTRL_SFTRST (1 << 31)
#define I2C_CTRL_CLKGATE (1 << 30)
#define I2C_CTRL_RUN (1 << 29)
#define I2C_CTRL_PREACK (1 << 27)
#define I2C_CTRL_ACKNOWLEDGE (1 << 26)
#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25)
#define I2C_CTRL_MULTI_MASTER (1 << 23)
#define I2C_CTRL_CLOCK_HELD (1 << 22)
#define I2C_CTRL_RETAIN_CLOCK (1 << 21)
#define I2C_CTRL_POST_SEND_STOP (1 << 20)
#define I2C_CTRL_PRE_SEND_START (1 << 19)
#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18)
#define I2C_CTRL_MASTER_MODE (1 << 17)
#define I2C_CTRL_DIRECTION (1 << 16)
#define I2C_CTRL_XFER_COUNT_MASK 0xffff
#define I2C_CTRL_XFER_COUNT_OFFSET 0
#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16)
#define I2C_TIMING0_HIGH_COUNT_OFFSET 16
#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff
#define I2C_TIMING0_RCV_COUNT_OFFSET 0
#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16)
#define I2C_TIMING1_LOW_COUNT_OFFSET 16
#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff
#define I2C_TIMING1_XMIT_COUNT_OFFSET 0
#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16)
#define I2C_TIMING2_BUS_FREE_OFFSET 16
#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff
#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0
#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30)
#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29)
#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28)
#define I2C_CTRL1_ACK_MODE (1 << 27)
#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26)
#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25)
#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24)
#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16)
#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16
#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15)
#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14)
#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13)
#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11)
#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10)
#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9)
#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8)
#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7)
#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6)
#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5)
#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4)
#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3)
#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2)
#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1)
#define I2C_CTRL1_SLAVE_IRQ (1 << 0)
#define I2C_STAT_MASTER_PRESENT (1 << 31)
#define I2C_STAT_SLAVE_PRESENT (1 << 30)
#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29)
#define I2C_STAT_GOT_A_NAK (1 << 28)
#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16)
#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16
#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15)
#define I2C_STAT_SLAVE_FOUND (1 << 14)
#define I2C_STAT_SLAVE_SEARCHING (1 << 13)
#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12)
#define I2C_STAT_BUS_BUSY (1 << 11)
#define I2C_STAT_CLK_GEN_BUSY (1 << 10)
#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9)
#define I2C_STAT_SLAVE_BUSY (1 << 8)
#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7)
#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6)
#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5)
#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4)
#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3)
#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2)
#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1)
#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0)
#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16)
#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16
#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8)
#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8
#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5)
#define I2C_QUEUECTRL_RD_CLEAR (1 << 4)
#define I2C_QUEUECTRL_WR_CLEAR (1 << 3)
#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2)
#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1)
#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0)
#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14)
#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13)
#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8)
#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8
#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6)
#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5)
#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f
#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0
#define I2C_QUEUECMD_PREACK (1 << 27)
#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26)
#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25)
#define I2C_QUEUECMD_MULTI_MASTER (1 << 23)
#define I2C_QUEUECMD_CLOCK_HELD (1 << 22)
#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21)
#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20)
#define I2C_QUEUECMD_PRE_SEND_START (1 << 19)
#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18)
#define I2C_QUEUECMD_MASTER_MODE (1 << 17)
#define I2C_QUEUECMD_DIRECTION (1 << 16)
#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff
#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0
#define I2C_QUEUEDATA_DATA_MASK 0xffffffff
#define I2C_QUEUEDATA_DATA_OFFSET 0
#define I2C_DATA_DATA_MASK 0xffffffff
#define I2C_DATA_DATA_OFFSET 0
#define I2C_DEBUG0_DMAREQ (1 << 31)
#define I2C_DEBUG0_DMAENDCMD (1 << 30)
#define I2C_DEBUG0_DMAKICK (1 << 29)
#define I2C_DEBUG0_DMATERMINATE (1 << 28)
#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26)
#define I2C_DEBUG0_STATE_VALUE_OFFSET 26
#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16)
#define I2C_DEBUG0_DMA_STATE_OFFSET 16
#define I2C_DEBUG0_START_TOGGLE (1 << 15)
#define I2C_DEBUG0_STOP_TOGGLE (1 << 14)
#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13)
#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12)
#define I2C_DEBUG0_STATE_LATCH (1 << 11)
#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10)
#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff
#define I2C_DEBUG0_STATE_STATE_OFFSET 0
#define I2C_DEBUG1_I2C_CLK_IN (1 << 31)
#define I2C_DEBUG1_I2C_DATA_IN (1 << 30)
#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24)
#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24
#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16)
#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16
#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9)
#define I2C_DEBUG1_LST_MODE_OFFSET 9
#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8)
#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4)
#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3)
#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2)
#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1)
#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0)
#define I2C_VERSION_MAJOR_MASK (0xff << 24)
#define I2C_VERSION_MAJOR_OFFSET 24
#define I2C_VERSION_MINOR_MASK (0xff << 16)
#define I2C_VERSION_MINOR_OFFSET 16
#define I2C_VERSION_STEP_MASK 0xffff
#define I2C_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_I2C_H__ */

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/*
* Freescale i.MX28 OCOTP Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_OCOTP_H__
#define __MX28_REGS_OCOTP_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_ocotp_regs {
mx28_reg(hw_ocotp_ctrl) /* 0x0 */
mx28_reg(hw_ocotp_data) /* 0x10 */
mx28_reg(hw_ocotp_cust0) /* 0x20 */
mx28_reg(hw_ocotp_cust1) /* 0x30 */
mx28_reg(hw_ocotp_cust2) /* 0x40 */
mx28_reg(hw_ocotp_cust3) /* 0x50 */
mx28_reg(hw_ocotp_crypto0) /* 0x60 */
mx28_reg(hw_ocotp_crypto1) /* 0x70 */
mx28_reg(hw_ocotp_crypto2) /* 0x80 */
mx28_reg(hw_ocotp_crypto3) /* 0x90 */
mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */
mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */
mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */
mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */
mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */
mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */
mx28_reg(hw_ocotp_swcap) /* 0x100 */
mx28_reg(hw_ocotp_custcap) /* 0x110 */
mx28_reg(hw_ocotp_lock) /* 0x120 */
mx28_reg(hw_ocotp_ops0) /* 0x130 */
mx28_reg(hw_ocotp_ops1) /* 0x140 */
mx28_reg(hw_ocotp_ops2) /* 0x150 */
mx28_reg(hw_ocotp_ops3) /* 0x160 */
mx28_reg(hw_ocotp_un0) /* 0x170 */
mx28_reg(hw_ocotp_un1) /* 0x180 */
mx28_reg(hw_ocotp_un2) /* 0x190 */
mx28_reg(hw_ocotp_rom0) /* 0x1a0 */
mx28_reg(hw_ocotp_rom1) /* 0x1b0 */
mx28_reg(hw_ocotp_rom2) /* 0x1c0 */
mx28_reg(hw_ocotp_rom3) /* 0x1d0 */
mx28_reg(hw_ocotp_rom4) /* 0x1e0 */
mx28_reg(hw_ocotp_rom5) /* 0x1f0 */
mx28_reg(hw_ocotp_rom6) /* 0x200 */
mx28_reg(hw_ocotp_rom7) /* 0x210 */
mx28_reg(hw_ocotp_srk0) /* 0x220 */
mx28_reg(hw_ocotp_srk1) /* 0x230 */
mx28_reg(hw_ocotp_srk2) /* 0x240 */
mx28_reg(hw_ocotp_srk3) /* 0x250 */
mx28_reg(hw_ocotp_srk4) /* 0x260 */
mx28_reg(hw_ocotp_srk5) /* 0x270 */
mx28_reg(hw_ocotp_srk6) /* 0x280 */
mx28_reg(hw_ocotp_srk7) /* 0x290 */
mx28_reg(hw_ocotp_version) /* 0x2a0 */
};
#endif
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16)
#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16
#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16)
#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13)
#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
#define OCOTP_CTRL_ERROR (1 << 9)
#define OCOTP_CTRL_BUSY (1 << 8)
#define OCOTP_CTRL_ADDR_MASK 0x3f
#define OCOTP_CTRL_ADDR_OFFSET 0
#define OCOTP_DATA_DATA_MASK 0xffffffff
#define OCOTP_DATA_DATA_OFFSET 0
#define OCOTP_CUST_BITS_MASK 0xffffffff
#define OCOTP_CUST_BITS_OFFSET 0
#define OCOTP_CRYPTO_BITS_MASK 0xffffffff
#define OCOTP_CRYPTO_BITS_OFFSET 0
#define OCOTP_HWCAP_BITS_MASK 0xffffffff
#define OCOTP_HWCAP_BITS_OFFSET 0
#define OCOTP_SWCAP_BITS_MASK 0xffffffff
#define OCOTP_SWCAP_BITS_OFFSET 0
#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2)
#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1)
#define OCOTP_LOCK_ROM7 (1 << 31)
#define OCOTP_LOCK_ROM6 (1 << 30)
#define OCOTP_LOCK_ROM5 (1 << 29)
#define OCOTP_LOCK_ROM4 (1 << 28)
#define OCOTP_LOCK_ROM3 (1 << 27)
#define OCOTP_LOCK_ROM2 (1 << 26)
#define OCOTP_LOCK_ROM1 (1 << 25)
#define OCOTP_LOCK_ROM0 (1 << 24)
#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23)
#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22)
#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21)
#define OCOTP_LOCK_PIN (1 << 20)
#define OCOTP_LOCK_OPS (1 << 19)
#define OCOTP_LOCK_UN2 (1 << 18)
#define OCOTP_LOCK_UN1 (1 << 17)
#define OCOTP_LOCK_UN0 (1 << 16)
#define OCOTP_LOCK_SRK (1 << 15)
#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12)
#define OCOTP_LOCK_UNALLOCATED_OFFSET 12
#define OCOTP_LOCK_SRK_SHADOW (1 << 11)
#define OCOTP_LOCK_ROM_SHADOW (1 << 10)
#define OCOTP_LOCK_CUSTCAP (1 << 9)
#define OCOTP_LOCK_HWSW (1 << 8)
#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7)
#define OCOTP_LOCK_HWSW_SHADOW (1 << 6)
#define OCOTP_LOCK_CRYPTODCP (1 << 5)
#define OCOTP_LOCK_CRYPTOKEY (1 << 4)
#define OCOTP_LOCK_CUST3 (1 << 3)
#define OCOTP_LOCK_CUST2 (1 << 2)
#define OCOTP_LOCK_CUST1 (1 << 1)
#define OCOTP_LOCK_CUST0 (1 << 0)
#define OCOTP_OPS_BITS_MASK 0xffffffff
#define OCOTP_OPS_BITS_OFFSET 0
#define OCOTP_UN_BITS_MASK 0xffffffff
#define OCOTP_UN_BITS_OFFSET 0
#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24)
#define OCOTP_ROM_BOOT_MODE_OFFSET 24
#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22)
#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22
#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20)
#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20
#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14)
#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14
#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12)
#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12
#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8)
#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8
#define OCOTP_ROM_EMMC_USE_DDR (1 << 7)
#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6)
#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5)
#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4)
#define OCOTP_ROM_SD_MBR_BOOT (1 << 3)
#define OCOTP_SRK_BITS_MASK 0xffffffff
#define OCOTP_SRK_BITS_OFFSET 0
#define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
#define OCOTP_VERSION_MAJOR_OFFSET 24
#define OCOTP_VERSION_MINOR_MASK (0xff << 16)
#define OCOTP_VERSION_MINOR_OFFSET 16
#define OCOTP_VERSION_STEP_MASK 0xffff
#define OCOTP_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_OCOTP_H__ */

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/*
* Freescale i.MX28 Power Controller Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_POWER_H__
#define __MX28_REGS_POWER_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_power_regs {
mx28_reg(hw_power_ctrl)
mx28_reg(hw_power_5vctrl)
mx28_reg(hw_power_minpwr)
mx28_reg(hw_power_charge)
uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl;
uint32_t reserved_vdda[3];
uint32_t hw_power_vddioctrl;
uint32_t reserved_vddio[3];
uint32_t hw_power_vddmemctrl;
uint32_t reserved_vddmem[3];
uint32_t hw_power_dcdc4p2;
uint32_t reserved_dcdc4p2[3];
uint32_t hw_power_misc;
uint32_t reserved_misc[3];
uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3];
mx28_reg(hw_power_loopctrl)
uint32_t hw_power_sts;
uint32_t reserved_sts[3];
mx28_reg(hw_power_speed)
uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3];
uint32_t reserved[4];
mx28_reg(hw_power_reset)
mx28_reg(hw_power_debug)
mx28_reg(hw_power_thermal)
mx28_reg(hw_power_usb1ctrl)
mx28_reg(hw_power_special)
mx28_reg(hw_power_version)
mx28_reg(hw_power_anaclkctrl)
mx28_reg(hw_power_refctrl)
};
#endif
#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
#define POWER_CTRL_DC_OK_IRQ (1 << 15)
#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
#define POWER_5VCTRL_DCDC_XFER (1 << 5)
#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
#define POWER_MINPWR_PWD_BO (1 << 12)
#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
#define POWER_MINPWR_ENABLE_OSC (1 << 9)
#define POWER_MINPWR_SELECT_OSC (1 << 8)
#define POWER_MINPWR_FBG_OFF (1 << 7)
#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
#define POWER_MINPWR_HALFFETS (1 << 5)
#define POWER_MINPWR_LESSANA_I (1 << 4)
#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
#define POWER_MINPWR_DC_STOPCLK (1 << 2)
#define POWER_MINPWR_EN_DC_PFM (1 << 1)
#define POWER_MINPWR_DC_HALFCLK (1 << 0)
#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
#define POWER_CHARGE_LIION_4P1 (1 << 18)
#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
#define POWER_VDDDCTRL_ADJTN_OFFSET 28
#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDDCTRL_TRG_MASK 0x1f
#define POWER_VDDDCTRL_TRG_OFFSET 0
#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDACTRL_TRG_MASK 0x1f
#define POWER_VDDACTRL_TRG_OFFSET 0
#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDIOCTRL_TRG_MASK 0x1f
#define POWER_VDDIOCTRL_TRG_OFFSET 0
#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
#define POWER_VDDMEMCTRL_TRG_OFFSET 0
#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
#define POWER_DCDC4P2_HYST_DIR (1 << 21)
#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
#define POWER_DCDC4P2_TRG_OFFSET 16
#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
#define POWER_DCDC4P2_BO_OFFSET 8
#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
#define POWER_MISC_FREQSEL_OFFSET 4
#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
#define POWER_MISC_DELAY_TIMING (1 << 2)
#define POWER_MISC_TEST (1 << 1)
#define POWER_MISC_SEL_PLLCLK (1 << 0)
#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
#define POWER_DCLIMITS_NETLIMIT_OFFSET 0
#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
#define POWER_LOOPCTRL_DC_FF_OFFSET 8
#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
#define POWER_LOOPCTRL_DC_R_OFFSET 4
#define POWER_LOOPCTRL_DC_C_MASK 0x3
#define POWER_LOOPCTRL_DC_C_OFFSET 0
#define POWER_LOOPCTRL_DC_C_MAX 0x0
#define POWER_LOOPCTRL_DC_C_2X 0x1
#define POWER_LOOPCTRL_DC_C_4X 0x2
#define POWER_LOOPCTRL_DC_C_MIN 0x3
#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
#define POWER_STS_PWRUP_SOURCE_OFFSET 24
#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
#define POWER_STS_PSWITCH_MASK (0x3 << 20)
#define POWER_STS_PSWITCH_OFFSET 20
#define POWER_STS_THERMAL_WARNING (1 << 19)
#define POWER_STS_VDDMEM_BO (1 << 18)
#define POWER_STS_AVALID0_STATUS (1 << 17)
#define POWER_STS_BVALID0_STATUS (1 << 16)
#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
#define POWER_STS_SESSEND0_STATUS (1 << 14)
#define POWER_STS_BATT_BO (1 << 13)
#define POWER_STS_VDD5V_FAULT (1 << 12)
#define POWER_STS_CHRGSTS (1 << 11)
#define POWER_STS_DCDC_4P2_BO (1 << 10)
#define POWER_STS_DC_OK (1 << 9)
#define POWER_STS_VDDIO_BO (1 << 8)
#define POWER_STS_VDDA_BO (1 << 7)
#define POWER_STS_VDDD_BO (1 << 6)
#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
#define POWER_STS_VDD5V_DROOP (1 << 4)
#define POWER_STS_AVALID0 (1 << 3)
#define POWER_STS_BVALID0 (1 << 2)
#define POWER_STS_VBUSVALID0 (1 << 1)
#define POWER_STS_SESSEND0 (1 << 0)
#define POWER_SPEED_STATUS_MASK (0xffff << 8)
#define POWER_SPEED_STATUS_OFFSET 8
#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
#define POWER_SPEED_STATUS_SEL_OFFSET 6
#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
#define POWER_SPEED_CTRL_MASK 0x3
#define POWER_SPEED_CTRL_OFFSET 0
#define POWER_SPEED_CTRL_SS_OFF 0x0
#define POWER_SPEED_CTRL_SS_ON 0x1
#define POWER_SPEED_CTRL_SS_ENABLE 0x3
#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
#define POWER_RESET_UNLOCK_OFFSET 16
#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
#define POWER_RESET_PWD_OFF (1 << 1)
#define POWER_RESET_PWD (1 << 0)
#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
#define POWER_THERMAL_TEST (1 << 8)
#define POWER_THERMAL_PWD (1 << 7)
#define POWER_THERMAL_LOW_POWER (1 << 6)
#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
#define POWER_USB1CTRL_AVALID1 (1 << 3)
#define POWER_USB1CTRL_BVALID1 (1 << 2)
#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
#define POWER_USB1CTRL_SESSEND1 (1 << 0)
#define POWER_SPECIAL_TEST_MASK 0xffffffff
#define POWER_SPECIAL_TEST_OFFSET 0
#define POWER_VERSION_MAJOR_MASK (0xff << 24)
#define POWER_VERSION_MAJOR_OFFSET 24
#define POWER_VERSION_MINOR_MASK (0xff << 16)
#define POWER_VERSION_MINOR_OFFSET 16
#define POWER_VERSION_STEP_MASK 0xffff
#define POWER_VERSION_STEP_OFFSET 0
#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
#define POWER_ANACLKCTRL_INDIV_MASK 0x7
#define POWER_ANACLKCTRL_INDIV_OFFSET 0
#define POWER_REFCTRL_FASTSETTLING (1 << 26)
#define POWER_REFCTRL_RAISE_REF (1 << 25)
#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
#define POWER_REFCTRL_LOW_PWR (1 << 19)
#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
#define POWER_REFCTRL_ADJ_ANA (1 << 13)
#define POWER_REFCTRL_ADJ_VAG (1 << 12)
#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
#define POWER_REFCTRL_VAG_VAL_OFFSET 4
#endif /* __MX28_REGS_POWER_H__ */

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/*
* Freescale i.MX28 RTC Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_RTC_H__
#define __MX28_REGS_RTC_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_rtc_regs {
mx28_reg(hw_rtc_ctrl)
mx28_reg(hw_rtc_stat)
mx28_reg(hw_rtc_milliseconds)
mx28_reg(hw_rtc_seconds)
mx28_reg(hw_rtc_rtc_alarm)
mx28_reg(hw_rtc_watchdog)
mx28_reg(hw_rtc_persistent0)
mx28_reg(hw_rtc_persistent1)
mx28_reg(hw_rtc_persistent2)
mx28_reg(hw_rtc_persistent3)
mx28_reg(hw_rtc_persistent4)
mx28_reg(hw_rtc_persistent5)
mx28_reg(hw_rtc_debug)
mx28_reg(hw_rtc_version)
};
#endif
#define RTC_CTRL_SFTRST (1 << 31)
#define RTC_CTRL_CLKGATE (1 << 30)
#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6)
#define RTC_CTRL_FORCE_UPDATE (1 << 5)
#define RTC_CTRL_WATCHDOGEN (1 << 4)
#define RTC_CTRL_ONEMSEC_IRQ (1 << 3)
#define RTC_CTRL_ALARM_IRQ (1 << 2)
#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1)
#define RTC_CTRL_ALARM_IRQ_EN (1 << 0)
#define RTC_STAT_RTC_PRESENT (1 << 31)
#define RTC_STAT_ALARM_PRESENT (1 << 30)
#define RTC_STAT_WATCHDOG_PRESENT (1 << 29)
#define RTC_STAT_XTAL32000_PRESENT (1 << 28)
#define RTC_STAT_XTAL32768_PRESENT (1 << 27)
#define RTC_STAT_STALE_REGS_MASK (0xff << 16)
#define RTC_STAT_STALE_REGS_OFFSET 16
#define RTC_STAT_NEW_REGS_MASK (0xff << 8)
#define RTC_STAT_NEW_REGS_OFFSET 8
#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff
#define RTC_MILLISECONDS_COUNT_OFFSET 0
#define RTC_SECONDS_COUNT_MASK 0xffffffff
#define RTC_SECONDS_COUNT_OFFSET 0
#define RTC_ALARM_VALUE_MASK 0xffffffff
#define RTC_ALARM_VALUE_OFFSET 0
#define RTC_WATCHDOG_COUNT_MASK 0xffffffff
#define RTC_WATCHDOG_COUNT_OFFSET 0
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28)
#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28)
#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21)
#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20)
#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14)
#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14
#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14)
#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14)
#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14)
#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8)
#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8
#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8)
#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8)
#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8)
#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8)
#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8)
#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4)
#define RTC_PERSISTENT0_LCK_SECS (1 << 3)
#define RTC_PERSISTENT0_ALARM_EN (1 << 2)
#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff
#define RTC_PERSISTENT1_GENERAL_OFFSET 0
#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080
#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100
#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200
#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400
#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800
#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000
#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff
#define RTC_PERSISTENT2_GENERAL_OFFSET 0
#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff
#define RTC_PERSISTENT3_GENERAL_OFFSET 0
#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff
#define RTC_PERSISTENT4_GENERAL_OFFSET 0
#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff
#define RTC_PERSISTENT5_GENERAL_OFFSET 0
#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1)
#define RTC_DEBUG_WATCHDOG_RESET (1 << 0)
#define RTC_VERSION_MAJOR_MASK (0xff << 24)
#define RTC_VERSION_MAJOR_OFFSET 24
#define RTC_VERSION_MINOR_MASK (0xff << 16)
#define RTC_VERSION_MINOR_OFFSET 16
#define RTC_VERSION_STEP_MASK 0xffff
#define RTC_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_RTC_H__ */

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/*
* Freescale i.MX28 SSP Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_ssp_regs {
mx28_reg(hw_ssp_ctrl0)
mx28_reg(hw_ssp_cmd0)
mx28_reg(hw_ssp_cmd1)
mx28_reg(hw_ssp_xfer_size)
mx28_reg(hw_ssp_block_size)
mx28_reg(hw_ssp_compref)
mx28_reg(hw_ssp_compmask)
mx28_reg(hw_ssp_timing)
mx28_reg(hw_ssp_ctrl1)
mx28_reg(hw_ssp_data)
mx28_reg(hw_ssp_sdresp0)
mx28_reg(hw_ssp_sdresp1)
mx28_reg(hw_ssp_sdresp2)
mx28_reg(hw_ssp_sdresp3)
mx28_reg(hw_ssp_ddr_ctrl)
mx28_reg(hw_ssp_dll_ctrl)
mx28_reg(hw_ssp_status)
mx28_reg(hw_ssp_dll_sts)
mx28_reg(hw_ssp_debug)
mx28_reg(hw_ssp_version)
};
#endif
#define SSP_CTRL0_SFTRST (1 << 31)
#define SSP_CTRL0_CLKGATE (1 << 30)
#define SSP_CTRL0_RUN (1 << 29)
#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
#define SSP_CTRL0_LOCK_CS (1 << 27)
#define SSP_CTRL0_IGNORE_CRC (1 << 26)
#define SSP_CTRL0_READ (1 << 25)
#define SSP_CTRL0_DATA_XFER (1 << 24)
#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22)
#define SSP_CTRL0_BUS_WIDTH_OFFSET 22
#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22)
#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22)
#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22)
#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
#define SSP_CTRL0_LONG_RESP (1 << 19)
#define SSP_CTRL0_CHECK_RESP (1 << 18)
#define SSP_CTRL0_GET_RESP (1 << 17)
#define SSP_CTRL0_ENABLE (1 << 16)
#define SSP_CMD0_SOFT_TERMINATE (1 << 26)
#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24)
#define SSP_CMD0_BOOT_ACK_EN (1 << 23)
#define SSP_CMD0_SLOW_CLKING_EN (1 << 22)
#define SSP_CMD0_CONT_CLKING_EN (1 << 21)
#define SSP_CMD0_APPEND_8CYC (1 << 20)
#define SSP_CMD0_CMD_MASK 0xff
#define SSP_CMD0_CMD_OFFSET 0
#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00
#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01
#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02
#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03
#define SSP_CMD0_CMD_MMC_SET_DSR 0x04
#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05
#define SSP_CMD0_CMD_MMC_SWITCH 0x06
#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07
#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08
#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09
#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a
#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b
#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c
#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d
#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e
#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f
#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10
#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11
#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12
#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13
#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14
#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17
#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18
#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19
#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a
#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b
#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c
#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d
#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e
#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23
#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24
#define SSP_CMD0_CMD_MMC_ERASE 0x26
#define SSP_CMD0_CMD_MMC_FAST_IO 0x27
#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28
#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a
#define SSP_CMD0_CMD_MMC_APP_CMD 0x37
#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38
#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00
#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02
#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03
#define SSP_CMD0_CMD_SD_SET_DSR 0x04
#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05
#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07
#define SSP_CMD0_CMD_SD_SEND_CSD 0x09
#define SSP_CMD0_CMD_SD_SEND_CID 0x0a
#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c
#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d
#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f
#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10
#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11
#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12
#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18
#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19
#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b
#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c
#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d
#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e
#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20
#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21
#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23
#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24
#define SSP_CMD0_CMD_SD_ERASE 0x26
#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a
#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34
#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35
#define SSP_CMD0_CMD_SD_APP_CMD 0x37
#define SSP_CMD0_CMD_SD_GEN_CMD 0x38
#define SSP_CMD1_CMD_ARG_MASK 0xffffffff
#define SSP_CMD1_CMD_ARG_OFFSET 0
#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff
#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0
#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4)
#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4
#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf
#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0
#define SSP_COMPREF_REFERENCE_MASK 0xffffffff
#define SSP_COMPREF_REFERENCE_OFFSET 0
#define SSP_COMPMASK_MASK_MASK 0xffffffff
#define SSP_COMPMASK_MASK_OFFSET 0
#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16)
#define SSP_TIMING_TIMEOUT_OFFSET 16
#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8)
#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8
#define SSP_TIMING_CLOCK_RATE_MASK 0xff
#define SSP_TIMING_CLOCK_RATE_OFFSET 0
#define SSP_CTRL1_SDIO_IRQ (1 << 31)
#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20)
#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19)
#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18)
#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
#define SSP_CTRL1_DMA_ENABLE (1 << 13)
#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12)
#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11)
#define SSP_CTRL1_PHASE (1 << 10)
#define SSP_CTRL1_POLARITY (1 << 9)
#define SSP_CTRL1_SLAVE_MODE (1 << 8)
#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4)
#define SSP_CTRL1_WORD_LENGTH_OFFSET 4
#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4)
#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4)
#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4)
#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4)
#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4)
#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4)
#define SSP_CTRL1_SSP_MODE_MASK 0xf
#define SSP_CTRL1_SSP_MODE_OFFSET 0
#define SSP_CTRL1_SSP_MODE_SPI 0x0
#define SSP_CTRL1_SSP_MODE_SSI 0x1
#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3
#define SSP_CTRL1_SSP_MODE_MS 0x4
#define SSP_DATA_DATA_MASK 0xffffffff
#define SSP_DATA_DATA_OFFSET 0
#define SSP_SDRESP0_RESP0_MASK 0xffffffff
#define SSP_SDRESP0_RESP0_OFFSET 0
#define SSP_SDRESP1_RESP1_MASK 0xffffffff
#define SSP_SDRESP1_RESP1_OFFSET 0
#define SSP_SDRESP2_RESP2_MASK 0xffffffff
#define SSP_SDRESP2_RESP2_OFFSET 0
#define SSP_SDRESP3_RESP3_MASK 0xffffffff
#define SSP_SDRESP3_RESP3_OFFSET 0
#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30)
#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30
#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1)
#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0)
#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28)
#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28
#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20)
#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20
#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10)
#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10
#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9)
#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7)
#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3)
#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3
#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2)
#define SSP_DLL_CTRL_RESET (1 << 1)
#define SSP_DLL_CTRL_ENABLE (1 << 0)
#define SSP_STATUS_PRESENT (1 << 31)
#define SSP_STATUS_MS_PRESENT (1 << 30)
#define SSP_STATUS_SD_PRESENT (1 << 29)
#define SSP_STATUS_CARD_DETECT (1 << 28)
#define SSP_STATUS_DMABURST (1 << 22)
#define SSP_STATUS_DMASENSE (1 << 21)
#define SSP_STATUS_DMATERM (1 << 20)
#define SSP_STATUS_DMAREQ (1 << 19)
#define SSP_STATUS_DMAEND (1 << 18)
#define SSP_STATUS_SDIO_IRQ (1 << 17)
#define SSP_STATUS_RESP_CRC_ERR (1 << 16)
#define SSP_STATUS_RESP_ERR (1 << 15)
#define SSP_STATUS_RESP_TIMEOUT (1 << 14)
#define SSP_STATUS_DATA_CRC_ERR (1 << 13)
#define SSP_STATUS_TIMEOUT (1 << 12)
#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11)
#define SSP_STATUS_CEATA_CCS_ERR (1 << 10)
#define SSP_STATUS_FIFO_OVRFLW (1 << 9)
#define SSP_STATUS_FIFO_FULL (1 << 8)
#define SSP_STATUS_FIFO_EMPTY (1 << 5)
#define SSP_STATUS_FIFO_UNDRFLW (1 << 4)
#define SSP_STATUS_CMD_BUSY (1 << 3)
#define SSP_STATUS_DATA_BUSY (1 << 2)
#define SSP_STATUS_BUSY (1 << 0)
#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8)
#define SSP_DLL_STS_REF_SEL_OFFSET 8
#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2)
#define SSP_DLL_STS_SLV_SEL_OFFSET 2
#define SSP_DLL_STS_REF_LOCK (1 << 1)
#define SSP_DLL_STS_SLV_LOCK (1 << 0)
#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28)
#define SSP_DEBUG_DATACRC_ERR_OFFSET 28
#define SSP_DEBUG_DATA_STALL (1 << 27)
#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24)
#define SSP_DEBUG_DAT_SM_OFFSET 24
#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24)
#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24)
#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24)
#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24)
#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24)
#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20)
#define SSP_DEBUG_MSTK_SM_OFFSET 20
#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20)
#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20)
#define SSP_DEBUG_CMD_OE (1 << 19)
#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16)
#define SSP_DEBUG_DMA_SM_OFFSET 16
#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16)
#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16)
#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16)
#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16)
#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16)
#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16)
#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16)
#define SSP_DEBUG_MMC_SM_MASK (0xf << 12)
#define SSP_DEBUG_MMC_SM_OFFSET 12
#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12)
#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12)
#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12)
#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12)
#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12)
#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12)
#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12)
#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12)
#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12)
#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12)
#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12)
#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10)
#define SSP_DEBUG_CMD_SM_OFFSET 10
#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10)
#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10)
#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10)
#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10)
#define SSP_DEBUG_SSP_CMD (1 << 9)
#define SSP_DEBUG_SSP_RESP (1 << 8)
#define SSP_DEBUG_SSP_RXD_MASK 0xff
#define SSP_DEBUG_SSP_RXD_OFFSET 0
#define SSP_VERSION_MAJOR_MASK (0xff << 24)
#define SSP_VERSION_MAJOR_OFFSET 24
#define SSP_VERSION_MINOR_MASK (0xff << 16)
#define SSP_VERSION_MINOR_OFFSET 16
#define SSP_VERSION_STEP_MASK 0xffff
#define SSP_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_SSP_H__ */

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/*
* Freescale i.MX28 TIMROT Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_REGS_TIMROT_H__
#define __MX28_REGS_TIMROT_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mx28_timrot_regs {
mx28_reg(hw_timrot_rotctrl)
mx28_reg(hw_timrot_rotcount)
mx28_reg(hw_timrot_timctrl0)
mx28_reg(hw_timrot_running_count0)
mx28_reg(hw_timrot_fixed_count0)
mx28_reg(hw_timrot_match_count0)
mx28_reg(hw_timrot_timctrl1)
mx28_reg(hw_timrot_running_count1)
mx28_reg(hw_timrot_fixed_count1)
mx28_reg(hw_timrot_match_count1)
mx28_reg(hw_timrot_timctrl2)
mx28_reg(hw_timrot_running_count2)
mx28_reg(hw_timrot_fixed_count2)
mx28_reg(hw_timrot_match_count2)
mx28_reg(hw_timrot_timctrl3)
mx28_reg(hw_timrot_running_count3)
mx28_reg(hw_timrot_fixed_count3)
mx28_reg(hw_timrot_match_count3)
mx28_reg(hw_timrot_version)
};
#endif
#define TIMROT_ROTCTRL_SFTRST (1 << 31)
#define TIMROT_ROTCTRL_CLKGATE (1 << 30)
#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29)
#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28)
#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27)
#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26)
#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25)
#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22)
#define TIMROT_ROTCTRL_STATE_OFFSET 22
#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
#define TIMROT_ROTCTRL_RELATIVE (1 << 12)
#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10)
#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10
#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10)
#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10)
#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10)
#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2
#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
#define TIMROT_TIMCTRLn_IRQ (1 << 15)
#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4)
#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4
#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4)
#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4)
#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4)
#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4)
#define TIMROT_TIMCTRLn_SELECT_MASK 0xf
#define TIMROT_TIMCTRLn_SELECT_OFFSET 0
#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0
#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1
#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2
#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9
#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa
#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb
#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
#define TIMROT_VERSION_MAJOR_OFFSET 24
#define TIMROT_VERSION_MINOR_MASK (0xff << 16)
#define TIMROT_VERSION_MINOR_OFFSET 16
#define TIMROT_VERSION_STEP_MASK 0xffff
#define TIMROT_VERSION_STEP_OFFSET 0
#endif /* __MX28_REGS_TIMROT_H__ */

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/*
* Freescale i.MX28 USB OTG Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __REGS_USB_H__
#define __REGS_USB_H__
struct mx28_usb_regs {
uint32_t hw_usbctrl_id; /* 0x000 */
uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
uint32_t hw_usbctrl_hwhost; /* 0x008 */
uint32_t hw_usbctrl_hwdevice; /* 0x00c */
uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */
uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */
uint32_t reserved1[26];
uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */
uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */
uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */
uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */
uint32_t hw_usbctrl_sbuscfg; /* 0x090 */
uint32_t reserved2[27];
uint32_t hw_usbctrl_caplength; /* 0x100 */
uint32_t hw_usbctrl_hcsparams; /* 0x104 */
uint32_t hw_usbctrl_hccparams; /* 0x108 */
uint32_t reserved3[5];
uint32_t hw_usbctrl_dciversion; /* 0x120 */
uint32_t hw_usbctrl_dccparams; /* 0x124 */
uint32_t reserved4[6];
uint32_t hw_usbctrl_usbcmd; /* 0x140 */
uint32_t hw_usbctrl_usbsts; /* 0x144 */
uint32_t hw_usbctrl_usbintr; /* 0x148 */
uint32_t hw_usbctrl_frindex; /* 0x14c */
uint32_t reserved5;
union {
uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */
uint32_t hw_usbctrl_deviceaddr; /* 0x154 */
};
union {
uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */
uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */
};
uint32_t hw_usbctrl_ttctrl; /* 0x15c */
uint32_t hw_usbctrl_burstsize; /* 0x160 */
uint32_t hw_usbctrl_txfilltuning; /* 0x164 */
uint32_t reserved6;
uint32_t hw_usbctrl_ic_usb; /* 0x16c */
uint32_t hw_usbctrl_ulpi; /* 0x170 */
uint32_t reserved7;
uint32_t hw_usbctrl_endptnak; /* 0x178 */
uint32_t hw_usbctrl_endptnaken; /* 0x17c */
uint32_t reserved8;
uint32_t hw_usbctrl_portsc1; /* 0x184 */
uint32_t reserved9[7];
uint32_t hw_usbctrl_otgsc; /* 0x1a4 */
uint32_t hw_usbctrl_usbmode; /* 0x1a8 */
uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */
uint32_t hw_usbctrl_endptprime; /* 0x1b0 */
uint32_t hw_usbctrl_endptflush; /* 0x1b4 */
uint32_t hw_usbctrl_endptstat; /* 0x1b8 */
uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */
uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */
uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */
uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */
uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */
uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */
uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */
uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */
uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */
};
#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
#define HW_USBCTRL_ID_CIVERSION_OFFSET 29
#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29)
#define HW_USBCTRL_ID_VERSION_OFFSET 25
#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25)
#define HW_USBCTRL_ID_REVISION_OFFSET 21
#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21)
#define HW_USBCTRL_ID_TAG_OFFSET 16
#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16)
#define HW_USBCTRL_ID_NID_OFFSET 8
#define HW_USBCTRL_ID_NID_MASK (0x3f << 8)
#define HW_USBCTRL_ID_ID_OFFSET 0
#define HW_USBCTRL_ID_ID_MASK (0x3f << 0)
#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9
#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9)
#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6
#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6)
#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4
#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4)
#define HW_USBCTRL_HWGENERAL_BWT (1 << 3)
#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1
#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1)
#define HW_USBCTRL_HWGENERAL_RT (1 << 0)
#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24
#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24)
#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16
#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19)
#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1
#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1)
#define HW_USBCTRL_HWHOST_HC (1 << 0)
#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1
#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1)
#define HW_USBCTRL_HWDEVICE_DC (1 << 0)
#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31)
#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16
#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16)
#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8
#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8)
#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0
#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff
#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8
#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8)
#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0
#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff
#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0
#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff
#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31)
#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30)
#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24)
#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0
#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff
#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0
#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7
#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0
#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1
#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2
#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3
#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5
#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6
#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7
#endif /* __REGS_USB_H__ */

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/*
* Freescale i.MX28 USB PHY Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __REGS_USBPHY_H__
#define __REGS_USBPHY_H__
struct mx28_usbphy_regs {
mx28_reg(hw_usbphy_pwd)
mx28_reg(hw_usbphy_tx)
mx28_reg(hw_usbphy_rx)
mx28_reg(hw_usbphy_ctrl)
mx28_reg(hw_usbphy_status)
mx28_reg(hw_usbphy_debug)
mx28_reg(hw_usbphy_debug0_status)
mx28_reg(hw_usbphy_debug1)
mx28_reg(hw_usbphy_version)
mx28_reg(hw_usbphy_ip)
};
#define USBPHY_PWD_RXPWDRX (1 << 20)
#define USBPHY_PWD_RXPWDDIFF (1 << 19)
#define USBPHY_PWD_RXPWD1PT1 (1 << 18)
#define USBPHY_PWD_RXPWDENV (1 << 17)
#define USBPHY_PWD_TXPWDV2I (1 << 12)
#define USBPHY_PWD_TXPWDIBIAS (1 << 11)
#define USBPHY_PWD_TXPWDFS (1 << 10)
#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26
#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26)
#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25)
#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24)
#define USBPHY_TX_TXENCAL45DP (1 << 21)
#define USBPHY_TX_TXCAL45DP_OFFSET 16
#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16)
#define USBPHY_TX_TXENCAL45DM (1 << 13)
#define USBPHY_TX_TXCAL45DM_OFFSET 8
#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8)
#define USBPHY_TX_D_CAL_OFFSET 0
#define USBPHY_TX_D_CAL_MASK 0xf
#define USBPHY_RX_RXDBYPASS (1 << 22)
#define USBPHY_RX_DISCONADJ_OFFSET 4
#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4)
#define USBPHY_RX_ENVADJ_OFFSET 0
#define USBPHY_RX_ENVADJ_MASK 0x7
#define USBPHY_CTRL_SFTRST (1 << 31)
#define USBPHY_CTRL_CLKGATE (1 << 30)
#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28)
#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26)
#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25)
#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24)
#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23)
#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22)
#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19)
#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18)
#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17)
#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16)
#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13)
#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12)
#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11)
#define USBPHY_CTRL_RESUME_IRQ (1 << 10)
#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9)
#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8)
#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5)
#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3)
#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2)
#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1)
#define USBPHY_STATUS_RESUME_STATUS (1 << 10)
#define USBPHY_STATUS_OTGID_STATUS (1 << 8)
#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3)
#define USBPHY_DEBUG_CLKGATE (1 << 30)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25)
#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16)
#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12)
#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8
#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8)
#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4
#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4)
#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2
#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1)
#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff
#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13
#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13)
#define USBPHY_DEBUG1_ENTX2TX (1 << 12)
#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0
#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf
#define USBPHY_VERSION_MAJOR_MASK (0xff << 24)
#define USBPHY_VERSION_MAJOR_OFFSET 24
#define USBPHY_VERSION_MINOR_MASK (0xff << 16)
#define USBPHY_VERSION_MINOR_OFFSET 16
#define USBPHY_VERSION_STEP_MASK 0xffff
#define USBPHY_VERSION_STEP_OFFSET 0
#define USBPHY_IP_DIV_SEL_OFFSET 23
#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23)
#define USBPHY_IP_LFR_SEL_OFFSET 21
#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21)
#define USBPHY_IP_CP_SEL_OFFSET 19
#define USBPHY_IP_CP_SEL_MASK (0x3 << 19)
#define USBPHY_IP_TSTI_TX_DP (1 << 18)
#define USBPHY_IP_TSTI_TX_DM (1 << 17)
#define USBPHY_IP_ANALOG_TESTMODE (1 << 16)
#define USBPHY_IP_EN_USB_CLKS (1 << 2)
#define USBPHY_IP_PLL_LOCKED (1 << 1)
#define USBPHY_IP_PLL_POWER (1 << 0)
#endif /* __REGS_USBPHY_H__ */

32
arch/arm/include/asm/arch-mx28/sys_proto.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Freescale i.MX28 MX28 specific functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX28_H__
#define __MX28_H__
int mx28_reset_block(struct mx28_register *reg);
int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout);
int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
#endif /* __MX28_H__ */

7
arch/arm/include/asm/arch-mx31/imx-regs.h
View File

@ -98,6 +98,12 @@ struct iim_regs {
u32 iim_scs3;
};
struct iomuxc_regs {
u32 unused1;
u32 unused2;
u32 gpr;
};
struct mx3_cpu_type {
u8 srev;
u32 v;
@ -636,7 +642,6 @@ struct esdc_regs {
#define WEIM_BASE 0xb8002000
#define IOMUXC_BASE 0x43FAC000
#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)

11
arch/arm/include/asm/arch-omap3/mmc_host_def.h
View File

@ -55,7 +55,7 @@ typedef struct t2 {
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
typedef struct hsmmc {
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
@ -77,7 +77,7 @@ typedef struct hsmmc {
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
} hsmmc_t;
};
/*
* OMAP HS MMC Bit definitions
@ -182,13 +182,6 @@ typedef struct hsmmc {
#define CLK_400KHZ 1
#define CLK_MISC 2
typedef struct {
unsigned int card_type;
unsigned int version;
unsigned int mode;
unsigned int size;
unsigned int RCA;
} mmc_card_data;
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)

23
arch/arm/include/asm/arch-omap4/clocks.h
View File

@ -687,4 +687,27 @@ struct dpll_params {
s8 m7;
};
extern struct omap4_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(u32 reg, u32 volt_mv);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_sri2c(void);
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */

1021
arch/arm/include/asm/arch-omap4/emif.h
View File

File diff suppressed because it is too large Load Diff

11
arch/arm/include/asm/arch-omap4/mmc_host_def.h
View File

@ -33,7 +33,7 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
typedef struct hsmmc {
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
@ -55,7 +55,7 @@ typedef struct hsmmc {
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
} hsmmc_t;
};
/*
* OMAP HS MMC Bit definitions
@ -160,13 +160,6 @@ typedef struct hsmmc {
#define CLK_400KHZ 1
#define CLK_MISC 2
typedef struct {
unsigned int card_type;
unsigned int version;
unsigned int mode;
unsigned int size;
unsigned int RCA;
} mmc_card_data;
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)

46
arch/arm/include/asm/arch-omap4/omap4.h → arch/arm/include/asm/arch-omap4/omap.h
View File

@ -44,7 +44,8 @@
#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
@ -57,16 +58,11 @@
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
/* 4430 */
#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
/* 4460 */
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
@ -151,7 +147,7 @@ struct omap4_sys_ctrl_regs {
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad3[260277];
unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad4[63];
unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */
@ -188,16 +184,6 @@ struct control_lpddr2io_regs {
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define OMAP4430_ES1_0 0x44300100
#define OMAP4430_ES2_0 0x44300200
#define OMAP4430_ES2_1 0x44300210
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
/* ROM code defines */
/* Boot device */
#define BOOT_DEVICE_MASK 0xFF
@ -205,5 +191,21 @@ struct control_lpddr2io_regs {
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
#define RESET_REASON_OFFSET 0x9
#define CH_FLAGS_OFFSET 0xA
#define CH_FLAGS_CHSETTINGS (0x1 << 0)
#define CH_FLAGS_CHRAM (0x1 << 1)
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
#ifndef __ASSEMBLY__
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
unsigned char omap_bootdevice;
unsigned char reset_reason;
unsigned char ch_flags;
};
#endif
#endif

38
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -21,7 +21,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/arch/omap4.h>
#include <asm/arch/omap.h>
#include <asm/arch/clocks.h>
#include <asm/io.h>
#include <asm/omap_common.h>
@ -32,17 +32,17 @@ struct omap_sysinfo {
};
extern const struct omap_sysinfo sysinfo;
extern struct omap4_prcm_regs *const prcm;
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
void omap_rev_string(char *omap_rev_string);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
@ -51,7 +51,17 @@ u32 get_sys_clk_freq(void);
u32 omap4_ddr_clk(void);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdram_init(void);
u32 omap4_sdram_size(void);
u32 omap_sdram_size(void);
u32 cortex_rev(void);
void init_omap_revision(void);
void do_io_settings(void);
/*
* This is used to verify if the configuration header
* was executed by Romcode prior to control of transfer
* to the bootloader. SPL is responsible for saving and
* passing this to the u-boot.
*/
extern struct omap_boot_parameters boot_params;
static inline u32 running_from_sdram(void)
{
@ -64,15 +74,17 @@ static inline u32 running_from_sdram(void)
static inline u8 uboot_loaded_by_spl(void)
{
/*
* Configuration Header is not supported yet, so u-boot init running
* from SDRAM implies that it was loaded by SPL. When this situation
* changes one of these approaches could be taken:
* i. Pass a magic from SPL to U-Boot and U-Boot save it at a known
* location.
* ii. Check the OPP. CH can support only 50% OPP while SPL initializes
* the DPLLs at 100% OPP.
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
return running_from_sdram();
if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
@ -86,7 +98,7 @@ static inline u8 uboot_loaded_by_spl(void)
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
static inline u32 omap4_hw_init_context(void)
static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;

722
arch/arm/include/asm/arch-omap5/clocks.h Normal file
View File

@ -0,0 +1,722 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
* loop, allow for a minimum of 2 ms wait (in reality the wait will be
* much more than that)
*/
#define LDELAY 1000000
#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
struct omap5_prcm_regs {
/* cm1.ckgen */
u32 cm_clksel_core; /* 4a004100 */
u32 pad001[1]; /* 4a004104 */
u32 cm_clksel_abe; /* 4a004108 */
u32 pad002[1]; /* 4a00410c */
u32 cm_dll_ctrl; /* 4a004110 */
u32 pad003[3]; /* 4a004114 */
u32 cm_clkmode_dpll_core; /* 4a004120 */
u32 cm_idlest_dpll_core; /* 4a004124 */
u32 cm_autoidle_dpll_core; /* 4a004128 */
u32 cm_clksel_dpll_core; /* 4a00412c */
u32 cm_div_m2_dpll_core; /* 4a004130 */
u32 cm_div_m3_dpll_core; /* 4a004134 */
u32 cm_div_h11_dpll_core; /* 4a004138 */
u32 cm_div_h12_dpll_core; /* 4a00413c */
u32 cm_div_h13_dpll_core; /* 4a004140 */
u32 cm_div_h14_dpll_core; /* 4a004144 */
u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
u32 cm_emu_override_dpll_core; /* 4a004150 */
u32 cm_div_h22_dpllcore; /* 4a004154 */
u32 cm_div_h23_dpll_core; /* 4a004158 */
u32 pad0041[1]; /* 4a00415c */
u32 cm_clkmode_dpll_mpu; /* 4a004160 */
u32 cm_idlest_dpll_mpu; /* 4a004164 */
u32 cm_autoidle_dpll_mpu; /* 4a004168 */
u32 cm_clksel_dpll_mpu; /* 4a00416c */
u32 cm_div_m2_dpll_mpu; /* 4a004170 */
u32 pad005[5]; /* 4a004174 */
u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
u32 pad006[3]; /* 4a004190 */
u32 cm_bypclk_dpll_mpu; /* 4a00419c */
u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
u32 cm_idlest_dpll_iva; /* 4a0041a4 */
u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
u32 cm_clksel_dpll_iva; /* 4a0041ac */
u32 pad007[2]; /* 4a0041b0 */
u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
u32 cm_div_h12_dpll_iva; /* 4a0041bc */
u32 pad008[2]; /* 4a0041c0 */
u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
u32 pad009[3]; /* 4a0041d0 */
u32 cm_bypclk_dpll_iva; /* 4a0041dc */
u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
u32 cm_idlest_dpll_abe; /* 4a0041e4 */
u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
u32 cm_clksel_dpll_abe; /* 4a0041ec */
u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
u32 pad010[4]; /* 4a0041f8 */
u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
u32 pad011[4]; /* 4a004210 */
u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
u32 pad012[1]; /* 4a004234 */
u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
u32 pad013[1]; /* 4a004244 */
u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
u32 pad014[5]; /* 4a00424c */
u32 cm_shadow_freq_config1; /* 4a004260 */
u32 pad0141[47]; /* 4a004264 */
u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
/* cm1.dsp */
u32 pad015[55]; /* 4a004324 */
u32 cm_dsp_clkstctrl; /* 4a004400 */
u32 pad016[7]; /* 4a004404 */
u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
/* cm1.abe */
u32 pad017[55]; /* 4a004424 */
u32 cm1_abe_clkstctrl; /* 4a004500 */
u32 pad018[7]; /* 4a004504 */
u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
u32 pad019[1]; /* 4a004524 */
u32 cm1_abe_aess_clkctrl; /* 4a004528 */
u32 pad020[1]; /* 4a00452c */
u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
u32 pad021[1]; /* 4a004534 */
u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
u32 pad022[1]; /* 4a00453c */
u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
u32 pad023[1]; /* 4a004544 */
u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
u32 pad024[1]; /* 4a00454c */
u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
u32 pad025[1]; /* 4a004554 */
u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
u32 pad026[1]; /* 4a00455c */
u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
u32 pad027[1]; /* 4a004564 */
u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
u32 pad028[1]; /* 4a00456c */
u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
u32 pad029[1]; /* 4a004574 */
u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
u32 pad030[1]; /* 4a00457c */
u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
u32 pad031[1]; /* 4a004584 */
u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
/* cm2.ckgen */
u32 pad032[3805]; /* 4a00458c */
u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
u32 cm_clksel_usb_60mhz; /* 4a008104 */
u32 cm_scale_fclk; /* 4a008108 */
u32 pad033[1]; /* 4a00810c */
u32 cm_core_dvfs_perf1; /* 4a008110 */
u32 cm_core_dvfs_perf2; /* 4a008114 */
u32 cm_core_dvfs_perf3; /* 4a008118 */
u32 cm_core_dvfs_perf4; /* 4a00811c */
u32 pad034[1]; /* 4a008120 */
u32 cm_core_dvfs_current; /* 4a008124 */
u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
u32 pad035[1]; /* 4a008134 */
u32 cm_iva_dvfs_current; /* 4a008138 */
u32 pad036[1]; /* 4a00813c */
u32 cm_clkmode_dpll_per; /* 4a008140 */
u32 cm_idlest_dpll_per; /* 4a008144 */
u32 cm_autoidle_dpll_per; /* 4a008148 */
u32 cm_clksel_dpll_per; /* 4a00814c */
u32 cm_div_m2_dpll_per; /* 4a008150 */
u32 cm_div_m3_dpll_per; /* 4a008154 */
u32 cm_div_h11_dpll_per; /* 4a008158 */
u32 cm_div_h12_dpll_per; /* 4a00815c */
u32 pad0361[1]; /* 4a008160 */
u32 cm_div_h14_dpll_per; /* 4a008164 */
u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
u32 cm_emu_override_dpll_per; /* 4a008170 */
u32 pad037[3]; /* 4a008174 */
u32 cm_clkmode_dpll_usb; /* 4a008180 */
u32 cm_idlest_dpll_usb; /* 4a008184 */
u32 cm_autoidle_dpll_usb; /* 4a008188 */
u32 cm_clksel_dpll_usb; /* 4a00818c */
u32 cm_div_m2_dpll_usb; /* 4a008190 */
u32 pad038[5]; /* 4a008194 */
u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
u32 pad039[1]; /* 4a0081b0 */
u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
u32 pad040[2]; /* 4a0081b8 */
u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
u32 cm_clksel_dpll_unipro; /* 4a0081cc */
u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
u32 pad041[5]; /* 4a0081d4 */
u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
/* cm2.core */
u32 pad0411[324]; /* 4a0081f0 */
u32 cm_l3_1_clkstctrl; /* 4a008700 */
u32 pad042[1]; /* 4a008704 */
u32 cm_l3_1_dynamicdep; /* 4a008708 */
u32 pad043[5]; /* 4a00870c */
u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
u32 pad044[55]; /* 4a008724 */
u32 cm_l3_2_clkstctrl; /* 4a008800 */
u32 pad045[1]; /* 4a008804 */
u32 cm_l3_2_dynamicdep; /* 4a008808 */
u32 pad046[5]; /* 4a00880c */
u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
u32 pad047[1]; /* 4a008824 */
u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
u32 pad048[1]; /* 4a00882c */
u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
u32 pad049[51]; /* 4a008834 */
u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
u32 cm_mpu_m3_staticdep; /* 4a008904 */
u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
u32 pad050[5]; /* 4a00890c */
u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
u32 pad051[55]; /* 4a008924 */
u32 cm_sdma_clkstctrl; /* 4a008a00 */
u32 cm_sdma_staticdep; /* 4a008a04 */
u32 cm_sdma_dynamicdep; /* 4a008a08 */
u32 pad052[5]; /* 4a008a0c */
u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
u32 pad053[55]; /* 4a008a24 */
u32 cm_memif_clkstctrl; /* 4a008b00 */
u32 pad054[7]; /* 4a008b04 */
u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
u32 pad055[1]; /* 4a008b24 */
u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
u32 pad056[1]; /* 4a008b2c */
u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
u32 pad057[1]; /* 4a008b34 */
u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
u32 pad058[1]; /* 4a008b3c */
u32 cm_memif_dll_clkctrl; /* 4a008b40 */
u32 pad059[3]; /* 4a008b44 */
u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
u32 pad060[1]; /* 4a008b54 */
u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
u32 pad061[1]; /* 4a008b5c */
u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
u32 pad062[39]; /* 4a008b64 */
u32 cm_c2c_clkstctrl; /* 4a008c00 */
u32 cm_c2c_staticdep; /* 4a008c04 */
u32 cm_c2c_dynamicdep; /* 4a008c08 */
u32 pad063[5]; /* 4a008c0c */
u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
u32 pad064[1]; /* 4a008c24 */
u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
u32 pad065[1]; /* 4a008c2c */
u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
u32 pad066[51]; /* 4a008c34 */
u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
u32 pad067[1]; /* 4a008d04 */
u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
u32 pad068[5]; /* 4a008d0c */
u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
u32 pad069[1]; /* 4a008d24 */
u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
u32 pad070[1]; /* 4a008d2c */
u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
u32 pad071[1]; /* 4a008d34 */
u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
u32 pad072[49]; /* 4a008d3c */
u32 cm_l3instr_clkstctrl; /* 4a008e00 */
u32 pad073[7]; /* 4a008e04 */
u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
u32 pad074[1]; /* 4a008e24 */
u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
u32 pad075[5]; /* 4a008e2c */
u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
/* cm2.ivahd */
u32 pad076[47]; /* 4a008e44 */
u32 cm_ivahd_clkstctrl; /* 4a008f00 */
u32 pad077[7]; /* 4a008f04 */
u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
u32 pad078[1]; /* 4a008f24 */
u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
/* cm2.cam */
u32 pad079[53]; /* 4a008f2c */
u32 cm_cam_clkstctrl; /* 4a009000 */
u32 pad080[7]; /* 4a009004 */
u32 cm_cam_iss_clkctrl; /* 4a009020 */
u32 pad081[1]; /* 4a009024 */
u32 cm_cam_fdif_clkctrl; /* 4a009028 */
/* cm2.dss */
u32 pad082[53]; /* 4a00902c */
u32 cm_dss_clkstctrl; /* 4a009100 */
u32 pad083[7]; /* 4a009104 */
u32 cm_dss_dss_clkctrl; /* 4a009120 */
/* cm2.sgx */
u32 pad084[55]; /* 4a009124 */
u32 cm_sgx_clkstctrl; /* 4a009200 */
u32 pad085[7]; /* 4a009204 */
u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
/* cm2.l3init */
u32 pad086[55]; /* 4a009224 */
u32 cm_l3init_clkstctrl; /* 4a009300 */
/* cm2.l3init */
u32 pad087[9]; /* 4a009304 */
u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
u32 pad088[1]; /* 4a00932c */
u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
u32 pad089[1]; /* 4a009334 */
u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
u32 pad090[7]; /* 4a00933c */
u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
u32 pad091[1]; /* 4a00935c */
u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
u32 pad092[1]; /* 4a009364 */
u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
u32 pad093[3]; /* 4a00936c */
u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
u32 pad094[21]; /* 4a00937c */
u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
u32 pad095[3]; /* 4a0093d4 */
u32 cm_l3init_ocp2scp1_clkctrl;
/* cm2.l4per */
u32 pad096[7]; /* 4a0093e4 */
u32 cm_l4per_clkstctrl; /* 4a009400 */
u32 pad097[1]; /* 4a009404 */
u32 cm_l4per_dynamicdep; /* 4a009408 */
u32 pad098[5]; /* 4a00940c */
u32 cm_l4per_adc_clkctrl; /* 4a009420 */
u32 pad100[1]; /* 4a009424 */
u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
u32 pad101[1]; /* 4a00942c */
u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
u32 pad102[1]; /* 4a009434 */
u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
u32 pad103[1]; /* 4a00943c */
u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
u32 pad104[1]; /* 4a009444 */
u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
u32 pad105[1]; /* 4a00944c */
u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
u32 pad106[1]; /* 4a009454 */
u32 cm_l4per_elm_clkctrl; /* 4a009458 */
u32 pad107[1]; /* 4a00945c */
u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
u32 pad108[1]; /* 4a009464 */
u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
u32 pad109[1]; /* 4a00946c */
u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
u32 pad110[1]; /* 4a009474 */
u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
u32 pad111[1]; /* 4a00947c */
u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
u32 pad112[1]; /* 4a009484 */
u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
u32 pad113[1]; /* 4a00948c */
u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
u32 pad114[1]; /* 4a009494 */
u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
u32 pad115[1]; /* 4a00949c */
u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
u32 pad116[1]; /* 4a0094a4 */
u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
u32 pad117[1]; /* 4a0094ac */
u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
u32 pad118[1]; /* 4a0094b4 */
u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
u32 pad119[1]; /* 4a0094bc */
u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
u32 pad1191[3]; /* 4a0094c4 */
u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
u32 pad120[1]; /* 4a0094d4 */
u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
u32 pad121[3]; /* 4a0094dc */
u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
u32 pad123[1]; /* 4a0094ec */
u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
u32 pad124[1]; /* 4a0094f4 */
u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
u32 pad125[1]; /* 4a0094fc */
u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
u32 pad126[1]; /* 4a009504 */
u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
u32 pad127[1]; /* 4a00950c */
u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
u32 pad1271[1]; /* 4a009514 */
u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
u32 pad1272[1]; /* 4a00951c */
u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
u32 pad128[1]; /* 4a009524 */
u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
u32 pad129[1]; /* 4a00952c */
u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
u32 pad130[1]; /* 4a009534 */
u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
u32 pad131[1]; /* 4a00953c */
u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
u32 pad132[1]; /* 4a009544 */
u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
u32 pad133[1]; /* 4a00954c */
u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
u32 pad134[1]; /* 4a009554 */
u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
u32 pad135[1]; /* 4a00955c */
u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
u32 pad136[1]; /* 4a009564 */
u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
u32 pad1371[1]; /* 4a00956c */
u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
u32 pad1372[1]; /* 4a009574 */
u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
u32 pad1374[1]; /* 4a00957c */
u32 cm_l4sec_clkstctrl; /* 4a009580 */
u32 cm_l4sec_staticdep; /* 4a009584 */
u32 cm_l4sec_dynamicdep; /* 4a009588 */
u32 pad138[5]; /* 4a00958c */
u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
u32 pad139[1]; /* 4a0095a4 */
u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
u32 pad140[1]; /* 4a0095ac */
u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
u32 pad141[1]; /* 4a0095b4 */
u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
u32 pad142[1]; /* 4a0095bc */
u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
u32 pad143[1]; /* 4a0095c4 */
u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
u32 pad144[3]; /* 4a0095cc */
u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
u32 pad145[3660425]; /* 4a0095dc */
/* l4 wkup regs */
u32 pad201[6211]; /* 4ae00000 */
u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
u32 cm_sys_clksel; /* 4ae06110 */
u32 pad202[1467]; /* 4ae06114 */
u32 cm_wkup_clkstctrl; /* 4ae07800 */
u32 pad203[7]; /* 4ae07804 */
u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
u32 pad204; /* 4ae07824 */
u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
u32 pad205; /* 4ae0782c */
u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
u32 pad206; /* 4ae07834 */
u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
u32 pad207; /* 4ae0783c */
u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
u32 pad208; /* 4ae07844 */
u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
u32 pad209; /* 4ae0784c */
u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
u32 pad210; /* 4ae07854 */
u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
u32 pad211; /* 4ae0785c */
u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
u32 pad212[5]; /* 4ae07864 */
u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
u32 pad213; /* 4ae0787c */
u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
u32 pad214; /* 4ae07884 */
u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
u32 pad215[197]; /* 4ae0788c */
u32 prm_vc_val_bypass; /* 4ae07ba0 */
u32 pad216[4];
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
};
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
#define CM_AUTOIDLE_DPLL 0x8
#define CM_CLKSEL_DPLL 0xC
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
#define CM_CLKMODE_DPLL_EN_SHIFT 0
#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
#define DPLL_EN_STOP 1
#define DPLL_EN_MN_BYPASS 4
#define DPLL_EN_LOW_POWER_BYPASS 5
#define DPLL_EN_FAST_RELOCK_BYPASS 6
#define DPLL_EN_LOCK 7
/* CM_IDLEST_DPLL fields */
#define ST_DPLL_CLK_MASK 1
/* CM_CLKSEL_DPLL */
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
#define CM_CLKSEL_DPLL_M_SHIFT 8
#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
#define OMAP4_DPLL_MAX_N 127
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0
#define CLKSEL_L3_SHIFT 4
#define CLKSEL_L4_SHIFT 8
#define CLKSEL_CORE_X2_DIV_1 0
#define CLKSEL_L3_CORE_DIV_2 1
#define CLKSEL_L4_L3_DIV_2 1
/* CM_ABE_PLL_REF_CLKSEL */
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
/* CM_SHADOW_FREQ_CONFIG1 */
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
/*CM_<clock_domain>__CLKCTRL */
#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
#define CD_CLKCTRL_CLKTRCTRL_MASK 3
#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
#define MODULE_CLKCTRL_MODULEMODE_MASK 3
#define MODULE_CLKCTRL_IDLEST_SHIFT 16
#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
#define MODULE_CLKCTRL_IDLEST_IDLE 2
#define MODULE_CLKCTRL_IDLEST_DISABLED 3
/* CM_L4PER_GPIO4_CLKCTRL */
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
/* CM_CAM_ISS_CLKCTRL */
#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_DSS_DSS_CLKCTRL */
#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
#define OMAP_32K_CLK_FREQ 32768
/* PRM_VC_CFG_I2C_CLK */
#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR 0x12
#define SMPS_REG_ADDR_VCORE1 0x55
#define SMPS_REG_ADDR_VCORE2 0x5B
#define SMPS_REG_ADDR_VCORE3 0x61
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
#define TPS62361_REG_ADDR_SET1 0x1
#define TPS62361_REG_ADDR_SET2 0x2
#define TPS62361_REG_ADDR_SET3 0x3
#define TPS62361_REG_ADDR_CTRL 0x4
#define TPS62361_REG_ADDR_TEMP 0x5
#define TPS62361_REG_ADDR_RMP_CTRL 0x6
#define TPS62361_REG_ADDR_CHIP_ID 0x8
#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
#define TPS62361_BASE_VOLT_MV 500
#define TPS62361_VSEL0_GPIO 7
/* Defines for DPLL setup */
#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
#define NUM_SYS_CLKS 7
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_h11_dpll;
u32 cm_div_h12_dpll;
u32 cm_div_h13_dpll;
u32 cm_div_h14_dpll;
u32 reserved[2];
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
};
/* DPLL parameter table */
struct dpll_params {
u32 m;
u32 n;
u8 m2;
u8 m3;
u8 h11;
u8 h12;
u8 h13;
u8 h14;
u8 h22;
u8 h23;
};
extern struct omap5_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(u32 reg, u32 volt_mv);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_sri2c(void);
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_non_essential_clocks(void);
void enable_basic_uboot_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP5_H_ */

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/*
* (C) Copyright 2006-2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _CPU_H
#define _CPU_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
u32 config1; /* 0x00 */
u32 config2; /* 0x04 */
u32 config3; /* 0x08 */
u32 config4; /* 0x0C */
u32 config5; /* 0x10 */
u32 config6; /* 0x14 */
u32 config7; /* 0x18 */
u32 nand_cmd; /* 0x1C */
u32 nand_adr; /* 0x20 */
u32 nand_dat; /* 0x24 */
u8 res[8]; /* blow up to 0x30 byte */
};
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
u8 res2[0x4];
u32 irqstatus; /* 0x18 */
u32 irqenable; /* 0x1C */
u8 res3[0x20];
u32 timeout_control; /* 0x40 */
u8 res4[0xC];
u32 config; /* 0x50 */
u32 status; /* 0x54 */
u8 res5[0x8]; /* 0x58 */
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
u8 res6[0x14]; /* 0x1E0 */
u32 ecc_config; /* 0x1F4 */
u32 ecc_control; /* 0x1F8 */
u32 ecc_size_config; /* 0x1FC */
u32 ecc1_result; /* 0x200 */
u32 ecc2_result; /* 0x204 */
u32 ecc3_result; /* 0x208 */
u32 ecc4_result; /* 0x20C */
u32 ecc5_result; /* 0x210 */
u32 ecc6_result; /* 0x214 */
u32 ecc7_result; /* 0x218 */
u32 ecc8_result; /* 0x21C */
u32 ecc9_result; /* 0x220 */
};
/* Used for board specific gpmc initialization */
extern struct gpmc *gpmc_cfg;
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res1[0xc];
u32 tiocp_cfg; /* 0x10 rw */
u8 res2[0x10];
u32 tisr_raw; /* 0x24 r */
u32 tisr; /* 0x28 rw */
u32 tier; /* 0x2c rw */
u32 ticr; /* 0x30 rw */
u32 twer; /* 0x34 rw */
u32 tclr; /* 0x38 rw */
u32 tcrr; /* 0x3c rw */
u32 tldr; /* 0x40 rw */
u32 ttgr; /* 0x44 rw */
u32 twpc; /* 0x48 r */
u32 tmar; /* 0x4c rw */
u32 tcar1; /* 0x50 r */
u32 tcicr; /* 0x54 rw */
u32 tcar2; /* 0x58 r */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
/* enable sys_clk NO-prescale /1 */
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct watchdog {
u8 res1[0x34];
u32 wwps; /* 0x34 r */
u8 res2[0x10];
u32 wspr; /* 0x48 rw */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
#define SYSCLKDIV_1 (0x1 << 6)
#define SYSCLKDIV_2 (0x1 << 7)
#define CLKSEL_GPT1 (0x1 << 0)
#define EN_GPT1 (0x1 << 0)
#define EN_32KSYNC (0x1 << 2)
#define ST_WDT2 (0x1 << 5)
#define RESETDONE (0x1 << 0)
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* GPMC BASE */
#define GPMC_BASE (OMAP54XX_GPMC_BASE)
/* I2C base */
#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
/* MUSB base */
#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
/* OMAP4 GPIO registers */
#define OMAP_GPIO_REVISION 0x0000
#define OMAP_GPIO_SYSCONFIG 0x0010
#define OMAP_GPIO_SYSSTATUS 0x0114
#define OMAP_GPIO_IRQSTATUS1 0x0118
#define OMAP_GPIO_IRQSTATUS2 0x0128
#define OMAP_GPIO_IRQENABLE2 0x012c
#define OMAP_GPIO_IRQENABLE1 0x011c
#define OMAP_GPIO_WAKE_EN 0x0120
#define OMAP_GPIO_CTRL 0x0130
#define OMAP_GPIO_OE 0x0134
#define OMAP_GPIO_DATAIN 0x0138
#define OMAP_GPIO_DATAOUT 0x013c
#define OMAP_GPIO_LEVELDETECT0 0x0140
#define OMAP_GPIO_LEVELDETECT1 0x0144
#define OMAP_GPIO_RISINGDETECT 0x0148
#define OMAP_GPIO_FALLINGDETECT 0x014c
#define OMAP_GPIO_DEBOUNCE_EN 0x0150
#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
#define OMAP_GPIO_SETIRQENABLE1 0x0164
#define OMAP_GPIO_CLEARWKUENA 0x0180
#define OMAP_GPIO_SETWKUENA 0x0184
#define OMAP_GPIO_CLEARDATAOUT 0x0190
#define OMAP_GPIO_SETDATAOUT 0x0194
#endif /* _CPU_H */

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/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _GPIO_OMAP5_H
#define _GPIO_OMAP5_H
#include <asm/omap_gpio.h>
#define OMAP54XX_GPIO1_BASE 0x4Ae10000
#define OMAP54XX_GPIO2_BASE 0x48055000
#define OMAP54XX_GPIO3_BASE 0x48057000
#define OMAP54XX_GPIO4_BASE 0x48059000
#define OMAP54XX_GPIO5_BASE 0x4805B000
#define OMAP54XX_GPIO6_BASE 0x4805D000
#endif /* _GPIO_OMAP5_H */

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/*
* (C) Copyright 2004-2010
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_
#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
unsigned short revnb_lo; /* 0x00 */
unsigned short res1;
unsigned short revnb_hi; /* 0x04 */
unsigned short res2[13];
unsigned short sysc; /* 0x20 */
unsigned short res3;
unsigned short irqstatus_raw; /* 0x24 */
unsigned short res4;
unsigned short stat; /* 0x28 */
unsigned short res5;
unsigned short ie; /* 0x2C */
unsigned short res6;
unsigned short irqenable_clr; /* 0x30 */
unsigned short res7;
unsigned short iv; /* 0x34 */
unsigned short res8[45];
unsigned short syss; /* 0x90 */
unsigned short res9;
unsigned short buf; /* 0x94 */
unsigned short res10;
unsigned short cnt; /* 0x98 */
unsigned short res11;
unsigned short data; /* 0x9C */
unsigned short res13;
unsigned short res14; /* 0xA0 */
unsigned short res15;
unsigned short con; /* 0xA4 */
unsigned short res16;
unsigned short oa; /* 0xA8 */
unsigned short res17;
unsigned short sa; /* 0xAC */
unsigned short res18;
unsigned short psc; /* 0xB0 */
unsigned short res19;
unsigned short scll; /* 0xB4 */
unsigned short res20;
unsigned short sclh; /* 0xB8 */
unsigned short res21;
unsigned short systest; /* 0xBC */
unsigned short res22;
unsigned short bufstat; /* 0xC0 */
unsigned short res23;
};
#endif /* _OMAP5_I2C_H_ */

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/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x4809C100
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
};
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define DATI_CMDDIS (0x1 << 1)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
int omap_mmc_init(int dev_index);
#endif /* MMC_HOST_DEF_H */

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/*
* (C) Copyright 2004-2009
* Texas Instruments Incorporated
* Richard Woodruff <r-woodruff2@ti.com>
* Aneesh V <aneesh@ti.com>
* Balaji Krishnamoorthy <balajitk@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MUX_OMAP5_H_
#define _MUX_OMAP5_H_
#include <asm/types.h>
struct pad_conf_entry {
u16 offset;
u16 val;
} __attribute__ ((__packed__));
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (2 << 10)
#define OFF_IN (1 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (1 << 9)
#else
#define OFF_PD (0 << 12)
#define OFF_PU (0 << 12)
#define OFF_OUT_PTD (0 << 10)
#define OFF_OUT_PTU (0 << 10)
#define OFF_IN (0 << 10)
#define OFF_OUT (0 << 10)
#define OFF_EN (0 << 9)
#endif
#define IEN (1 << 8)
#define IDIS (0 << 8)
#define PTU (3 << 3)
#define PTD (1 << 3)
#define EN (1 << 3)
#define DIS (0 << 3)
#define M0 0
#define M1 1
#define M2 2
#define M3 3
#define M4 4
#define M5 5
#define M6 6
#define M7 7
#define SAFE_MODE M7
#ifdef CONFIG_OFF_PADCONF
#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
#else
#define OFF_IN_PD 0
#define OFF_IN_PU 0
#define OFF_OUT_PD 0
#define OFF_OUT_PU 0
#endif
#define CORE_REVISION 0x0000
#define CORE_HWINFO 0x0004
#define CORE_SYSCONFIG 0x0010
#define GPMC_AD0 0x0040
#define GPMC_AD1 0x0042
#define GPMC_AD2 0x0044
#define GPMC_AD3 0x0046
#define GPMC_AD4 0x0048
#define GPMC_AD5 0x004A
#define GPMC_AD6 0x004C
#define GPMC_AD7 0x004E
#define GPMC_AD8 0x0050
#define GPMC_AD9 0x0052
#define GPMC_AD10 0x0054
#define GPMC_AD11 0x0056
#define GPMC_AD12 0x0058
#define GPMC_AD13 0x005A
#define GPMC_AD14 0x005C
#define GPMC_AD15 0x005E
#define GPMC_A16 0x0060
#define GPMC_A17 0x0062
#define GPMC_A18 0x0064
#define GPMC_A19 0x0066
#define GPMC_A20 0x0068
#define GPMC_A21 0x006A
#define GPMC_A22 0x006C
#define GPMC_A23 0x006E
#define GPMC_A24 0x0070
#define GPMC_A25 0x0072
#define GPMC_NCS0 0x0074
#define GPMC_NCS1 0x0076
#define GPMC_NCS2 0x0078
#define GPMC_NCS3 0x007A
#define GPMC_NWP 0x007C
#define GPMC_CLK 0x007E
#define GPMC_NADV_ALE 0x0080
#define GPMC_NOE 0x0082
#define GPMC_NWE 0x0084
#define GPMC_NBE0_CLE 0x0086
#define GPMC_NBE1 0x0088
#define GPMC_WAIT0 0x008A
#define GPMC_WAIT1 0x008C
#define C2C_DATA11 0x008E
#define C2C_DATA12 0x0090
#define C2C_DATA13 0x0092
#define C2C_DATA14 0x0094
#define C2C_DATA15 0x0096
#define HDMI_HPD 0x0098
#define HDMI_CEC 0x009A
#define HDMI_DDC_SCL 0x009C
#define HDMI_DDC_SDA 0x009E
#define CSI21_DX0 0x00A0
#define CSI21_DY0 0x00A2
#define CSI21_DX1 0x00A4
#define CSI21_DY1 0x00A6
#define CSI21_DX2 0x00A8
#define CSI21_DY2 0x00AA
#define CSI21_DX3 0x00AC
#define CSI21_DY3 0x00AE
#define CSI21_DX4 0x00B0
#define CSI21_DY4 0x00B2
#define CSI22_DX0 0x00B4
#define CSI22_DY0 0x00B6
#define CSI22_DX1 0x00B8
#define CSI22_DY1 0x00BA
#define CAM_SHUTTER 0x00BC
#define CAM_STROBE 0x00BE
#define CAM_GLOBALRESET 0x00C0
#define USBB1_ULPITLL_CLK 0x00C2
#define USBB1_ULPITLL_STP 0x00C4
#define USBB1_ULPITLL_DIR 0x00C6
#define USBB1_ULPITLL_NXT 0x00C8
#define USBB1_ULPITLL_DAT0 0x00CA
#define USBB1_ULPITLL_DAT1 0x00CC
#define USBB1_ULPITLL_DAT2 0x00CE
#define USBB1_ULPITLL_DAT3 0x00D0
#define USBB1_ULPITLL_DAT4 0x00D2
#define USBB1_ULPITLL_DAT5 0x00D4
#define USBB1_ULPITLL_DAT6 0x00D6
#define USBB1_ULPITLL_DAT7 0x00D8
#define USBB1_HSIC_DATA 0x00DA
#define USBB1_HSIC_STROBE 0x00DC
#define USBC1_ICUSB_DP 0x00DE
#define USBC1_ICUSB_DM 0x00E0
#define SDMMC1_CLK 0x00E2
#define SDMMC1_CMD 0x00E4
#define SDMMC1_DAT0 0x00E6
#define SDMMC1_DAT1 0x00E8
#define SDMMC1_DAT2 0x00EA
#define SDMMC1_DAT3 0x00EC
#define SDMMC1_DAT4 0x00EE
#define SDMMC1_DAT5 0x00F0
#define SDMMC1_DAT6 0x00F2
#define SDMMC1_DAT7 0x00F4
#define ABE_MCBSP2_CLKX 0x00F6
#define ABE_MCBSP2_DR 0x00F8
#define ABE_MCBSP2_DX 0x00FA
#define ABE_MCBSP2_FSX 0x00FC
#define ABE_MCBSP1_CLKX 0x00FE
#define ABE_MCBSP1_DR 0x0100
#define ABE_MCBSP1_DX 0x0102
#define ABE_MCBSP1_FSX 0x0104
#define ABE_PDM_UL_DATA 0x0106
#define ABE_PDM_DL_DATA 0x0108
#define ABE_PDM_FRAME 0x010A
#define ABE_PDM_LB_CLK 0x010C
#define ABE_CLKS 0x010E
#define ABE_DMIC_CLK1 0x0110
#define ABE_DMIC_DIN1 0x0112
#define ABE_DMIC_DIN2 0x0114
#define ABE_DMIC_DIN3 0x0116
#define UART2_CTS 0x0118
#define UART2_RTS 0x011A
#define UART2_RX 0x011C
#define UART2_TX 0x011E
#define HDQ_SIO 0x0120
#define I2C1_SCL 0x0122
#define I2C1_SDA 0x0124
#define I2C2_SCL 0x0126
#define I2C2_SDA 0x0128
#define I2C3_SCL 0x012A
#define I2C3_SDA 0x012C
#define I2C4_SCL 0x012E
#define I2C4_SDA 0x0130
#define MCSPI1_CLK 0x0132
#define MCSPI1_SOMI 0x0134
#define MCSPI1_SIMO 0x0136
#define MCSPI1_CS0 0x0138
#define MCSPI1_CS1 0x013A
#define MCSPI1_CS2 0x013C
#define MCSPI1_CS3 0x013E
#define UART3_CTS_RCTX 0x0140
#define UART3_RTS_SD 0x0142
#define UART3_RX_IRRX 0x0144
#define UART3_TX_IRTX 0x0146
#define SDMMC5_CLK 0x0148
#define SDMMC5_CMD 0x014A
#define SDMMC5_DAT0 0x014C
#define SDMMC5_DAT1 0x014E
#define SDMMC5_DAT2 0x0150
#define SDMMC5_DAT3 0x0152
#define MCSPI4_CLK 0x0154
#define MCSPI4_SIMO 0x0156
#define MCSPI4_SOMI 0x0158
#define MCSPI4_CS0 0x015A
#define UART4_RX 0x015C
#define UART4_TX 0x015E
#define USBB2_ULPITLL_CLK 0x0160
#define USBB2_ULPITLL_STP 0x0162
#define USBB2_ULPITLL_DIR 0x0164
#define USBB2_ULPITLL_NXT 0x0166
#define USBB2_ULPITLL_DAT0 0x0168
#define USBB2_ULPITLL_DAT1 0x016A
#define USBB2_ULPITLL_DAT2 0x016C
#define USBB2_ULPITLL_DAT3 0x016E
#define USBB2_ULPITLL_DAT4 0x0170
#define USBB2_ULPITLL_DAT5 0x0172
#define USBB2_ULPITLL_DAT6 0x0174
#define USBB2_ULPITLL_DAT7 0x0176
#define USBB2_HSIC_DATA 0x0178
#define USBB2_HSIC_STROBE 0x017A
#define UNIPRO_TX0 0x017C
#define UNIPRO_TY0 0x017E
#define UNIPRO_TX1 0x0180
#define UNIPRO_TY1 0x0182
#define UNIPRO_TX2 0x0184
#define UNIPRO_TY2 0x0186
#define UNIPRO_RX0 0x0188
#define UNIPRO_RY0 0x018A
#define UNIPRO_RX1 0x018C
#define UNIPRO_RY1 0x018E
#define UNIPRO_RX2 0x0190
#define UNIPRO_RY2 0x0192
#define USBA0_OTG_CE 0x0194
#define USBA0_OTG_DP 0x0196
#define USBA0_OTG_DM 0x0198
#define FREF_CLK1_OUT 0x019A
#define FREF_CLK2_OUT 0x019C
#define SYS_NIRQ1 0x019E
#define SYS_NIRQ2 0x01A0
#define SYS_BOOT0 0x01A2
#define SYS_BOOT1 0x01A4
#define SYS_BOOT2 0x01A6
#define SYS_BOOT3 0x01A8
#define SYS_BOOT4 0x01AA
#define SYS_BOOT5 0x01AC
#define DPM_EMU0 0x01AE
#define DPM_EMU1 0x01B0
#define DPM_EMU2 0x01B2
#define DPM_EMU3 0x01B4
#define DPM_EMU4 0x01B6
#define DPM_EMU5 0x01B8
#define DPM_EMU6 0x01BA
#define DPM_EMU7 0x01BC
#define DPM_EMU8 0x01BE
#define DPM_EMU9 0x01C0
#define DPM_EMU10 0x01C2
#define DPM_EMU11 0x01C4
#define DPM_EMU12 0x01C6
#define DPM_EMU13 0x01C8
#define DPM_EMU14 0x01CA
#define DPM_EMU15 0x01CC
#define DPM_EMU16 0x01CE
#define DPM_EMU17 0x01D0
#define DPM_EMU18 0x01D2
#define DPM_EMU19 0x01D4
#define WAKEUPEVENT_0 0x01D8
#define WAKEUPEVENT_1 0x01DC
#define WAKEUPEVENT_2 0x01E0
#define WAKEUPEVENT_3 0x01E4
#define WAKEUPEVENT_4 0x01E8
#define WAKEUPEVENT_5 0x01EC
#define WAKEUPEVENT_6 0x01F0
#define WKUP_REVISION 0x0000
#define WKUP_HWINFO 0x0004
#define WKUP_SYSCONFIG 0x0010
#define PAD0_SIM_IO 0x0040
#define PAD1_SIM_CLK 0x0042
#define PAD0_SIM_RESET 0x0044
#define PAD1_SIM_CD 0x0046
#define PAD0_SIM_PWRCTRL 0x0048
#define PAD1_SR_SCL 0x004A
#define PAD0_SR_SDA 0x004C
#define PAD1_FREF_XTAL_IN 0x004E
#define PAD0_FREF_SLICER_IN 0x0050
#define PAD1_FREF_CLK_IOREQ 0x0052
#define PAD0_FREF_CLK0_OUT 0x0054
#define PAD1_FREF_CLK3_REQ 0x0056
#define PAD0_FREF_CLK3_OUT 0x0058
#define PAD1_FREF_CLK4_REQ 0x005A
#define PAD0_FREF_CLK4_OUT 0x005C
#define PAD1_SYS_32K 0x005E
#define PAD0_SYS_NRESPWRON 0x0060
#define PAD1_SYS_NRESWARM 0x0062
#define PAD0_SYS_PWR_REQ 0x0064
#define PAD1_SYS_PWRON_RESET 0x0066
#define PAD0_SYS_BOOT6 0x0068
#define PAD1_SYS_BOOT7 0x006A
#define PAD0_JTAG_NTRST 0x006C
#define PAD1_JTAG_TCK 0x006D
#define PAD0_JTAG_RTCK 0x0070
#define PAD1_JTAG_TMS_TMSC 0x0072
#define PAD0_JTAG_TDI 0x0074
#define PAD1_JTAG_TDO 0x0076
#define PADCONF_WAKEUPEVENT_0 0x007C
#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
#define PADCONF_MODE 0x05A8
#define CONTROL_XTAL_OSCILLATOR 0x05AC
#define CONTROL_CONTROL_I2C_2 0x0604
#define CONTROL_CONTROL_JTAG 0x0608
#define CONTROL_CONTROL_SYS 0x060C
#define CONTROL_SPARE_RW 0x0614
#define CONTROL_SPARE_R 0x0618
#define CONTROL_SPARE_R_C0 0x061C
#endif /* _MUX_OMAP5_H_ */

223
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@ -0,0 +1,223 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Authors:
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _OMAP5_H_
#define _OMAP5_H_
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
#define OMAP54XX_L4_CORE_BASE 0x4A000000
#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
#define OMAP54XX_L4_PER_BASE 0x48000000
#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
/* CONTROL */
#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
/* LPDDR2 IO regs. To be verified */
#define LPDDR2_IO_REGS_BASE 0x4A100638
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */
#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
#define PROD_ID_1_SILICON_TYPE_SHIFT 16
#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
/* General Purpose Timers */
#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
/* 32KTIMER */
#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
/* SYSTEM CONTROL MODULE */
#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
/*
* Hardware Register Details
*/
/* Watchdog Timer */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
/* GP Timer */
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/*
* PRCM
*/
/* PRM */
#define PRM_BASE 0x4AE06000
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
/* Control Module */
#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
/* LPDDR2 IO regs */
#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
#define LPDDR2IO_GR10_WD_MASK (3 << 17)
#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
#define MMC1_PWRDNZ (1 << 26)
#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
#define MMC1_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__
struct s32ktimer {
unsigned char res[0x10];
unsigned int s32k_cr; /* 0x10 */
};
struct omap4_sys_ctrl_regs {
unsigned int pad1[129];
unsigned int control_id_code; /* 0x4A002204 */
unsigned int pad11[22];
unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
unsigned int pad2[47];
unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad3[260277];
unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad4[63];
unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */
};
struct control_lpddr2io_regs {
unsigned int control_lpddr2io1_0;
unsigned int control_lpddr2io1_1;
unsigned int control_lpddr2io1_2;
unsigned int control_lpddr2io1_3;
unsigned int control_lpddr2io2_0;
unsigned int control_lpddr2io2_1;
unsigned int control_lpddr2io2_2;
unsigned int control_lpddr2io2_3;
};
#endif /* __ASSEMBLY__ */
/*
* Non-secure SRAM Addresses
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
/* Temporary SRAM stack used while low level init is done */
#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/*
* SRAM scratch space entries
*/
#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define OMAP4430_ES1_0 0x44300100
#define OMAP4430_ES2_0 0x44300200
#define OMAP4430_ES2_1 0x44300210
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
/* ROM code defines */
/* Boot device */
#define BOOT_DEVICE_MASK 0xFF
#define BOOT_DEVICE_OFFSET 0x8
#define DEV_DESC_PTR_OFFSET 0x4
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
#define RESET_REASON_OFFSET 0x9
#define CH_FLAGS_OFFSET 0xA
#define CH_FLAGS_CHSETTINGS (0x1 << 0)
#define CH_FLAGS_CHRAM (0x1 << 1)
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
#ifndef __ASSEMBLY__
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
unsigned char omap_bootdevice;
unsigned char reset_reason;
unsigned char ch_flags;
};
#endif /* __ASSEMBLY__ */
#endif

122
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/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/arch/omap.h>
#include <asm/io.h>
#include <asm/arch/clocks.h>
#include <asm/omap_common.h>
#include <asm/arch/mux_omap5.h>
#include <asm/arch/clocks.h>
struct omap_sysinfo {
char *board_string;
};
extern const struct omap_sysinfo sysinfo;
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void omap_rev_string(char *omap_rev_string);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap5_ddr_clk(void);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdram_init(void);
u32 omap_sdram_size(void);
u32 cortex_rev(void);
void init_omap_revision(void);
void do_io_settings(void);
/*
* This is used to verify if the configuration header
* was executed by Romcode prior to control of transfer
* to the bootloader. SPL is responsible for saving and
* passing this to the u-boot.
*/
extern struct omap_boot_parameters boot_params;
static inline u32 running_from_sdram(void)
{
u32 pc;
asm volatile ("mov %0, pc" : "=r" (pc));
return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
(pc < OMAP54XX_DRAM_ADDR_SPACE_END));
}
static inline u8 uboot_loaded_by_spl(void)
{
/*
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
* different contexts:
* 1. SPL running from SRAM
* 2. U-Boot running from FLASH
* 3. Non-XIP U-Boot loaded to SDRAM by SPL
* 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
*
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
#else
if (uboot_loaded_by_spl())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
else if (running_from_sdram())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
else
return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
#endif
}
static inline u32 omap_revision(void)
{
extern u32 *const omap5_revision;
return *omap5_revision;
}
#endif

111
arch/arm/include/asm/arch-pxa/pxa-regs.h
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@ -313,117 +313,6 @@ typedef void (*ExcpHndlr) (void) ;
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
/******************************************************************************/
/*
* UARTs
*/
/* Full Function UART (FFUART) */
#define FFUART FFRBR
#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
#define FFLCR 0x4010000C /* Line Control Register (read/write) */
#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
#define FFLSR 0x40100014 /* Line Status Register (read only) */
#define FFMSR 0x40100018 /* Modem Status Register (read only) */
#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Bluetooth UART (BTUART) */
#define BTUART BTRBR
#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
#define BTLCR 0x4020000C /* Line Control Register (read/write) */
#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
#define BTLSR 0x40200014 /* Line Status Register (read only) */
#define BTMSR 0x40200018 /* Modem Status Register (read only) */
#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Standard UART (STUART) */
#define STUART STRBR
#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
#define STFCR 0x40700008 /* FIFO Control Register (write only) */
#define STLCR 0x4070000C /* Line Control Register (read/write) */
#define STMCR 0x40700010 /* Modem Control Register (read/write) */
#define STLSR 0x40700014 /* Line Status Register (read only) */
#define STMSR 0x40700018 /* Reserved */
#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
#define IIR_TOD (1 << 3) /* Time Out Detected */
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1 (0)
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
#define LCR_SB (1 << 6) /* Set Break */
#define LCR_STKYP (1 << 5) /* Sticky Parity */
#define LCR_EPS (1 << 4) /* Even Parity Select */
#define LCR_PEN (1 << 3) /* Parity Enable */
#define LCR_STB (1 << 2) /* Stop Bit */
#define LCR_WLS1 (1 << 1) /* Word Length Select */
#define LCR_WLS0 (1 << 0) /* Word Length Select */
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
#define LSR_BI (1 << 4) /* Break Interrupt */
#define LSR_FE (1 << 3) /* Framing Error */
#define LSR_PE (1 << 2) /* Parity Error */
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
#define MCR_LOOP (1 << 4) /* */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
#define MCR_DTR (1 << 0) /* Data Terminal Ready */
#define MSR_DCD (1 << 7) /* Data Carrier Detect */
#define MSR_RI (1 << 6) /* Ring Indicator */
#define MSR_DSR (1 << 5) /* Data Set Ready */
#define MSR_CTS (1 << 4) /* Clear To Send */
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
/******************************************************************************/
/*
* IrSR (Infrared Selection Register)

109
arch/arm/include/asm/arch-pxa/regs-uart.h Normal file
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@ -0,0 +1,109 @@
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __REGS_UART_H__
#define __REGS_UART_H__
#define FFUART_BASE 0x40100000
#define BTUART_BASE 0x40200000
#define STUART_BASE 0x40700000
#define HWUART_BASE 0x41600000
struct pxa_uart_regs {
union {
uint32_t thr;
uint32_t rbr;
uint32_t dll;
};
union {
uint32_t ier;
uint32_t dlh;
};
union {
uint32_t fcr;
uint32_t iir;
};
uint32_t lcr;
uint32_t mcr;
uint32_t lsr;
uint32_t msr;
uint32_t spr;
uint32_t isr;
};
#define IER_DMAE (1 << 7)
#define IER_UUE (1 << 6)
#define IER_NRZE (1 << 5)
#define IER_RTIOE (1 << 4)
#define IER_MIE (1 << 3)
#define IER_RLSE (1 << 2)
#define IER_TIE (1 << 1)
#define IER_RAVIE (1 << 0)
#define IIR_FIFOES1 (1 << 7)
#define IIR_FIFOES0 (1 << 6)
#define IIR_TOD (1 << 3)
#define IIR_IID2 (1 << 2)
#define IIR_IID1 (1 << 1)
#define IIR_IP (1 << 0)
#define FCR_ITL2 (1 << 7)
#define FCR_ITL1 (1 << 6)
#define FCR_RESETTF (1 << 2)
#define FCR_RESETRF (1 << 1)
#define FCR_TRFIFOE (1 << 0)
#define FCR_ITL_1 0
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7)
#define LCR_SB (1 << 6)
#define LCR_STKYP (1 << 5)
#define LCR_EPS (1 << 4)
#define LCR_PEN (1 << 3)
#define LCR_STB (1 << 2)
#define LCR_WLS1 (1 << 1)
#define LCR_WLS0 (1 << 0)
#define LSR_FIFOE (1 << 7)
#define LSR_TEMT (1 << 6)
#define LSR_TDRQ (1 << 5)
#define LSR_BI (1 << 4)
#define LSR_FE (1 << 3)
#define LSR_PE (1 << 2)
#define LSR_OE (1 << 1)
#define LSR_DR (1 << 0)
#define MCR_LOOP (1 << 4)
#define MCR_OUT2 (1 << 3)
#define MCR_OUT1 (1 << 2)
#define MCR_RTS (1 << 1)
#define MCR_DTR (1 << 0)
#define MSR_DCD (1 << 7)
#define MSR_RI (1 << 6)
#define MSR_DSR (1 << 5)
#define MSR_CTS (1 << 4)
#define MSR_DDCD (1 << 3)
#define MSR_TERI (1 << 2)
#define MSR_DDSR (1 << 1)
#define MSR_DCTS (1 << 0)
#endif /* __REGS_UART_H__ */

3
arch/arm/include/asm/armv7.h
View File

@ -31,6 +31,9 @@
#define MIDR_CORTEX_A9_R1P3 0x411FC093
#define MIDR_CORTEX_A9_R2P10 0x412FC09A
/* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
#define CCSIDR_LINE_SIZE_MASK 0x7

1035
arch/arm/include/asm/emif.h Normal file
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File diff suppressed because it is too large Load Diff

13
arch/arm/include/asm/mach-types.h
View File

@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_THALES_ADC 3492
#define MACH_TYPE_UBISYS_P9D_EVP 3493
#define MACH_TYPE_ATDGP318 3494
#define MACH_TYPE_OMAP5_SEVM 3777
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@ -14209,6 +14210,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_atdgp318() (0)
#endif
#ifdef CONFIG_MACH_OMAP5_SEVM
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_OMAP5_SEVM
# endif
# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM)
#else
# define machine_is_omap5_sevm() (0)
#endif
/*
* These have not yet been registered
*/

31
arch/arm/include/asm/omap_common.h
View File

@ -37,7 +37,16 @@
void preloader_console_init(void);
/* Boot device */
#ifdef CONFIG_OMAP44XX /* OMAP4 */
#ifdef CONFIG_OMAP54XX
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
#define BOOT_DEVICE_ONE_NAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC3 7
#elif defined(CONFIG_OMAP44XX) /* OMAP4 */
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
@ -71,10 +80,10 @@ struct spl_image_info {
extern struct spl_image_info spl_image;
extern u32* boot_params_ptr;
u32 omap_boot_device(void);
u32 omap_boot_mode(void);
/* SPL common function s*/
void spl_parse_image_header(const struct image_header *header);
void omap_rev_string(char *omap_rev_string);
@ -85,4 +94,22 @@ void spl_nand_load_image(void);
/* MMC SPL functions */
void spl_mmc_load_image(void);
/*
* silicon revisions.
* Moving this to common, so that most of code can be moved to common,
* directories.
*/
/* omap4 */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define OMAP4430_ES1_0 0x44300100
#define OMAP4430_ES2_0 0x44300200
#define OMAP4430_ES2_1 0x44300210
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
#endif /* _OMAP_COMMON_H_ */

62
board/armltd/integrator/arm-ebi.h Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright 2011
* Linaro
* Linus Walleij <linus.walleij@linaro.org>
* Register definitions for the External Bus Interface (EBI)
* found in the ARM Integrator AP and CP reference designs
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ARM_EBI_H
#define __ARM_EBI_H
#define EBI_BASE 0x12000000
#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
/*
* The four upper bits are the waitstates for each chip select
* 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
*/
#define EBI_CSR_WAIT_MASK 0xF0
/* Whether memory is synchronous or asynchronous */
#define EBI_CSR_SYNC_MASK 0xF7
#define EBI_CSR_ASYNC 0x00
#define EBI_CSR_SYNC 0x08
/* Whether memory is write enabled or not */
#define EBI_CSR_WREN_MASK 0xFB
#define EBI_CSR_WREN_DISABLE 0x00
#define EBI_CSR_WREN_ENABLE 0x04
/* Memory bit width for each chip select */
#define EBI_CSR_MEMSIZE_MASK 0xFC
#define EBI_CSR_MEMSIZE_8BIT 0x00
#define EBI_CSR_MEMSIZE_16BIT 0x01
#define EBI_CSR_MEMSIZE_32BIT 0x02
/*
* The lock register need to be written with 0xa05f before anything in the
* EBI can be changed.
*/
#define EBI_LOCK_REG 0x20
#define EBI_UNLOCK_MAGIC 0xA05F
#endif

5
board/armltd/integrator/config.mk
View File

@ -1,5 +0,0 @@
#
# image should be loaded at 0x01000000
#
CONFIG_SYS_TEXT_BASE = 0x01000000

91
board/armltd/integrator/integrator-sc.h Normal file
View File

@ -0,0 +1,91 @@
/*
* (C) Copyright 2011
* Linaro
* Linus Walleij <linus.walleij@linaro.org>
* Register definitions for the System Controller (SC) and
* the similar "CP Controller" found in the ARM Integrator/AP and
* Integrator/CP reference designs
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ARM_SC_H
#define __ARM_SC_H
#define SC_BASE 0x11000000
/*
* The system controller registers
*/
#define SC_ID_OFFSET 0x00
#define SC_OSC_OFFSET 0x04
/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
#define SC_OSC_DIVXY (1 << 8)
#define SC_CTRLS_OFFSET 0x08
#define SC_CTRLC_OFFSET 0x0C
/* Set bits by writing CTRLS, clear bits by writing CTRLC */
#define SC_CTRL_SOFTRESET (1 << 0)
#define SC_CTRL_FLASHVPP (1 << 1)
#define SC_CTRL_FLASHWP (1 << 2)
#define SC_CTRL_UART1DTR (1 << 4)
#define SC_CTRL_UART1RTS (1 << 5)
#define SC_CTRL_UART0DTR (1 << 6)
#define SC_CTRL_UART0RTS (1 << 7)
#define SC_DEC_OFFSET 0x10
#define SC_ARB_OFFSET 0x14
#define SC_PCI_OFFSET 0x18
#define SC_PCI_PCIEN (1 << 0)
#define SC_PCI_PCIBINT_CLR (1 << 1)
#define SC_LOCK_OFFSET 0x1C
#define SC_LBFADDR_OFFSET 0x20
#define SC_LBFCODE_OFFSET 0x24
#define SC_ID (SC_BASE + SC_ID_OFFSET)
#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
/*
* The Integrator/CP as a smaller set of registers, at a different
* offset - probably not to disturb old software.
*/
#define CP_BASE 0xCB000000
#define CP_IDFIELD_OFFSET 0x00
#define CP_FLASHPROG_OFFSET 0x04
#define CP_FLASHPROG_FLVPPEN (1 << 0)
#define CP_FLASHPROG_FLWREN (1 << 1)
#define CP_FLASHPROG_FLASHSIZE (1 << 2)
#define CP_FLASHPROG_EXTRABANK (1 << 3)
#define CP_INTREG_OFFSET 0x08
#define CP_DECODE_OFFSET 0x0C
#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
#endif

63
board/armltd/integrator/integrator.c
View File

@ -35,6 +35,9 @@
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include "arm-ebi.h"
#include "integrator-sc.h"
DECLARE_GLOBAL_DATA_PTR;
@ -55,6 +58,8 @@ void show_boot_progress(int progress)
int board_init (void)
{
u32 val;
/* arch number of Integrator Board */
#ifdef CONFIG_ARCH_CINTEGRATOR
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
@ -72,6 +77,37 @@ extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
#ifdef CONFIG_ARCH_CINTEGRATOR
/*
* Flash protection on the Integrator/CP is in a simple register
*/
val = readl(CP_FLASHPROG);
val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
writel(val, CP_FLASHPROG);
#else
/*
* The Integrator/AP has some special protection mechanisms
* for the external memories, first the External Bus Interface (EBI)
* then the system controller (SC).
*
* The system comes up with the flash memory non-writable and
* configuration locked. If we want U-Boot to be used for flash
* access we cannot have the flash memory locked.
*/
writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
val = readl(EBI_BASE + EBI_CSR1_REG);
val &= EBI_CSR_WREN_MASK;
val |= EBI_CSR_WREN_ENABLE;
writel(val, EBI_BASE + EBI_CSR1_REG);
writel(0, EBI_BASE + EBI_LOCK_REG);
/*
* Set up the system controller to remove write protection from
* the flash memory and enable Vpp
*/
writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
#endif
icache_enable ();
return 0;
@ -86,21 +122,30 @@ int misc_init_r (void)
return (0);
}
/*
* The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
* from there, which means we cannot test the RAM underneath the ROM at this
* point. It will be unmapped later on, when we are executing from the
* relocated in RAM U-Boot. We simply assume that this RAM is usable if the
* RAM on higher addresses works fine.
*/
#define REMAPPED_FLASH_SZ 0x40000
int dram_init (void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
unsigned long cm_reg_sdram;
unsigned long sdram_shift;
u32 cm_reg_sdram;
u32 sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
@ -110,16 +155,18 @@ extern void dram_query(void);
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
/* We only have one bank of RAM, set it to whatever was detected */
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}

166
board/csb226/csb226.c
View File

@ -1,166 +0,0 @@
/*
* (C) Copyright 2002
* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
* Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
* Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
/**
* misc_init_r: - misc initialisation routines
*/
int misc_init_r(void)
{
#if 0
uchar *str;
/* determine if the software update key is pressed during startup */
/* not ported yet... */
if (GPLR0 & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
printf("using bootcmd_update (sw-update button pressed)\n");
str = getenv("bootcmd_update");
}
setenv("bootcmd",str);
#endif
return 0;
}
/**
* board_init: - setup some data structures
*
* @return: 0 in case of success
*/
int board_init (void)
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of CSB226 board */
gd->bd->bi_arch_number = MACH_TYPE_CSB226;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
/**
* csb226_set_led: - switch LEDs on or off
*
* @param led: LED to switch (0,1,2)
* @param state: switch on (1) or off (0)
*/
void csb226_set_led(int led, int state)
{
switch(led) {
case 0: if (state==1) {
writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}
return;
}
/**
* show_boot_progress: - indicate state of the boot process
*
* @param status: Status number - see README for details.
*
* The CSB226 does only have 3 LEDs, so we switch them on at the most
* important states (1, 5, 15).
*/
void show_boot_progress (int status)
{
switch(status) {
case 1: csb226_set_led(0,1); break;
case 5: csb226_set_led(1,1); break;
case 15: csb226_set_led(2,1); break;
}
return;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_CS8900
rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
#endif
return rc;
}
#endif

368
board/csb226/flash.c
View File

@ -1,368 +0,0 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
*
* (C) Copyright 2003 (2 x 16 bit Flash bank patches)
* Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
#define FLASH_BANK_SIZE 0x02000000
#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/**
* flash_init: - initialize data structures for flash chips
*
* @return: size of the flash
*/
ulong flash_init(void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(INTEL_MANUFACT & FLASH_VENDMASK) |
(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
switch (i) {
case 0:
flashbase = PHYS_FLASH_1;
break;
default:
panic("configured too many flash banks!\n");
break;
}
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
}
size += flash_info[i].size;
}
/* Protect monitor and environment sectors */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
&flash_info[0]);
return size;
}
/**
* flash_print_info: - print information about the flash situation
*/
void flash_print_info (flash_info_t *info)
{
int i, j;
for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
switch (info->flash_id & FLASH_VENDMASK) {
case (INTEL_MANUFACT & FLASH_VENDMASK):
printf ("Intel: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
printf("28F128J3 (128Mbit)\n");
break;
default:
printf("Unknown Chip Type\n");
return;
}
printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
info++;
}
}
/**
* flash_erase: - erase flash sectors
*/
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
int rc = ERR_OK;
ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) prot++;
}
if (prot) return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
u32 * volatile addr = (u32 * volatile)(info->start[sect]);
/* erase sector: */
/* The strata flashs are aligned side by side on */
/* the data bus, so we have to write the commands */
/* to both chips here: */
*addr = 0x00200020; /* erase setup */
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase*/
*addr = 0x00FF00FF; /* read mode */
rc = ERR_TIMOUT;
goto outahere;
}
}
*addr = 0x00500050; /* clear status register cmd. */
*addr = 0x00FF00FF; /* reset to read mode */
}
printf("ok.\n");
}
if (ctrlc()) printf("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked(10000);
if (flag) enable_interrupts();
return rc;
}
/**
* write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
*/
static int write_long (flash_info_t *info, ulong dest, ulong data)
{
u32 * volatile addr = (u32 * volatile)dest, val;
int rc = ERR_OK;
int flag;
ulong start;
/* read array command - just for the case... */
*addr = 0x00FF00FF;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
flag = disable_interrupts();
/* clear status register command */
*addr = 0x00500050;
/* program set-up command */
*addr = 0x00400040;
/* latch address/data */
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait while polling the status register */
while(((val = *addr) & 0x00800080) != 0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0x00B000B0;
goto outahere;
}
}
/* check for errors */
if(val & 0x001A001A) {
printf("\nFlash write error %02x at address %08lx\n",
(int)val, (unsigned long)dest);
if(val & 0x00080008) {
printf("Voltage range error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
if(val & 0x00020002) {
printf("Device protect error.\n");
rc = ERR_PROTECTED;
goto outahere;
}
if(val & 0x00100010) {
printf("Programming error.\n");
rc = ERR_PROG_ERROR;
goto outahere;
}
rc = ERR_PROG_ERROR;
goto outahere;
}
outahere:
/* read array command */
*addr = 0x00FF00FF;
if (flag) enable_interrupts();
return rc;
}
/**
* write_buf: - Copy memory to flash.
*
* @param info:
* @param src: source of copy transaction
* @param addr: where to copy to
* @param cnt: number of bytes to copy
*
* @return error code
*/
/* "long" version, uses 32bit words */
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
ulong data;
int l;
int i, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 24);
}
for (; i<4 && cnt>0; ++i) {
data = (data >> 8) | (*src++ << 24);
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 24);
}
if ((rc = write_long(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = *((ulong*)src);
if ((rc = write_long(info, wp, data)) != 0) {
return (rc);
}
src += 4;
wp += 4;
cnt -= 4;
}
if (cnt == 0) return ERR_OK;
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 24);
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data >> 8) | (*(uchar *)cp << 24);
}
return write_long(info, wp, data);
}

2
board/davedenx/qong/qong.c
View File

@ -231,7 +231,7 @@ static void board_nand_setup(void)
mxc_setup_weimcs(3, &cs3);
__REG(IOMUXC_GPR) |= 1 << 13;
mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));

20
board/davinci/dm6467evm/dm6467evm.c
View File

@ -24,6 +24,26 @@
DECLARE_GLOBAL_DATA_PTR;
#define REV_DM6467EVM 0
#define REV_DM6467TEVM 1
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
* bit[0-3] System clock frequency
* 0000b - 27 MHz
* 0001b - 33 MHz
*/
u32 get_board_rev(void)
{
#ifdef DAVINCI_DM6467TEVM
return REV_DM6467TEVM;
#else
return REV_DM6467EVM;
#endif
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;

56
board/denx/m28evk/Makefile Normal file
View File

@ -0,0 +1,56 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
ifndef CONFIG_SPL_BUILD
COBJS := m28evk.o
endif
ifdef CONFIG_SPL_BUILD
COBJS := mem_init.o mmc_boot.o power_init.o memsize.o
endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
all: $(ALL)
ifdef CONFIG_SPL_BUILD
memsize.c:
ln -sf $(TOPDIR)/common/memsize.c $@
endif
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

48
arch/arm/cpu/armv7/omap4/sys_info.c → board/denx/m28evk/m28_init.h
View File

@ -1,10 +1,11 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Freescale i.MX28 SPL functions
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -13,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -22,32 +23,19 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#ifndef __M28_INIT_H__
#define __M28_INIT_H__
/*
* get_device_type(): tell if GP/HS/EMU/TST
*/
u32 get_device_type(void)
{
return 0;
}
void early_delay(int delay);
/*
* get_board_rev() - get board revision
*/
u32 get_board_rev(void)
{
return 0x20;
}
void mx28_power_init(void);
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
void mx28_power_wait_pswitch(void);
#else
static inline void mx28_power_wait_pswitch(void) { }
#endif
puts("CPU : OMAP4430\n");
void mx28_mem_init(void);
return 0;
}
#endif /* __M28_INIT_H__ */

216
board/denx/m28evk/m28evk.c Normal file
View File

@ -0,0 +1,216 @@
/*
* DENX M28 module
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <netdev.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Functions
*/
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
#endif
return 0;
}
int board_init(void)
{
/* Adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
#define HW_DIGCTRL_SCRATCH0 0x8001c280
#define HW_DIGCTRL_SCRATCH1 0x8001c290
int dram_init(void)
{
uint32_t sz[2];
sz[0] = readl(HW_DIGCTRL_SCRATCH0);
sz[1] = readl(HW_DIGCTRL_SCRATCH1);
if (sz[0] != sz[1]) {
printf("MX28:\n"
"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
"verify these two registers contain valid RAM size!\n");
hang();
}
gd->ram_size = sz[0];
return 0;
}
#ifdef CONFIG_CMD_MMC
static int m28_mmc_wp(int id)
{
if (id != 0) {
printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
return 1;
}
return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
}
int board_mmc_init(bd_t *bis)
{
/* Configure WP as output */
gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
return mxsmmc_initialize(bis, 0, m28_mmc_wp);
}
#endif
#ifdef CONFIG_CMD_NET
#define MII_OPMODE_STRAP_OVERRIDE 0x16
#define MII_PHY_CTRL1 0x1e
#define MII_PHY_CTRL2 0x1f
int fecmxc_mii_postcall(int phy)
{
miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
if (phy == 3)
miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
return 0;
}
int board_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
ret = cpu_eth_init(bis);
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
CLKCTRL_ENET_TIME_SEL_RMII_CLK);
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
if (ret) {
printf("FEC MXS: Unable to init FEC0\n");
return ret;
}
ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
if (ret) {
printf("FEC MXS: Unable to init FEC1\n");
return ret;
}
dev = eth_get_dev_by_name("FEC0");
if (!dev) {
printf("FEC MXS: Unable to get FEC0 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXS: Unable to register FEC0 mii postcall\n");
return ret;
}
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
printf("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
printf("FEC MXS: Unable to register FEC1 mii postcall\n");
return ret;
}
return ret;
}
#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
#define MXS_OCOTP_MAX_TIMEOUT 1000000
void imx_get_mac_from_fuse(char *mac)
{
struct mx28_ocotp_regs *ocotp_regs =
(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
uint32_t data;
memset(mac, 0, 6);
writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
MXS_OCOTP_MAX_TIMEOUT)) {
printf("MXS FEC: Can't get MAC from OCOTP\n");
return;
}
data = readl(&ocotp_regs->hw_ocotp_cust0);
mac[0] = 0x00;
mac[1] = 0x04;
mac[2] = (data >> 24) & 0xff;
mac[3] = (data >> 16) & 0xff;
mac[4] = (data >> 8) & 0xff;
mac[5] = data & 0xff;
}
#else
void imx_get_mac_from_fuse(char *mac)
{
memset(mac, 0, 6);
}
#endif
#endif

240
board/denx/m28evk/mem_init.c Normal file
View File

@ -0,0 +1,240 @@
/*
* Freescale i.MX28 RAM init
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include "m28_init.h"
uint32_t dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
};
void init_m28_200mhz_ddr2(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
void mx28_mem_init_clock(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Gate EMI clock */
writel(CLKCTRL_FRAC0_CLKGATEEMI,
&clkctrl_regs->hw_clkctrl_frac0_set);
/* EMI = 205MHz */
writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
&clkctrl_regs->hw_clkctrl_frac0_set);
writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
CLKCTRL_FRAC0_EMIFRAC_MASK,
&clkctrl_regs->hw_clkctrl_frac0_clr);
/* Ungate EMI clock */
writel(CLKCTRL_FRAC0_CLKGATEEMI,
&clkctrl_regs->hw_clkctrl_frac0_clr);
early_delay(11000);
writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
&clkctrl_regs->hw_clkctrl_emi);
/* Unbypass EMI */
writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
early_delay(10000);
}
void mx28_mem_setup_cpu_and_hbus(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* CPU = 454MHz and ungate CPU clock */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
/* Set CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* HBUS = 151MHz */
writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
&clkctrl_regs->hw_clkctrl_hbus_clr);
early_delay(10000);
/* CPU clock divider = 1 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
CLKCTRL_CPU_DIV_CPU_MASK, 1);
/* Disable CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
}
void mx28_mem_setup_vdda(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
&power_regs->hw_power_vddactrl);
}
void mx28_mem_setup_vddd(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
&power_regs->hw_power_vdddctrl);
}
#define HW_DIGCTRL_SCRATCH0 0x8001c280
#define HW_DIGCTRL_SCRATCH1 0x8001c290
void data_abort_memdetect_handler(void) __attribute__((naked));
void data_abort_memdetect_handler(void)
{
asm volatile("subs pc, r14, #4");
}
void mx28_mem_get_size(void)
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
/* Replace the DABT handler. */
da = vt[4];
vt[4] = (uint32_t)&data_abort_memdetect_handler;
sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
writel(sz, HW_DIGCTRL_SCRATCH0);
writel(sz, HW_DIGCTRL_SCRATCH1);
/* Restore the old DABT handler. */
vt[4] = da;
}
void mx28_mem_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mx28_pinctrl_regs *pinctrl_regs =
(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
/* Power up PLL0 */
writel(CLKCTRL_PLL0CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
early_delay(11000);
mx28_mem_init_clock();
mx28_mem_setup_vdda();
/*
* Configure the DRAM registers
*/
/* Clear START bit from DRAM_CTL16 */
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
init_m28_200mhz_ddr2();
/* Clear SREFRESH bit from DRAM_CTL17 */
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
/* Set START bit in DRAM_CTL16 */
setbits_le32(MXS_DRAM_BASE + 0x40, 1);
/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
mx28_mem_setup_vddd();
early_delay(10000);
mx28_mem_setup_cpu_and_hbus();
mx28_mem_get_size();
}

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/*
* Freescale i.MX28 Boot setup
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx28.h>
#include "m28_init.h"
/*
* This delay function is intended to be used only in early stage of boot, where
* clock are not set up yet. The timer used here is reset on every boot and
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
*/
#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
void early_delay(int delay)
{
uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
st += delay;
while (st > readl(HW_DIGCTRL_MICROSECONDS))
;
}
#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
const iomux_cfg_t iomux_setup[] = {
/* LED */
MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
/* framebuffer */
MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
/* UART1 */
MX28_PAD_PWM0__DUART_RX,
MX28_PAD_PWM1__DUART_TX,
MX28_PAD_AUART0_TX__DUART_RTS,
MX28_PAD_AUART0_RX__DUART_CTS,
/* UART2 */
MX28_PAD_AUART1_RX__AUART1_RX,
MX28_PAD_AUART1_TX__AUART1_TX,
MX28_PAD_AUART1_RTS__AUART1_RTS,
MX28_PAD_AUART1_CTS__AUART1_CTS,
/* CAN */
MX28_PAD_GPMI_RDY2__CAN0_TX,
MX28_PAD_GPMI_RDY3__CAN0_RX,
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
/* TSC2007 */
MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
/* MMC0 */
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
MX28_PAD_SSP0_SCK__SSP0_SCK |
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */
MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */
/* GPMI NAND */
MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RDN__GPMI_RDN |
(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
/* FEC Ethernet */
MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
/* EMI */
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
/* SPI2 (for flash) */
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};
void board_init_ll(void)
{
mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup));
mx28_power_init();
mx28_mem_init();
mx28_power_wait_pswitch();
}
/* Support aparatus */
inline void board_init_f(unsigned long bootflag)
{
for (;;)
;
}
inline void board_init_r(gd_t *id, ulong dest_addr)
{
for (;;)
;
}
inline int printf(const char *fmt, ...)
{
return 0;
}
inline void __coloured_LED_init(void) {}
inline void __red_LED_on(void) {}
void coloured_LED_init(void)
__attribute__((weak, alias("__coloured_LED_init")));
void red_LED_on(void)
__attribute__((weak, alias("__red_LED_on")));
void hang(void) __attribute__ ((noreturn));
void hang(void)
{
for (;;)
;
}

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/*
* Freescale i.MX28 Boot PMIC init
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include "m28_init.h"
void mx28_power_clock2xtal(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
void mx28_power_clock2pll(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
writel(CLKCTRL_PLL0CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
early_delay(100);
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
}
void mx28_power_clear_auto_restart(void)
{
struct mx28_rtc_regs *rtc_regs =
(struct mx28_rtc_regs *)MXS_RTC_BASE;
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
;
writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
;
/*
* Due to the hardware design bug of mx28 EVK-A
* we need to set the AUTO_RESTART bit.
*/
if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
return;
while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
;
setbits_le32(&rtc_regs->hw_rtc_persistent0,
RTC_PERSISTENT0_AUTO_RESTART);
writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
;
while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
;
}
void mx28_power_set_linreg(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
clrsetbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_LINREG_OFFSET_MASK,
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
void mx28_power_setup_5v_detect(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
void mx28_src_power_init(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
clrsetbits_le32(&power_regs->hw_power_dclimits,
POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
setbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_EN_BATADJ);
/* Increase the RCSCALE level for quick DCDC response to dynamic load */
clrsetbits_le32(&power_regs->hw_power_loopctrl,
POWER_LOOPCTRL_EN_RCSCALE_MASK,
POWER_LOOPCTRL_RCSCALE_THRESH |
POWER_LOOPCTRL_EN_RCSCALE_8X);
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
/* 5V to battery handoff ... FIXME */
setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
early_delay(30);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
void mx28_power_init_4p2_params(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_HEADROOM_ADJ_MASK,
0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_DROPOUT_CTRL_MASK,
POWER_DCDC4P2_DROPOUT_CTRL_100MV |
POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
void mx28_enable_4p2_dcdc_input(int xfer)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
POWER_CTRL_ENIRQ_VDD5V_DROOP;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
if (xfer && (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
return;
}
/*
* Recording orignal values that will be modified temporarlily
* to handle a chip bug. See chip errata for CQ ENGR00115837
*/
tmp = readl(&power_regs->hw_power_5vctrl);
vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
/*
* Disable mechanisms that get erroneously tripped by when setting
* the DCDC4P2 EN_DCDC
*/
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_5VDETECT |
POWER_5VCTRL_VBUSVALID_TRSH_MASK);
writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
if (xfer) {
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
early_delay(20);
clrbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_DCDC_XFER);
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_ENABLE_DCDC);
} else {
setbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
}
early_delay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
if (vbus_5vdetect)
writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
if (!pwd_bo)
clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
clrbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_VBUS_VALID_IRQ);
if (prev_5v_brnout) {
writel(POWER_5VCTRL_PWDN_5VBRNOUT,
&power_regs->hw_power_5vctrl_set);
writel(POWER_RESET_UNLOCK_KEY,
&power_regs->hw_power_reset);
} else {
writel(POWER_5VCTRL_PWDN_5VBRNOUT,
&power_regs->hw_power_5vctrl_clr);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
clrbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_VDD5V_DROOP_IRQ);
if (prev_5v_droop)
clrbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_ENIRQ_VDD5V_DROOP);
else
setbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
void mx28_power_init_4p2_regulator(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
&power_regs->hw_power_5vctrl_clr);
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
/* Power up the 4p2 rail and logic/control */
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
/*
* Start charging up the 4p2 capacitor. We ramp of this charge
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
mx28_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
* If we arrived here, we were unable to recover from mx23 chip
* errata 5837. 4P2 is disabled and sufficient battery power is
* not present. Exiting to not enable DCDC power during 5V
* connected state.
*/
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
hang();
}
/*
* Here we set the 4p2 brownout level to something very close to 4.2V.
* We then check the brownout status. If the brownout status is false,
* the voltage is already close to the target voltage of 4.2V so we
* can go ahead and set the 4P2 current limit to our max target limit.
* If the brownout status is true, we need to ramp us the current limit
* so that we don't cause large inrush current issues. We step up the
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
setbits_le32(&power_regs->hw_power_5vctrl,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
} else {
tmp = (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
while (tmp < 0x3f) {
if (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
early_delay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp++;
tmp2 = readl(&power_regs->hw_power_5vctrl);
tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
early_delay(100);
}
}
}
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
void mx28_power_init_dcdc_4p2_source(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
hang();
}
mx28_enable_4p2_dcdc_input(1);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_ENABLE_DCDC,
&power_regs->hw_power_5vctrl_clr);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
}
}
void mx28_power_enable_4p2(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
POWER_VDDDCTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
POWER_VDDACTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
mx28_power_init_4p2_params();
mx28_power_init_4p2_regulator();
/* Shutdown battery (none present) */
clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
mx28_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
early_delay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
* Check if FET is enabled on either powerout and if so,
* disable load.
*/
tmp = 0;
tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
POWER_VDDDCTRL_DISABLE_FET);
tmp |= !(readl(&power_regs->hw_power_vddactrl) &
POWER_VDDACTRL_DISABLE_FET);
tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
POWER_VDDIOCTRL_DISABLE_FET);
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
}
void mx28_boot_valid_5v(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
*/
writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
&power_regs->hw_power_5vctrl_set);
/* Configure polarity to check for 5V disconnection. */
writel(POWER_CTRL_POLARITY_VBUSVALID |
POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
&power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
&power_regs->hw_power_ctrl_clr);
mx28_power_enable_4p2();
}
void mx28_powerdown(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
void mx28_handle_5v_conflict(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
for (;;) {
tmp = readl(&power_regs->hw_power_sts);
if (tmp & POWER_STS_VDDIO_BO) {
mx28_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
mx28_boot_valid_5v();
break;
} else {
mx28_powerdown();
break;
}
}
}
int mx28_get_batt_volt(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
return volt;
}
int mx28_is_batt_ready(void)
{
return (mx28_get_batt_volt() >= 3600);
}
void mx28_5v_boot(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
mx28_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
mx28_boot_valid_5v();
return;
}
mx28_handle_5v_conflict();
}
void mx28_init_batt_bo(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
void mx28_switch_vddd_to_dcdc_source(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
POWER_VDDDCTRL_DISABLE_STEPPING);
}
int mx28_is_batt_good(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t volt;
volt = readl(&power_regs->hw_power_battmonitor);
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
if ((volt >= 2400) && (volt <= 4300))
return 1;
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
clrsetbits_le32(&power_regs->hw_power_charge,
POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
early_delay(500000);
volt = readl(&power_regs->hw_power_battmonitor);
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
if (volt >= 3500)
return 0;
if (volt >= 2400)
return 1;
writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
&power_regs->hw_power_charge_clr);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
return 0;
}
void mx28_power_configure_power_source(void)
{
mx28_src_power_init();
mx28_5v_boot();
mx28_power_clock2pll();
mx28_init_batt_bo();
mx28_switch_vddd_to_dcdc_source();
}
void mx28_enable_output_rail_protection(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_PWDN_BRNOUT);
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
int mx28_get_vddio_power_source_off(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
if (!(readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
}
return 0;
}
int mx28_get_vddd_power_source_off(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
if (!(readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
return 1;
}
}
if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
return 1;
}
}
return 0;
}
void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
new_brownout = new_target - new_brownout;
cur_target = readl(&power_regs->hw_power_vddioctrl);
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
powered_by_linreg = mx28_get_vddio_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vddioctrl);
clrbits_le32(&power_regs->hw_power_vddioctrl,
POWER_CTRL_ENIRQ_VDDIO_BO);
}
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
do {
if (new_target - cur_target > 100)
diff = cur_target + 100;
else
diff = new_target;
diff -= 2800;
diff /= 50;
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_TRG_MASK, diff);
if (powered_by_linreg)
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vddioctrl);
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
} while (new_target > cur_target);
if (powered_by_linreg) {
writel(POWER_CTRL_VDDIO_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_CTRL_ENIRQ_VDDIO_BO);
}
} else {
do {
if (cur_target - new_target > 100)
diff = cur_target - 100;
else
diff = new_target;
diff -= 2800;
diff /= 50;
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_TRG_MASK, diff);
if (powered_by_linreg)
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vddioctrl);
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
} while (new_target < cur_target);
}
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDDCTRL_BO_OFFSET_MASK,
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
new_brownout = new_target - new_brownout;
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
powered_by_linreg = mx28_get_vddd_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vdddctrl);
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_CTRL_ENIRQ_VDDD_BO);
}
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_BO_OFFSET_MASK);
do {
if (new_target - cur_target > 100)
diff = cur_target + 100;
else
diff = new_target;
diff -= 800;
diff /= 25;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_TRG_MASK, diff);
if (powered_by_linreg)
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
} while (new_target > cur_target);
if (powered_by_linreg) {
writel(POWER_CTRL_VDDD_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
setbits_le32(&power_regs->hw_power_vdddctrl,
POWER_CTRL_ENIRQ_VDDD_BO);
}
} else {
do {
if (cur_target - new_target > 100)
diff = cur_target - 100;
else
diff = new_target;
diff -= 800;
diff /= 25;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_TRG_MASK, diff);
if (powered_by_linreg)
early_delay(1500);
else {
while (!(readl(&power_regs->hw_power_sts) &
POWER_STS_DC_OK))
;
}
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
} while (new_target < cur_target);
}
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_BO_OFFSET_MASK,
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
void mx28_power_init(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
mx28_power_clock2xtal();
mx28_power_clear_auto_restart();
mx28_power_set_linreg();
mx28_power_setup_5v_detect();
mx28_power_configure_power_source();
mx28_enable_output_rail_protection();
mx28_power_set_vddio(3300, 3150);
mx28_power_set_vddd(1350, 1200);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
early_delay(1000);
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
void mx28_power_wait_pswitch(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
#endif

234
board/denx/m28evk/start.S Normal file
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@ -0,0 +1,234 @@
/*
* armboot - Startup Code for ARM926EJS CPU-core
*
* Copyright (c) 2003 Texas Instruments
*
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
*
* Change to support call back into iMX28 bootrom
* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <version.h>
#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#elif defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start:
b reset
b undefined_instruction
b software_interrupt
b prefetch_abort
b data_abort
b not_used
b irq
b fiq
/*
* Vector table, located at address 0x20.
* This table allows the code running AFTER SPL, the U-Boot, to install it's
* interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
* including it's interrupt vectoring table and the table at 0x0 is still the
* SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
* is still used.
*/
_vt_reset:
.word _reset
_vt_undefined_instruction:
.word _hang
_vt_software_interrupt:
.word _hang
_vt_prefetch_abort:
.word _hang
_vt_data_abort:
.word _hang
_vt_not_used:
.word _reset
_vt_irq:
.word _hang
_vt_fiq:
.word _hang
reset:
ldr pc, _vt_reset
undefined_instruction:
ldr pc, _vt_undefined_instruction
software_interrupt:
ldr pc, _vt_software_interrupt
prefetch_abort:
ldr pc, _vt_prefetch_abort
data_abort:
ldr pc, _vt_data_abort
not_used:
ldr pc, _vt_not_used
irq:
ldr pc, _vt_irq
fiq:
ldr pc, _vt_fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
.globl _end_ofs
_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
_reset:
/*
* Store all registers on old stack pointer, this will allow us later to
* return to the BootROM and let the BootROM load U-Boot into RAM.
*/
push {r0-r12,r14}
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
bl board_init_ll
pop {r0-r12,r14}
bx lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
.align 5
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
_hang:
ldr sp, _TEXT_BASE /* switch to abort stack */
1:
bl 1b /* hang and never return */

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