ARM: remove broken "ixdp425" and "ixpdg425" boards
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Albert ARIBAUD
parent
279bbbca12
commit
0ca8eb7137
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@ -786,7 +786,6 @@ John Rigby <jcrigby@gmail.com>
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Stefan Roese <sr@denx.de>
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ixdpg425 xscale/ixp
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pdnb3 xscale/ixp
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scpu xscale/ixp
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@ -894,7 +893,6 @@ Unknown / orphaned boards:
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Board CPU Last known maintainer / Comment
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.........................................................................
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cradle xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
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ixdp425 xscale/ixp Kyle Harris <kharris@nexus-tech.net> / dead address
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lubbock xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
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imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
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@ -1,50 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := ixdp425.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,238 +0,0 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include <asm/arch/ixp425pci.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */
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int board_early_init_f(void)
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{
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/* CS2: LED port */
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writel(0xbcff0002, IXP425_EXP_CS2);
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writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */
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return 0;
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}
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#ifdef CONFIG_PCI
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_ixpdp425_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{ 0x400,
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0x40000000,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{ 0x800,
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0x40010000,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{ 0xc00,
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0x40020000,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{ 0x1000,
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0x40030000,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_ixpdp425_config_table,
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#endif
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};
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#endif /* CONFIG_PCI */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */
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#ifdef CONFIG_IXDPG425
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/* arch number of IXDP */
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gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
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#else
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/* arch number of IXDP */
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gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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#ifdef CONFIG_IXDPG425
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/*
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* Get realtek RTL8305 switch and SLIC out of reset
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*/
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
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/*
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* Setup GPIOs for PCI INTA & INTB
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*/
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
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/* Setup GPIOs for 33MHz clock output */
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writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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/* set GPIO8..11 interrupt type to active low */
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writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
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/* clear pending interrupts */
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writel(-1, IXP425_GPIO_GPISR);
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/* assert PCI reset */
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N);
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udelay(533);
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/* deassert PCI reset */
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
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udelay(533);
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#else /* IXDP425 */
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/* Setup GPIOs for 33MHz ExpBus and PCI clock output */
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writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N);
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/* set GPIO8..11 interrupt type to active low */
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writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
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/* clear pending interrupts */
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writel(-1, IXP425_GPIO_GPISR);
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/* assert PCI reset */
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N);
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udelay(533);
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/* deassert PCI reset */
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N);
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udelay(533);
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#endif
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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#ifdef CONFIG_IXDPG425
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puts("Board: IXDPG425 - Intel Network Gateway Reference Platform");
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#else
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puts("Board: IXDP425 - Intel Development Platform");
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#endif
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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int dram_init(void)
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{
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/* we can only map 64MB via PCI, so we limit memory
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until a better solution is implemented. */
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#ifdef CONFIG_PCI
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20);
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#else
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20);
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#endif
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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pci_ixp_init(&hose);
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}
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/*
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* dev 0 on the PCI bus is not the host bridge, so we have to override
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* these functions in order to not skip PCI slot 0 during configuration.
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*/
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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return 0;
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}
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int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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return 1;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_PCI
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pci_eth_init(bis);
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#endif
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return cpu_eth_init(bis);
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}
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@ -194,8 +194,6 @@ actux2 arm ixp
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actux3 arm ixp
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actux4 arm ixp
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dvlhost arm ixp
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ixdp425 arm ixp
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ixdpg425 arm ixp ixdp425
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balloon3 arm pxa
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cerf250 arm pxa
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colibri_pxa270 arm pxa
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@ -69,3 +69,5 @@ MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz <andre.schwarz@matrix-vis
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adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
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R5200 ColdFire 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
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CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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ixdpg425 ARM xscale/ixp - 2011-09-22 Stefan Roese <sr@denx.de>
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ixdp425 ARM xscale/ixp - 2011-09-22 Kyle Harris <kharris@nexus-tech.net>
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@ -1,268 +0,0 @@
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/*
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* Configuation settings for the IXDP425 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
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#define CONFIG_IXDP425 1 /* on an IXDP425 Board */
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#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
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#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
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/*
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* select serial console configuration
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*/
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#define CONFIG_IXP_SERIAL
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Command line configuration. */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_IXP_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI_ENUM
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#define CONFIG_EEPRO100
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#endif
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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#define CONFIG_SYS_HZ 1000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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/***************************************************************
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* Platform/Board specific defines start here.
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***************************************************************/
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/*
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* Hardware drivers
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*/
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/*
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
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#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_BOARD_SIZE_LIMIT 262144
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/* Expansion bus settings */
|
||||
#define CONFIG_SYS_EXP_CS0 0xbcd23c42
|
||||
|
||||
/* SDRAM settings */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
|
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
#define CONFIG_SYS_SDR_CONFIG 0xd
|
||||
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
|
||||
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Use common CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
/* no byte writes on IXP4xx */
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
/* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
|
||||
/* Ethernet */
|
||||
|
||||
/* include IXP4xx NPE support */
|
||||
#define CONFIG_IXP4XX_NPE 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
/* NPE0 PHY address */
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
/* NPE1 PHY address (HW Release E only) */
|
||||
#define CONFIG_PHY1_ADDR 1
|
||||
/* MII PHY management */
|
||||
#define CONFIG_MII 1
|
||||
/* Number of ethernet rx buffers & descriptors */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16
|
||||
|
||||
#define CONFIG_HAS_ETH1 1
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#undef CONFIG_CMD_NFS
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"npe_ucode=50060000\0" \
|
||||
"mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \
|
||||
"kerneladdr=50080000\0" \
|
||||
"kernelfile=ixdp425/uImage\0" \
|
||||
"rootfile=ixdp425/rootfs\0" \
|
||||
"rootaddr=50280000\0" \
|
||||
"loadaddr=10000\0" \
|
||||
"updateboot_ser=mw.b 10000 ff 40000;" \
|
||||
" loady ${loadaddr};" \
|
||||
" run eraseboot writeboot\0" \
|
||||
"updateboot_net=mw.b 10000 ff 40000;" \
|
||||
" tftp ${loadaddr} ixdp425/u-boot.bin;" \
|
||||
" run eraseboot writeboot\0" \
|
||||
"eraseboot=protect off 50000000 5003ffff;" \
|
||||
" erase 50000000 5003ffff\0" \
|
||||
"writeboot=cp.b 10000 50000000 ${filesize}\0" \
|
||||
"updateucode=loady;" \
|
||||
" era ${npe_ucode} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
|
||||
"updateroot=tftp ${loadaddr} ${rootfile};" \
|
||||
" era ${rootaddr} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
|
||||
"updatekern=tftp ${loadaddr} ${kernelfile};" \
|
||||
" era ${kerneladdr} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
|
||||
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
|
||||
"boot_flash=run flashargs addtty addeth;" \
|
||||
" bootm ${kerneladdr}\0" \
|
||||
"boot_net=run netargs addtty addeth;" \
|
||||
" tftpboot ${loadaddr} ${kernelfile};" \
|
||||
" bootm\0"
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*/
|
||||
#define CONFIG_SYS_GPIO_UTOPIA_GPIO1 0
|
||||
#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N 1
|
||||
#define CONFIG_SYS_GPIO_HSS1_IRQ_N 2
|
||||
#define CONFIG_SYS_GPIO_HSS0_IRQ_N 3
|
||||
#define CONFIG_SYS_GPIO_ETH0_IRQ_N 4
|
||||
#define CONFIG_SYS_GPIO_ETH1_IRQ_N 5
|
||||
#define CONFIG_SYS_GPIO_I2C_SCL 6
|
||||
#define CONFIG_SYS_GPIO_I2C_SDA 7
|
||||
#define CONFIG_SYS_GPIO_PCI_INTD_N 8
|
||||
#define CONFIG_SYS_GPIO_PCI_INTC_N 9
|
||||
#define CONFIG_SYS_GPIO_PCI_INTB_N 10
|
||||
#define CONFIG_SYS_GPIO_PCI_INTA_N 11
|
||||
#define CONFIG_SYS_GPIO_UTOPIA_GPIO0 12
|
||||
#define CONFIG_SYS_GPIO_PCI_RESET_N 13
|
||||
#define CONFIG_SYS_GPIO_PCI_CLK 14
|
||||
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,256 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2005-2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2003
|
||||
* Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl
|
||||
*
|
||||
* Configuation settings for the IXDPG425 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
|
||||
#define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
|
||||
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
/*
|
||||
* Misc configuration options
|
||||
*/
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_IXP_SERIAL
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
|
||||
|
||||
#define CONFIG_IXP425_TIMER_CLK 66666666
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/***************************************************************
|
||||
* Platform/Board specific defines start here.
|
||||
***************************************************************/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Default configuration (environment varibles...)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=ixdpg425\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/arm\0" \
|
||||
"bootfile=/tftpboot/ixdpg425/uImage\0" \
|
||||
"kernel_addr=50080000\0" \
|
||||
"ramdisk_addr=50200000\0" \
|
||||
"load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \
|
||||
"update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \
|
||||
"cp.b 100000 50000000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
|
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x50000000
|
||||
|
||||
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
|
||||
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
|
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
|
||||
/*
|
||||
* Expansion bus settings
|
||||
*/
|
||||
#define CONFIG_SYS_EXP_CS0 0xbcd23c42
|
||||
|
||||
/*
|
||||
* SDRAM settings
|
||||
*/
|
||||
#define CONFIG_SYS_SDR_CONFIG 0x18
|
||||
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
|
||||
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*/
|
||||
#define CONFIG_SYS_GPIO_PCI_INTA_N 6
|
||||
#define CONFIG_SYS_GPIO_PCI_INTB_N 7
|
||||
#define CONFIG_SYS_GPIO_SWITCH_RESET_N 8
|
||||
#define CONFIG_SYS_GPIO_SLIC_RESET_N 13
|
||||
#define CONFIG_SYS_GPIO_PCI_CLK 14
|
||||
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue