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u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-arm 

Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2013-03-18 12:31:00 -04:00
parent b5bec88434 b27673ccbd
commit 0ce033d258
486 changed files with 15600 additions and 10419 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -44,7 +44,6 @@
/u-boot.dtb
/u-boot.sb
/u-boot.geany
/include/u-boot.lst
#
# Generated files

11
MAINTAINERS
View File

@ -606,6 +606,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
igep0020 ARM ARMV7 (OMAP3xx SoC)
igep0030 ARM ARMV7 (OMAP3xx SoC)
igep0032 ARM ARMV7 (OMAP3xx SoC)
Eric Benard <eric@eukrea.com>
@ -974,6 +975,8 @@ Tom Warren <twarren@nvidia.com>
harmony Tegra20 (ARM7 & A9 Dual Core)
seaboard Tegra20 (ARM7 & A9 Dual Core)
cardhu Tegra30 (ARM7 & A9 Quad Core)
dalmore Tegra114 (ARM7 & A15 Quad Core)
Tom Warren <twarren@nvidia.com>
Stephen Warren <swarren@nvidia.com>
@ -1035,6 +1038,14 @@ Pali Rohár <pali.rohar@gmail.com>
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
Eric Nelson <eric.nelson@boundarydevices.com>
nitrogen6dl i.MX6DL 1GB
nitrogen6dl2g i.MX6DL 2GB
nitrogen6q i.MX6Q/6D 1GB
nitrogen6q2g i.MX6Q/6D 2GB
nitrogen6s i.MX6S 512MB
nitrogen6s1g i.MX6S 1GB
-------------------------------------------------------------------------
Unknown / orphaned boards:

17
Makefile
View File

@ -464,8 +464,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
$(obj)u-boot.imx: $(obj)u-boot.bin depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@ -556,10 +556,8 @@ GEN_UBOOT = \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
$$UNDEF_LST $(__OBJS) \
$(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
@ -592,11 +590,7 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
# The following line expands into whole rule which generates u-boot.lst,
# the file containing u-boots LG-array linker section. This is included into
# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
@ -832,7 +826,6 @@ clean:
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
$(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@ -870,7 +863,7 @@ clobber: tidy
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)spl/u-boot-spl.lds
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes

29
README
View File

@ -485,6 +485,16 @@ The following options need to be configured:
Thumb2 this flag will result in Thumb2 code generated by
GCC.
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
workarounds to be applied; no CPU-type/version detection
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
@ -1533,6 +1543,17 @@ CBFS (Coreboot Filesystem) support
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
CONFIG_SPLASHIMAGE_GUARD
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
(see README.displaying-bmps and README.arm-unaligned-accesses).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
accesses (for example because your toolchain prevents them)
there is no need to set this option.
CONFIG_SPLASH_SCREEN_ALIGN
If this option is set the splash image can be freely positioned
@ -1553,6 +1574,14 @@ CBFS (Coreboot Filesystem) support
=> vertically centered image
at x = dspWidth - bmpWidth - 9
CONFIG_SPLASH_SCREEN_PREPARE
If this option is set then the board_splash_screen_prepare()
function, which must be defined in your code, is called as part
of the splash screen display sequence. It gives the board an
opportunity to prepare the splash image data before it is
processed and sent to the frame buffer by U-Boot.
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP

2
arch/arm/cpu/arm1136/mx35/generic.c
View File

@ -519,7 +519,7 @@ u32 spl_boot_device(void)
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
return BOOT_DEVICE_ONE_NAND;
return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}

37
arch/arm/cpu/arm720t/tegra114/cpu.c
View File

@ -201,6 +201,7 @@ void t114_init_clocks(void)
reset_set_enable(PERIPH_ID_MSELECT, 0);
reset_set_enable(PERIPH_ID_EMC1, 0);
reset_set_enable(PERIPH_ID_MC1, 0);
reset_set_enable(PERIPH_ID_DVFS, 0);
debug("t114_init_clocks exit\n");
}
@ -269,6 +270,8 @@ void powerup_cpus(void)
void start_cpu(u32 reset_vector)
{
u32 imme, inst;
debug("start_cpu entry, reset_vector = %x\n", reset_vector);
t114_init_clocks();
@ -285,12 +288,38 @@ void start_cpu(u32 reset_vector)
/* Take CPU(s) out of reset */
remove_cpu_resets();
/* Set the entry point for CPU execution from reset */
/*
* Set the entry point for CPU execution from reset,
* if it's a non-zero value.
* A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
* See nvbug 1193357 for details.
*/
if (reset_vector)
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
/* mov r0, #lsb(reset_vector) */
imme = reset_vector & 0xffff;
inst = imme & 0xfff;
inst |= ((imme >> 12) << 16);
inst |= 0xe3000000;
writel(inst, 0x4003fff0);
/* movt r0, #msb(reset_vector) */
imme = (reset_vector >> 16) & 0xffff;
inst = imme & 0xfff;
inst |= ((imme >> 12) << 16);
inst |= 0xe3400000;
writel(inst, 0x4003fff4);
/* bx r0 */
writel(0xe12fff10, 0x4003fff8);
/* b -12 */
imme = (u32)-20;
inst = (imme >> 2) & 0xffffff;
inst |= 0xea000000;
writel(inst, 0x4003fffc);
/* Write to orignal location for compatibility */
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
/* If the CPU(s) don't already have power, power 'em up */
powerup_cpus();

2
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
View File

@ -51,7 +51,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);

30
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
View File

@ -61,20 +61,20 @@ char *get_cpu_name()
if (cpu_is_at91sam9x5()) {
switch (extension_id) {
case ARCH_EXID_AT91SAM9G15:
return CONFIG_SYS_AT91_G15_CPU_NAME;
return "AT91SAM9G15";
case ARCH_EXID_AT91SAM9G25:
return CONFIG_SYS_AT91_G25_CPU_NAME;
return "AT91SAM9G25";
case ARCH_EXID_AT91SAM9G35:
return CONFIG_SYS_AT91_G35_CPU_NAME;
return "AT91SAM9G35";
case ARCH_EXID_AT91SAM9X25:
return CONFIG_SYS_AT91_X25_CPU_NAME;
return "AT91SAM9X25";
case ARCH_EXID_AT91SAM9X35:
return CONFIG_SYS_AT91_X35_CPU_NAME;
return "AT91SAM9X35";
default:
return CONFIG_SYS_AT91_UNKNOWN_CPU;
return "Unknown CPU type";
}
} else {
return CONFIG_SYS_AT91_UNKNOWN_CPU;
return "Unknown CPU type";
}
}
@ -246,14 +246,14 @@ void at91_macb_hw_init(void)
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}

2
arch/arm/cpu/arm926ejs/config.mk
View File

@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(OBJTREE)/u-boot.imx
ALL-y += $(obj)u-boot.imx
endif

3
arch/arm/cpu/arm926ejs/mxs/clock.c
View File

@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mxs_get_sspclk(bus);
const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
const uint32_t sspclk = mxs_get_sspclk(clk);
uint32_t reg;
uint32_t divide, rate, tgtclk;

2
arch/arm/cpu/arm926ejs/mxs/mxs_init.h
View File

@ -30,7 +30,7 @@ void early_delay(int delay);
void mxs_power_init(void);
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void);
#else
static inline void mxs_power_wait_pswitch(void) { }

16
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View File

@ -27,6 +27,7 @@
#include <config.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@ -119,6 +120,10 @@ static void initialize_dram_values(void)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
#ifdef CONFIG_MX23
/*
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
* element to be set
*/
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
#endif
}
@ -229,7 +234,7 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_ILIMIT |
POWER_VDDMEMCTRL_ENABLE_LINREG |
POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
@ -237,13 +242,20 @@ static void mx23_mem_setup_vddmem(void)
early_delay(10000);
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_LINREG,
&power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
{
/*
* Reset/ungate the EMI block. This is essential, otherwise the system
* suffers from memory instability. This thing is mx23 specific and is
* no longer present on mx28.
*/
mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
mx23_mem_setup_vddmem();
/*

2
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -921,7 +921,7 @@ void mxs_power_init(void)
early_delay(1000);
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void)
{
struct mxs_power_regs *power_regs =

39
arch/arm/cpu/arm926ejs/mxs/timer.c
View File

@ -32,7 +32,11 @@
#include <asm/arch/sys_proto.h>
/* Maximum fixed count */
#define TIMER_LOAD_VAL 0xffffffff
#if defined(CONFIG_MX23)
#define TIMER_LOAD_VAL 0xffff
#elif defined(CONFIG_MX28)
#define TIMER_LOAD_VAL 0xffffffff
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -42,22 +46,22 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* This driver uses 1kHz clock source.
*/
#define MX28_INCREMENTER_HZ 1000
#define MXS_INCREMENTER_HZ 1000
static inline unsigned long tick_to_time(unsigned long tick)
{
return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
static inline unsigned long time_to_tick(unsigned long time)
{
return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
/* Calculate how many ticks happen in "us" microseconds */
static inline unsigned long us_to_tick(unsigned long us)
{
return (us * MX28_INCREMENTER_HZ) / 1000000;
return (us * MXS_INCREMENTER_HZ) / 1000000;
}
int timer_init(void)
@ -69,7 +73,11 @@ int timer_init(void)
mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */
#if defined(CONFIG_MX23)
writel(0, &timrot_regs->hw_timrot_timcount0);
#elif defined(CONFIG_MX28)
writel(0, &timrot_regs->hw_timrot_fixed_count0);
#endif
/* Set UPDATE bit and 1Khz frequency */
writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
@ -77,7 +85,11 @@ int timer_init(void)
&timrot_regs->hw_timrot_timctrl0);
/* Set fixed_count to maximal value */
#if defined(CONFIG_MX23)
writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
#elif defined(CONFIG_MX28)
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
#endif
return 0;
}
@ -86,9 +98,16 @@ unsigned long long get_ticks(void)
{
struct mxs_timrot_regs *timrot_regs =
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
uint32_t now;
/* Current tick value */
uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
#if defined(CONFIG_MX23)
/* Upper bits are the valid ones. */
now = readl(&timrot_regs->hw_timrot_timcount0) >>
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
#elif defined(CONFIG_MX28)
now = readl(&timrot_regs->hw_timrot_running_count0);
#endif
if (lastdec >= now) {
/*
@ -117,17 +136,17 @@ ulong get_timer(ulong base)
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
void __udelay(unsigned long usec)
{
uint32_t old, new, incr;
uint32_t counter = 0;
old = readl(MX28_HW_DIGCTL_MICROSECONDS);
old = readl(MXS_HW_DIGCTL_MICROSECONDS);
while (counter < usec) {
new = readl(MX28_HW_DIGCTL_MICROSECONDS);
new = readl(MXS_HW_DIGCTL_MICROSECONDS);
/* Check if the timer wrapped. */
if (new < old) {
@ -152,5 +171,5 @@ void __udelay(unsigned long usec)
ulong get_tbclk(void)
{
return MX28_INCREMENTER_HZ;
return MXS_INCREMENTER_HZ;
}

6
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
View File

@ -51,12 +51,6 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)

6
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View File

@ -51,12 +51,6 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)

2
arch/arm/cpu/armv7/Makefile
View File

@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
SOBJS += lowlevel_init.o
endif

4
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis)
{
int ret;
ret = omap_mmc_init(0, 0, 0);
ret = omap_mmc_init(0, 0, 0, -1, -1);
if (ret)
return ret;
return omap_mmc_init(1, 0, 0);
return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif

12
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -45,13 +45,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
*/
void config_sdram(const struct emif_regs *regs)
{
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
if (regs->zq_config){
if (regs->zq_config) {
/*
* A value of 0x2800 for the REF CTRL will give us
* about 570us for a delay, which will be long enough
* to configure things.
*/
writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
}
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
}
/**

67
arch/arm/cpu/armv7/am33xx/u-boot-spl.lds Normal file
View File

@ -0,0 +1,67 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} >.sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} >.sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} >.sdram
}

2
arch/arm/cpu/armv7/config.mk
View File

@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(OBJTREE)/u-boot.imx
ALL-y += $(obj)u-boot.imx
endif

1
arch/arm/cpu/armv7/mx6/Makefile
View File

@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

16
arch/arm/cpu/armv7/mx6/soc.c
View File

@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <stdbool.h>
struct scu_regs {
u32 ctrl;
@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
writel(reg, &anatop->reg_core);
}
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
}
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
return 0;
}
@ -193,3 +205,7 @@ const struct boot_mode soc_boot_modes[] = {
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
void s_init(void)
{
}

7
arch/arm/cpu/armv7/omap-common/boot-common.c
View File

@ -55,17 +55,20 @@ void spl_board_init(void)
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
}
int board_mmc_init(bd_t *bis)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
omap_mmc_init(0, 0, 0);
omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
omap_mmc_init(1, 0, 0);
omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;

312
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@ -36,6 +36,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
@ -46,9 +47,20 @@
#define puts(s)
#endif
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
20000000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
s8 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
@ -60,8 +72,15 @@ static inline u32 __get_sys_clk_index(void)
ind = OMAP_SYS_CLK_IND_38_4_MHZ;
else {
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl(&prcm->cm_sys_clksel) &
ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
/*
* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
* NUM_SYS_CLK. So considering the last 3 bits as the index
* for the dpll param array.
*/
ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@ -75,7 +94,34 @@ u32 get_sys_clk_freq(void)
return sys_clk_array[index];
}
static inline void do_bypass_dpll(u32 *const base)
void setup_post_dividers(u32 const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->m4_h11 >= 0)
writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
if (params->m5_h12 >= 0)
writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
if (params->m6_h13 >= 0)
writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
if (params->m7_h14 >= 0)
writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
if (params->h21 >= 0)
writel(params->h21, &dpll_regs->cm_div_h21_dpll);
if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
if (params->h24 >= 0)
writel(params->h24, &dpll_regs->cm_div_h24_dpll);
}
static inline void do_bypass_dpll(u32 const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
@ -85,17 +131,17 @@ static inline void do_bypass_dpll(u32 *const base)
CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_bypass(u32 *const base)
static inline void wait_for_bypass(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
LDELAY)) {
printf("Bypassing DPLL failed %p\n", base);
printf("Bypassing DPLL failed %x\n", base);
}
}
static inline void do_lock_dpll(u32 *const base)
static inline void do_lock_dpll(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
@ -104,18 +150,18 @@ static inline void do_lock_dpll(u32 *const base)
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
static inline void wait_for_lock(u32 *const base)
static inline void wait_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
&dpll_regs->cm_idlest_dpll, LDELAY)) {
printf("DPLL locking failed for %p\n", base);
printf("DPLL locking failed for %x\n", base);
hang();
}
}
inline u32 check_for_lock(u32 *const base)
inline u32 check_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
@ -123,12 +169,65 @@ inline u32 check_for_lock(u32 *const base)
return lock;
}
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->mpu[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->core[sysclk_ind];
}
const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->per[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->iva[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->usb[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &dpll_data->abe[sysclk_ind];
#else
return dpll_data->abe;
#endif
}
static const struct dpll_params *get_ddr_dpll_params
(struct dplls const *dpll_data)
{
u32 sysclk_ind = get_sys_clk_index();
if (!dpll_data->ddr)
return NULL;
return &dpll_data->ddr[sysclk_ind];
}
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!params)
return;
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
@ -183,7 +282,7 @@ u32 omap_ddr_clk(void)
omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
core_dpll_params = get_core_dpll_params();
core_dpll_params = get_core_dpll_params(*dplls_data);
debug("sys_clk %d\n ", sys_clk_khz * 1000);
@ -235,24 +334,19 @@ void configure_mpu_dpll(void)
*/
if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
params = get_mpu_dpll_params(*dplls_data);
params = get_mpu_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
@ -271,17 +365,17 @@ static void setup_usb_dpll(void)
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
params = get_usb_dpll_params();
params = get_usb_dpll_params(*dplls_data);
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
sd_div = num / den;
clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
}
#endif
@ -293,28 +387,28 @@ static void setup_dplls(void)
debug("setup_dplls\n");
/* CORE dpll */
params = get_core_dpll_params(); /* default - safest */
params = get_core_dpll_params(*dplls_data); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
if (omap_revision() != OMAP5432_ES1_0)
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
writel(temp, &prcm->cm_clksel_core);
writel(temp, (*prcm)->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
params = get_per_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
params = get_per_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
@ -324,6 +418,9 @@ static void setup_dplls(void)
#ifdef CONFIG_USB_EHCI_OMAP
setup_usb_dpll();
#endif
params = get_ddr_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
params, DPLL_LOCK, "ddr");
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@ -333,14 +430,14 @@ static void setup_non_essential_dplls(void)
const struct dpll_params *params;
/* IVA */
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
params = get_iva_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
params = get_iva_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/* Configure ABE dpll */
params = get_abe_dpll_params();
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
@ -349,64 +446,65 @@ static void setup_non_essential_dplls(void)
* We need to enable some additional options to achieve
* 196.608MHz from 32768 Hz
*/
setbits_le32(&prcm->cm_clkmode_dpll_abe,
setbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
/* Spend 4 REFCLK cycles at each stage */
clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
#endif
/* Select the right reference clk */
clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
}
#endif
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
{
u32 step;
int ret = 0;
u32 offset_code;
/* See if we can first get the GPIO if needed */
if (gpio >= 0)
ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
if (ret < 0) {
printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
gpio = -1;
}
volt_offset -= pmic->base_offset;
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (gpio >= 0)
gpio_direction_output(gpio, 0);
offset_code = (volt_offset + pmic->step - 1) / pmic->step;
step = volt_mv - TPS62361_BASE_VOLT_MV;
step /= 10;
debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
puts("Scaling voltage failed for vdd_mpu from TPS\n");
/* Pull the GPIO high to select SET1 register */
if (gpio >= 0)
gpio_direction_output(gpio, 1);
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
return offset_code + pmic->start_code;
}
void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
int ret = 0;
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
if (ret < 0) {
printf("%s: gpio %d request failed %d\n", __func__,
pmic->gpio, ret);
return;
}
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 0);
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
offset_code = get_offset_code(offset);
offset_code = get_offset_code(offset, pmic);
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
@ -414,16 +512,46 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
}
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(struct vcores_data const *vcores)
{
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
do_scale_vcore(vcores->core.addr, vcores->core.value,
vcores->core.pmic);
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
vcores->mpu.pmic);
do_scale_vcore(vcores->mm.addr, vcores->mm.value,
vcores->mm.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, (*prcm)->prm_sldo_core_setup);
writel(2, (*prcm)->prm_sldo_mpu_setup);
writel(2, (*prcm)->prm_sldo_mm_setup);
}
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
debug("Enable clock domain - %p\n", clkctrl_reg);
debug("Enable clock domain - %x\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
static inline void wait_for_clk_enable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
u32 bound = LDELAY;
@ -435,19 +563,19 @@ static inline void wait_for_clk_enable(u32 *clkctrl_addr)
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
printf("Clock enable failed for 0x%p idlest 0x%x\n",
printf("Clock enable failed for 0x%x idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
u32 wait_for_enable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
debug("Enable clock module - %p\n", clkctrl_addr);
debug("Enable clock module - %x\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
@ -458,12 +586,12 @@ void freq_update_core(void)
const struct dpll_params *core_dpll_params;
u32 omap_rev = omap_revision();
core_dpll_params = get_core_dpll_params();
core_dpll_params = get_core_dpll_params(*dplls_data);
/* Put EMIF clock domain in sw wakeup mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
@ -475,9 +603,9 @@ void freq_update_core(void)
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
writel(freq_config1, &prcm->cm_shadow_freq_config1);
writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
&prcm->cm_shadow_freq_config1, LDELAY)) {
(u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
puts("FREQ UPDATE procedure failed!!");
hang();
}
@ -489,20 +617,20 @@ void freq_update_core(void)
*/
if (omap_rev != OMAP5430_ES1_0) {
/* Put EMIF clock domain back in hw auto mode */
enable_clock_domain(&prcm->cm_memif_clkstctrl,
enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
}
}
void bypass_dpll(u32 *const base)
void bypass_dpll(u32 const base)
{
do_bypass_dpll(base);
wait_for_bypass(base);
}
void lock_dpll(u32 *const base)
void lock_dpll(u32 const base)
{
do_lock_dpll(base);
wait_for_lock(base);
@ -511,39 +639,39 @@ void lock_dpll(u32 *const base)
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable all UARTs - console will be on one of them */
clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
u8 wait_for_enable)
{
u32 i, max = 100;
@ -582,7 +710,7 @@ void prcm_init(void)
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
scale_vcores();
scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();

73
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -66,6 +66,19 @@ inline u32 emif_num(u32 base)
return 0;
}
/*
* Get SDRAM type connected to EMIF.
* Assuming similar SDRAM parts are connected to both EMIF's
* which is typically the case. So it is sufficient to get
* SDRAM type from EMIF1.
*/
u32 emif_sdram_type()
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
return (readl(&emif->emif_sdram_config) &
EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
@ -110,11 +123,13 @@ void emif_reset_phy(u32 base)
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
const struct lpddr2_mr_regs *mr_regs;
get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
@ -122,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs)
sdelay(2000);
if (omap_revision() >= OMAP5430_ES1_0)
set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
else
set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
set_mr(base, cs, mr_addr, RL_FINAL - 2);
set_mr(base, cs, mr_addr, mr_regs->mr2);
if (omap_revision() >= OMAP5430_ES1_0)
set_mr(base, cs, LPDDR2_MR3, 0x1);
if (mr_regs->mr3 > 0)
set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
@ -255,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
@ -277,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ddr3_ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ddr3_ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
}
do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
@ -1079,7 +1067,7 @@ static void do_sdram_init(u32 base)
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
if (omap_revision() != OMAP5432_ES1_0)
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
@ -1096,9 +1084,6 @@ void emif_post_init_config(u32 base)
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
if (omap_rev == OMAP5430_ES1_0)
return;
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
@ -1206,7 +1191,7 @@ void dmm_init(u32 base)
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
if (omap_revision() >= OMAP4460_ES1_0) {
if (lisa_map_regs->is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
@ -1264,7 +1249,7 @@ void dmm_init(u32 base)
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
u32 omap_rev = omap_revision();
u32 sdram_type = emif_sdram_type();
debug(">>sdram_init()\n");
@ -1275,10 +1260,10 @@ void sdram_init(void)
debug("in_sdram = %d\n", in_sdram);
if (!(in_sdram || warm_reset())) {
if (omap_rev != OMAP5432_ES1_0)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else
writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
if (!in_sdram)
@ -1298,7 +1283,7 @@ void sdram_init(void)
}
/* for the shadow registers to take effect */
if (omap_rev != OMAP5432_ES1_0)
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
freq_update_core();
/* Do some testing after the init */

23
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -32,6 +32,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@ -79,12 +81,17 @@ u32 cortex_rev(void)
void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
minor_rev);
if (soc_variant)
printf("OMAP");
else
printf("DRA");
printf("%x ES%x.%x\n", omap_variant, major_rev,
minor_rev);
}
#ifdef CONFIG_SPL_BUILD
@ -99,6 +106,10 @@ void spl_display_print(void)
}
#endif
void __weak srcomp_enable(void)
{
}
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@ -116,6 +127,8 @@ void spl_display_print(void)
void s_init(void)
{
init_omap_revision();
hw_data_init();
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
force_emif_self_refresh();
@ -123,6 +136,7 @@ void s_init(void)
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
srcomp_enable();
setup_clocks_for_console();
gd = &gdata;
@ -235,10 +249,7 @@ int checkboard(void)
*/
u32 get_device_type(void)
{
struct omap_sys_ctrl_regs *ctrl =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
return (readl(&ctrl->control_status) &
return (readl((*ctrl)->control_status) &
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}

4
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
View File

@ -48,10 +48,6 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
__image_copy_end = .;
_end = .;

11
arch/arm/cpu/armv7/omap-common/vc.c
View File

@ -81,13 +81,13 @@ void omap_vc_init(u16 speed_khz)
cycles_low -= 7;
val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
writel(val, &prcm->prm_vc_cfg_i2c_clk);
writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
/* No HS mode for now */
val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
writel(val, &prcm->prm_vc_cfg_i2c_mode);
writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
}
/**
@ -113,14 +113,15 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
writel(reg_val, &prcm->prm_vc_val_bypass);
writel(reg_val, (*prcm)->prm_vc_val_bypass);
/* Signal VC to send data */
writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
(*prcm)->prm_vc_val_bypass);
/* Wait on VC to complete transmission */
do {
reg_val = readl(&prcm->prm_vc_val_bypass) &
reg_val = readl((*prcm)->prm_vc_val_bypass) &
PRM_VC_VAL_BYPASS_VALID_BIT;
if (!reg_val)
break;

6
arch/arm/cpu/armv7/omap3/board.c
View File

@ -98,11 +98,11 @@ int board_mmc_init(bd_t *bis)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
omap_mmc_init(0, 0, 0);
omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
omap_mmc_init(1, 0, 0);
omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;
@ -110,7 +110,7 @@ int board_mmc_init(bd_t *bis)
void spl_board_init(void)
{
#ifdef CONFIG_SPL_NAND_SUPPORT
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT

3
arch/arm/cpu/armv7/omap4/Makefile
View File

@ -27,8 +27,9 @@ LIB = $(obj)lib$(SOC).o
COBJS += sdram_elpida.o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += prcm-regs.o
COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

517
arch/arm/cpu/armv7/omap4/clocks.c
View File

@ -1,517 +0,0 @@
/*
*
* Clock initialization for OMAP4
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif /* !CONFIG_SPL_BUILD */
struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
13000000, /* 13 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
};
/*
* The M & N values in the following tables are created using the
* following tool:
* tools/omap/clocks_get_m_n.c
* Please use this tool for creating the table for any new frequency.
*/
/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
{175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
{291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
void setup_post_dividers(u32 *const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->m4 >= 0)
writel(params->m4, &dpll_regs->cm_div_m4_dpll);
if (params->m5 >= 0)
writel(params->m5, &dpll_regs->cm_div_m5_dpll);
if (params->m6 >= 0)
writel(params->m6, &dpll_regs->cm_div_m6_dpll);
if (params->m7 >= 0)
writel(params->m7, &dpll_regs->cm_div_m7_dpll);
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 omap_rev, sysclk_ind;
omap_rev = omap_revision();
sysclk_ind = get_sys_clk_index();
if (omap_rev == OMAP4430_ES1_0)
return &mpu_dpll_params_1200mhz[sysclk_ind];
else if (omap_rev < OMAP4460_ES1_0)
return &mpu_dpll_params_1600mhz[sysclk_ind];
else
return &mpu_dpll_params_1400mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
switch (omap_revision()) {
case OMAP4430_ES1_0:
return &core_dpll_params_es1_1524mhz[sysclk_ind];
case OMAP4430_ES2_0:
case OMAP4430_SILICON_ID_INVALID:
/* safest */
return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
default:
return &core_dpll_params_1600mhz[sysclk_ind];
}
}
const struct dpll_params *get_per_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_1536mhz[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_1862mhz[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(void)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
return &abe_dpll_params_32k_196608khz;
#endif
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(void)
{
u32 volt, omap_rev;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
omap_rev = omap_revision();
/*
* Scale Voltage rails:
* 1. VDD_CORE
* 3. VDD_MPU
* 3. VDD_IVA
*/
if (omap_rev < OMAP4460_ES1_0) {
/*
* OMAP4430:
* VDD_CORE = TWL6030 VCORE3
* VDD_MPU = TWL6030 VCORE1
* VDD_IVA = TWL6030 VCORE2
*/
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
/*
* note on VDD_MPU:
* Setting a high voltage for Nitro mode as smart reflex is not
* enabled. We use the maximum possible value in the AVS range
* because the next higher voltage in the discrete range
* (code >= 0b111010) is way too high.
*/
volt = 1325;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
} else {
/*
* OMAP4460:
* VDD_CORE = TWL6030 VCORE1
* VDD_MPU = TPS62361
* VDD_IVA = TWL6030 VCORE2
*/
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
/* TPS62361 */
volt = 1203;
do_scale_tps62361(TPS62361_VSEL0_GPIO,
TPS62361_REG_ADDR_SET1, volt);
/* VCORE 2 - supplies vdd_iva */
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
}
}
u32 get_offset_code(u32 offset)
{
u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
if (omap_revision() == OMAP4430_ES1_0)
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
else
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
offset_code = (offset + step - 1) / step;
/* The code starts at 1 not 0 */
return ++offset_code;
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 *const clk_domains_essential[] = {
&prcm->cm_l4per_clkstctrl,
&prcm->cm_l3init_clkstctrl,
&prcm->cm_memif_clkstctrl,
&prcm->cm_l4cfg_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
/* Enable optional 48M functional clock for USB PHY */
setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
&prcm->cm_clksel_usb_60mhz,
&prcm->cm_l3init_hsusbtll_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 *const clk_domains_non_essential[] = {
&prcm->cm_mpu_m3_clkstctrl,
&prcm->cm_ivahd_clkstctrl,
&prcm->cm_dsp_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sgx_clkstctrl,
&prcm->cm1_abe_clkstctrl,
&prcm->cm_c2c_clkstctrl,
&prcm->cm_cam_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sdma_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_non_essential[] = {
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
0
};
u32 *const clk_modules_explicit_en_non_essential[] = {
&prcm->cm1_abe_aess_clkctrl,
&prcm->cm1_abe_pdm_clkctrl,
&prcm->cm1_abe_dmic_clkctrl,
&prcm->cm1_abe_mcasp_clkctrl,
&prcm->cm1_abe_mcbsp1_clkctrl,
&prcm->cm1_abe_mcbsp2_clkctrl,
&prcm->cm1_abe_mcbsp3_clkctrl,
&prcm->cm1_abe_slimbus_clkctrl,
&prcm->cm1_abe_timer5_clkctrl,
&prcm->cm1_abe_timer6_clkctrl,
&prcm->cm1_abe_timer7_clkctrl,
&prcm->cm1_abe_timer8_clkctrl,
&prcm->cm1_abe_wdt3_clkctrl,
&prcm->cm_l4per_gptimer9_clkctrl,
&prcm->cm_l4per_gptimer10_clkctrl,
&prcm->cm_l4per_gptimer11_clkctrl,
&prcm->cm_l4per_gptimer3_clkctrl,
&prcm->cm_l4per_gptimer4_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
&prcm->cm_l4per_mcbsp4_clkctrl,
&prcm->cm_l4per_mcspi2_clkctrl,
&prcm->cm_l4per_mcspi3_clkctrl,
&prcm->cm_l4per_mcspi4_clkctrl,
&prcm->cm_l4per_mmcsd3_clkctrl,
&prcm->cm_l4per_mmcsd4_clkctrl,
&prcm->cm_l4per_mmcsd5_clkctrl,
&prcm->cm_l4per_uart1_clkctrl,
&prcm->cm_l4per_uart2_clkctrl,
&prcm->cm_l4per_uart4_clkctrl,
&prcm->cm_wkup_keyboard_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_cam_iss_clkctrl,
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

491
arch/arm/cpu/armv7/omap4/hw_data.c Normal file
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@ -0,0 +1,491 @@
/*
*
* HW data initialization for OMAP4
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
/*
* The M & N values in the following tables are created using the
* following tool:
* tools/omap/clocks_get_m_n.c
* Please use this tool for creating the table for any new frequency.
*/
/*
* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
* OMAP4460 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/*
* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
* OMAP4430 OPP_TURBO frequency
*/
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/*
* dpll locked at 1200 MHz - MPU clk at 600 MHz
* OMAP4430 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4460 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4430 ES1 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OMAP4430 ES2.X OPP_NOM frequency */
static const struct dpll_params
core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
struct dplls omap4430_dplls_es1 = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_es1_1524mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4430_dplls = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap4460_dplls = {
.mpu = mpu_dpll_params_1400mhz,
.core = core_dpll_params_1600mhz,
.per = per_dpll_params_1536mhz,
.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 10 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 10 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data tps62361 = {
.base_offset = TPS62361_BASE_VOLT_MV,
.step = 10000, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
.gpio_en = 1
};
struct vcores_data omap4430_volts_es1 = {
.mpu.value = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030_4430es1,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030_4430es1,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030_4430es1,
};
struct vcores_data omap4430_volts = {
.mpu.value = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
struct vcores_data omap4460_volts = {
.mpu.value = 1203,
.mpu.addr = TPS62361_REG_ADDR_SET1,
.mpu.pmic = &tps62361,
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &tps62361,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &tps62361,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
/* Enable optional 48M functional clock for USB PHY */
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbotg_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_l3init_usbphy_clkctrl,
(*prcm)->cm_clksel_usb_60mhz,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
(*prcm)->cm_l4per_mcbsp4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
(*prcm) = &omap4_prcm;
switch (omap_rev) {
case OMAP4430_ES1_0:
*dplls_data = &omap4430_dplls_es1;
*omap_vcores = &omap4430_volts_es1;
break;
case OMAP4430_ES2_0:
case OMAP4430_ES2_1:
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
*dplls_data = &omap4430_dplls;
*omap_vcores = &omap4430_volts;
break;
case OMAP4460_ES1_0:
case OMAP4460_ES1_1:
*dplls_data = &omap4460_dplls;
*omap_vcores = &omap4460_volts;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
*ctrl = &omap4_ctrl;
}

36
arch/arm/cpu/armv7/omap4/hwinit.c
View File

@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
void do_io_settings(void)
{
u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
struct omap_sys_ctrl_regs *const ctrl =
(struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
@ -72,20 +68,20 @@ void do_io_settings(void)
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
(*ctrl)->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
/* EMIF2 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
(*ctrl)->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
@ -93,16 +89,16 @@ void do_io_settings(void)
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_iva_voltage_ctrl);
(*ctrl)->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_mpu_voltage_ctrl);
(*ctrl)->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_core_voltage_ctrl);
(*ctrl)->control_ldosram_core_voltage_ctrl);
}
/*
@ -110,11 +106,11 @@ void do_io_settings(void)
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
if (!readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
if (!readl((*ctrl)->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */

315
arch/arm/cpu/armv7/omap4/prcm-regs.c Normal file
View File

@ -0,0 +1,315 @@
/*
*
* HW regs data for OMAP4
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/omap_common.h>
struct prcm_regs const omap4_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a004100,
.cm_clksel_abe = 0x4a004108,
.cm_dll_ctrl = 0x4a004110,
.cm_clkmode_dpll_core = 0x4a004120,
.cm_idlest_dpll_core = 0x4a004124,
.cm_autoidle_dpll_core = 0x4a004128,
.cm_clksel_dpll_core = 0x4a00412c,
.cm_div_m2_dpll_core = 0x4a004130,
.cm_div_m3_dpll_core = 0x4a004134,
.cm_div_m4_dpll_core = 0x4a004138,
.cm_div_m5_dpll_core = 0x4a00413c,
.cm_div_m6_dpll_core = 0x4a004140,
.cm_div_m7_dpll_core = 0x4a004144,
.cm_ssc_deltamstep_dpll_core = 0x4a004148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
.cm_emu_override_dpll_core = 0x4a004150,
.cm_clkmode_dpll_mpu = 0x4a004160,
.cm_idlest_dpll_mpu = 0x4a004164,
.cm_autoidle_dpll_mpu = 0x4a004168,
.cm_clksel_dpll_mpu = 0x4a00416c,
.cm_div_m2_dpll_mpu = 0x4a004170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
.cm_bypclk_dpll_mpu = 0x4a00419c,
.cm_clkmode_dpll_iva = 0x4a0041a0,
.cm_idlest_dpll_iva = 0x4a0041a4,
.cm_autoidle_dpll_iva = 0x4a0041a8,
.cm_clksel_dpll_iva = 0x4a0041ac,
.cm_div_m4_dpll_iva = 0x4a0041b8,
.cm_div_m5_dpll_iva = 0x4a0041bc,
.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
.cm_bypclk_dpll_iva = 0x4a0041dc,
.cm_clkmode_dpll_abe = 0x4a0041e0,
.cm_idlest_dpll_abe = 0x4a0041e4,
.cm_autoidle_dpll_abe = 0x4a0041e8,
.cm_clksel_dpll_abe = 0x4a0041ec,
.cm_div_m2_dpll_abe = 0x4a0041f0,
.cm_div_m3_dpll_abe = 0x4a0041f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
.cm_clkmode_dpll_ddrphy = 0x4a004220,
.cm_idlest_dpll_ddrphy = 0x4a004224,
.cm_autoidle_dpll_ddrphy = 0x4a004228,
.cm_clksel_dpll_ddrphy = 0x4a00422c,
.cm_div_m2_dpll_ddrphy = 0x4a004230,
.cm_div_m4_dpll_ddrphy = 0x4a004238,
.cm_div_m5_dpll_ddrphy = 0x4a00423c,
.cm_div_m6_dpll_ddrphy = 0x4a004240,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
.cm_shadow_freq_config1 = 0x4a004260,
.cm_mpu_mpu_clkctrl = 0x4a004320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a004400,
.cm_dsp_dsp_clkctrl = 0x4a004420,
/* cm1.abe */
.cm1_abe_clkstctrl = 0x4a004500,
.cm1_abe_l4abe_clkctrl = 0x4a004520,
.cm1_abe_aess_clkctrl = 0x4a004528,
.cm1_abe_pdm_clkctrl = 0x4a004530,
.cm1_abe_dmic_clkctrl = 0x4a004538,
.cm1_abe_mcasp_clkctrl = 0x4a004540,
.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
.cm1_abe_slimbus_clkctrl = 0x4a004560,
.cm1_abe_timer5_clkctrl = 0x4a004568,
.cm1_abe_timer6_clkctrl = 0x4a004570,
.cm1_abe_timer7_clkctrl = 0x4a004578,
.cm1_abe_timer8_clkctrl = 0x4a004580,
.cm1_abe_wdt3_clkctrl = 0x4a004588,
/* cm2.ckgen */
.cm_clksel_mpu_m3_iss_root = 0x4a008100,
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_scale_fclk = 0x4a008108,
.cm_core_dvfs_perf1 = 0x4a008110,
.cm_core_dvfs_perf2 = 0x4a008114,
.cm_core_dvfs_perf3 = 0x4a008118,
.cm_core_dvfs_perf4 = 0x4a00811c,
.cm_core_dvfs_current = 0x4a008124,
.cm_iva_dvfs_perf_tesla = 0x4a008128,
.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
.cm_iva_dvfs_perf_abe = 0x4a008130,
.cm_iva_dvfs_current = 0x4a008138,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_m4_dpll_per = 0x4a008158,
.cm_div_m5_dpll_per = 0x4a00815c,
.cm_div_m6_dpll_per = 0x4a008160,
.cm_div_m7_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_emu_override_dpll_per = 0x4a008170,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_unipro = 0x4a0081c0,
.cm_idlest_dpll_unipro = 0x4a0081c4,
.cm_autoidle_dpll_unipro = 0x4a0081c8,
.cm_clksel_dpll_unipro = 0x4a0081cc,
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_memif_emif_h1_clkctrl = 0x4a008b50,
.cm_memif_emif_h2_clkctrl = 0x4a008b58,
.cm_memif_dll_h_clkctrl = 0x4a008b60,
.cm_c2c_clkstctrl = 0x4a008c00,
.cm_c2c_staticdep = 0x4a008c04,
.cm_c2c_dynamicdep = 0x4a008c08,
.cm_c2c_sad2d_clkctrl = 0x4a008c20,
.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
.cm_ivahd_clkstctrl = 0x4a008f00,
/* cm2.ivahd */
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009000,
.cm_cam_iss_clkctrl = 0x4a009020,
.cm_cam_fdif_clkctrl = 0x4a009028,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009100,
.cm_dss_dss_clkctrl = 0x4a009120,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009200,
.cm_sgx_sgx_clkctrl = 0x4a009220,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009300,
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
.cm_l3init_hsi_clkctrl = 0x4a009338,
.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
.cm_l3init_p1500_clkctrl = 0x4a009378,
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009400,
.cm_l4per_dynamicdep = 0x4a009408,
.cm_l4per_adc_clkctrl = 0x4a009420,
.cm_l4per_gptimer10_clkctrl = 0x4a009428,
.cm_l4per_gptimer11_clkctrl = 0x4a009430,
.cm_l4per_gptimer2_clkctrl = 0x4a009438,
.cm_l4per_gptimer3_clkctrl = 0x4a009440,
.cm_l4per_gptimer4_clkctrl = 0x4a009448,
.cm_l4per_gptimer9_clkctrl = 0x4a009450,
.cm_l4per_elm_clkctrl = 0x4a009458,
.cm_l4per_gpio2_clkctrl = 0x4a009460,
.cm_l4per_gpio3_clkctrl = 0x4a009468,
.cm_l4per_gpio4_clkctrl = 0x4a009470,
.cm_l4per_gpio5_clkctrl = 0x4a009478,
.cm_l4per_gpio6_clkctrl = 0x4a009480,
.cm_l4per_hdq1w_clkctrl = 0x4a009488,
.cm_l4per_hecc1_clkctrl = 0x4a009490,
.cm_l4per_hecc2_clkctrl = 0x4a009498,
.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
.cm_l4per_l4per_clkctrl = 0x4a0094c0,
.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
.cm_l4per_mgate_clkctrl = 0x4a0094e8,
.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009500,
.cm_l4per_mcspi4_clkctrl = 0x4a009508,
.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
.cm_l4per_msprohg_clkctrl = 0x4a009530,
.cm_l4per_slimbus2_clkctrl = 0x4a009538,
.cm_l4per_uart1_clkctrl = 0x4a009540,
.cm_l4per_uart2_clkctrl = 0x4a009548,
.cm_l4per_uart3_clkctrl = 0x4a009550,
.cm_l4per_uart4_clkctrl = 0x4a009558,
.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
.cm_l4per_i2c5_clkctrl = 0x4a009568,
.cm_l4sec_clkstctrl = 0x4a009580,
.cm_l4sec_staticdep = 0x4a009584,
.cm_l4sec_dynamicdep = 0x4a009588,
.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
.cm_l4sec_rng_clkctrl = 0x4a0095c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4a30610c,
.cm_sys_clksel = 0x4a306110,
.cm_wkup_clkstctrl = 0x4a307800,
.cm_wkup_l4wkup_clkctrl = 0x4a307820,
.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
.cm_wkup_gpio1_clkctrl = 0x4a307838,
.cm_wkup_gptimer1_clkctrl = 0x4a307840,
.cm_wkup_gptimer12_clkctrl = 0x4a307848,
.cm_wkup_synctimer_clkctrl = 0x4a307850,
.cm_wkup_usim_clkctrl = 0x4a307858,
.cm_wkup_sarram_clkctrl = 0x4a307860,
.cm_wkup_keyboard_clkctrl = 0x4a307878,
.cm_wkup_rtc_clkctrl = 0x4a307880,
.cm_wkup_bandgap_clkctrl = 0x4a307888,
.prm_vc_val_bypass = 0x4a307ba0,
.prm_vc_cfg_channel = 0x4a307ba4,
.prm_vc_cfg_i2c_mode = 0x4a307ba8,
.prm_vc_cfg_i2c_clk = 0x4a307bac,
};
struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_id_code = 0x4A002204,
.control_std_fuse_opp_bgap = 0x4a002260,
.control_status = 0x4a0022c4,
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0 = 0x4A100638,
.control_lpddr2io1_1 = 0x4A10063C,
.control_lpddr2io1_2 = 0x4A100640,
.control_lpddr2io1_3 = 0x4A100644,
.control_lpddr2io2_0 = 0x4A100648,
.control_lpddr2io2_1 = 0x4A10064C,
.control_lpddr2io2_2 = 0x4A100650,
.control_lpddr2io2_3 = 0x4A100654,
.control_efuse_1 = 0x4A100700,
.control_efuse_2 = 0x4A100704,
};

34
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View File

@ -90,21 +90,28 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
/* Dummy registers for OMAP44xx */
const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80540300
.dmm_lisa_map_3 = 0x80540300,
.is_ma_present = 0x0
};
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80640300
.dmm_lisa_map_3 = 0x80640300,
.is_ma_present = 0x0
};
const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
.dmm_lisa_map_3 = 0x80640300,
.is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
@ -129,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
else
else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
else
*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
@ -284,3 +293,16 @@ void emif_get_device_timings(u32 emif_nr,
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
.mr2 = 0x4,
.mr3 = -1,
.mr10 = MR10_ZQ_ZQINIT,
.mr16 = MR16_REF_FULL_ARRAY
};
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}

3
arch/arm/cpu/armv7/omap5/Makefile
View File

@ -26,9 +26,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += hwinit.o
COBJS += clocks.o
COBJS += emif.o
COBJS += sdram.o
COBJS += prcm-regs.o
COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

494
arch/arm/cpu/armv7/omap5/clocks.c
View File

@ -1,494 +0,0 @@
/*
*
* Clock initialization for OMAP5
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
* Sricharan R <r.sricharan@ti.com>
*
* Based on previous work by:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Rajendra Nayak <rnayak@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
#ifndef CONFIG_SPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
*/
#define printf(fmt, args...)
#define puts(s)
#endif
struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
0, /* NA */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
0, /* NA */
38400000, /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
void setup_post_dividers(u32 *const base, const struct dpll_params *params)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->h11 >= 0)
writel(params->h11, &dpll_regs->cm_div_h11_dpll);
if (params->h12 >= 0)
writel(params->h12, &dpll_regs->cm_div_h12_dpll);
if (params->h13 >= 0)
writel(params->h13, &dpll_regs->cm_div_h13_dpll);
if (params->h14 >= 0)
writel(params->h14, &dpll_regs->cm_div_h14_dpll);
if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
}
const struct dpll_params *get_mpu_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &mpu_dpll_params_800mhz[sysclk_ind];
}
const struct dpll_params *get_core_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
/* Configuring the DDR to be at 532mhz */
return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
}
const struct dpll_params *get_per_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &per_dpll_params_768mhz[sysclk_ind];
}
const struct dpll_params *get_iva_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &iva_dpll_params_2330mhz[sysclk_ind];
}
const struct dpll_params *get_usb_dpll_params(void)
{
u32 sysclk_ind = get_sys_clk_index();
return &usb_dpll_params_1920mhz[sysclk_ind];
}
const struct dpll_params *get_abe_dpll_params(void)
{
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
u32 sysclk_ind = get_sys_clk_index();
return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
#else
return &abe_dpll_params_32k_196608khz;
#endif
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
*/
void scale_vcores(void)
{
u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */
if (omap_revision() != OMAP5432_ES1_0) {
volt_core = VDD_CORE;
volt_mpu = VDD_MPU;
volt_mm = VDD_MM;
} else {
volt_core = VDD_CORE_5432;
volt_mpu = VDD_MPU_5432;
volt_mm = VDD_MM_5432;
}
do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
if (omap_revision() == OMAP5432_ES1_0) {
/* Configure LDO SRAM "magic" bits */
writel(2, &prcm->prm_sldo_core_setup);
writel(2, &prcm->prm_sldo_mpu_setup);
writel(2, &prcm->prm_sldo_mm_setup);
}
}
u32 get_offset_code(u32 volt_offset)
{
u32 offset_code, step = 10000; /* 10 mV represented in uV */
volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
offset_code = (volt_offset + step - 1) / step;
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
return offset_code + 6;
}
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 *const clk_domains_essential[] = {
&prcm->cm_l4per_clkstctrl,
&prcm->cm_l3init_clkstctrl,
&prcm->cm_memif_clkstctrl,
&prcm->cm_l4cfg_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_wkup_gpio1_clkctrl,
&prcm->cm_l4per_gpio2_clkctrl,
&prcm->cm_l4per_gpio3_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_wkup_gptimer1_clkctrl,
&prcm->cm_l3init_hsmmc1_clkctrl,
&prcm->cm_l3init_hsmmc2_clkctrl,
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
&prcm->cm_l4per_i2c1_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
/* Select 384Mhz for GPU as its the POR for ES1.0 */
setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_HYD_GCLK_MASK);
setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_CORE_GCLK_MASK);
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 *const clk_domains_essential[] = {
0
};
u32 *const clk_modules_hw_auto_essential[] = {
0
};
u32 *const clk_modules_explicit_en_essential[] = {
&prcm->cm_l4per_mcspi1_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
&prcm->cm_l3init_hsusbtll_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
&prcm->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 *const clk_domains_non_essential[] = {
&prcm->cm_mpu_m3_clkstctrl,
&prcm->cm_ivahd_clkstctrl,
&prcm->cm_dsp_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sgx_clkstctrl,
&prcm->cm1_abe_clkstctrl,
&prcm->cm_c2c_clkstctrl,
&prcm->cm_cam_clkstctrl,
&prcm->cm_dss_clkstctrl,
&prcm->cm_sdma_clkstctrl,
0
};
u32 *const clk_modules_hw_auto_non_essential[] = {
&prcm->cm_mpu_m3_mpu_m3_clkctrl,
&prcm->cm_ivahd_ivahd_clkctrl,
&prcm->cm_ivahd_sl2_clkctrl,
&prcm->cm_dsp_dsp_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
0
};
u32 *const clk_modules_explicit_en_non_essential[] = {
&prcm->cm1_abe_aess_clkctrl,
&prcm->cm1_abe_pdm_clkctrl,
&prcm->cm1_abe_dmic_clkctrl,
&prcm->cm1_abe_mcasp_clkctrl,
&prcm->cm1_abe_mcbsp1_clkctrl,
&prcm->cm1_abe_mcbsp2_clkctrl,
&prcm->cm1_abe_mcbsp3_clkctrl,
&prcm->cm1_abe_slimbus_clkctrl,
&prcm->cm1_abe_timer5_clkctrl,
&prcm->cm1_abe_timer6_clkctrl,
&prcm->cm1_abe_timer7_clkctrl,
&prcm->cm1_abe_timer8_clkctrl,
&prcm->cm1_abe_wdt3_clkctrl,
&prcm->cm_l4per_gptimer9_clkctrl,
&prcm->cm_l4per_gptimer10_clkctrl,
&prcm->cm_l4per_gptimer11_clkctrl,
&prcm->cm_l4per_gptimer3_clkctrl,
&prcm->cm_l4per_gptimer4_clkctrl,
&prcm->cm_l4per_mcspi2_clkctrl,
&prcm->cm_l4per_mcspi3_clkctrl,
&prcm->cm_l4per_mcspi4_clkctrl,
&prcm->cm_l4per_mmcsd3_clkctrl,
&prcm->cm_l4per_mmcsd4_clkctrl,
&prcm->cm_l4per_mmcsd5_clkctrl,
&prcm->cm_l4per_uart1_clkctrl,
&prcm->cm_l4per_uart2_clkctrl,
&prcm->cm_l4per_uart4_clkctrl,
&prcm->cm_wkup_keyboard_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_cam_iss_clkctrl,
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

596
arch/arm/cpu/armv7/omap5/hw_data.c Normal file
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@ -0,0 +1,596 @@
/*
*
* HW data initialization for OMAP5
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
/* OPP HIGH FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP LOW FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP LOW FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
{266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
{277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
{368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
{266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
{96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
{533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
{533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
.per = per_dpll_params_768mhz,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap5_dplls_es2 = {
.mpu = mpu_dpll_params_1100mhz,
.core = core_dpll_params_2128mhz_ddr532_es2,
.per = per_dpll_params_768mhz_es2,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_ddr532_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_1066mhz,
};
struct pmic_data palmas = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
};
struct vcores_data omap5430_volts = {
.mpu.value = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5430_volts_es2 = {
.mpu.value = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
/* Select 384Mhz for GPU as its the POR for ES1.0 */
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_HYD_GCLK_MASK);
setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
CLKSEL_GPU_CORE_GCLK_MASK);
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
0
};
u32 const clk_modules_hw_auto_essential[] = {
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
(*prcm)->cm_l3init_hsusbtll_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
/*
* Enable non-essential clock domains, modules and
* do some additional special settings needed
*/
void enable_non_essential_clocks(void)
{
u32 const clk_domains_non_essential[] = {
(*prcm)->cm_mpu_m3_clkstctrl,
(*prcm)->cm_ivahd_clkstctrl,
(*prcm)->cm_dsp_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sgx_clkstctrl,
(*prcm)->cm1_abe_clkstctrl,
(*prcm)->cm_c2c_clkstctrl,
(*prcm)->cm_cam_clkstctrl,
(*prcm)->cm_dss_clkstctrl,
(*prcm)->cm_sdma_clkstctrl,
0
};
u32 const clk_modules_hw_auto_non_essential[] = {
(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
(*prcm)->cm_ivahd_ivahd_clkctrl,
(*prcm)->cm_ivahd_sl2_clkctrl,
(*prcm)->cm_dsp_dsp_clkctrl,
(*prcm)->cm_l3instr_l3_3_clkctrl,
(*prcm)->cm_l3instr_l3_instr_clkctrl,
(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
(*prcm)->cm_l3init_hsi_clkctrl,
(*prcm)->cm_l4per_hdq1w_clkctrl,
0
};
u32 const clk_modules_explicit_en_non_essential[] = {
(*prcm)->cm1_abe_aess_clkctrl,
(*prcm)->cm1_abe_pdm_clkctrl,
(*prcm)->cm1_abe_dmic_clkctrl,
(*prcm)->cm1_abe_mcasp_clkctrl,
(*prcm)->cm1_abe_mcbsp1_clkctrl,
(*prcm)->cm1_abe_mcbsp2_clkctrl,
(*prcm)->cm1_abe_mcbsp3_clkctrl,
(*prcm)->cm1_abe_slimbus_clkctrl,
(*prcm)->cm1_abe_timer5_clkctrl,
(*prcm)->cm1_abe_timer6_clkctrl,
(*prcm)->cm1_abe_timer7_clkctrl,
(*prcm)->cm1_abe_timer8_clkctrl,
(*prcm)->cm1_abe_wdt3_clkctrl,
(*prcm)->cm_l4per_gptimer9_clkctrl,
(*prcm)->cm_l4per_gptimer10_clkctrl,
(*prcm)->cm_l4per_gptimer11_clkctrl,
(*prcm)->cm_l4per_gptimer3_clkctrl,
(*prcm)->cm_l4per_gptimer4_clkctrl,
(*prcm)->cm_l4per_mcspi2_clkctrl,
(*prcm)->cm_l4per_mcspi3_clkctrl,
(*prcm)->cm_l4per_mcspi4_clkctrl,
(*prcm)->cm_l4per_mmcsd3_clkctrl,
(*prcm)->cm_l4per_mmcsd4_clkctrl,
(*prcm)->cm_l4per_mmcsd5_clkctrl,
(*prcm)->cm_l4per_uart1_clkctrl,
(*prcm)->cm_l4per_uart2_clkctrl,
(*prcm)->cm_l4per_uart4_clkctrl,
(*prcm)->cm_wkup_keyboard_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_cam_iss_clkctrl,
(*prcm)->cm_cam_fdif_clkctrl,
(*prcm)->cm_dss_dss_clkctrl,
(*prcm)->cm_sgx_sgx_clkctrl,
0
};
/* Enable optional functional clock for ISS */
setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
/* Enable all optional functional clocks of DSS */
setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
do_enable_clocks(clk_domains_non_essential,
clk_modules_hw_auto_non_essential,
clk_modules_explicit_en_non_essential,
0);
/* Put camera module in no sleep mode */
clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
const struct ctrl_ioregs ioregs_omap5430 = {
.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
};
const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5432_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
*omap_vcores = &omap5430_volts;
*ctrl = &omap5_ctrl;
break;
case OMAP5430_ES2_0:
case OMAP5432_ES2_0:
*prcm = &omap5_es2_prcm;
*dplls_data = &omap5_dplls_es2;
*omap_vcores = &omap5430_volts_es2;
*ctrl = &omap5_ctrl;
break;
case DRA752_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*omap_vcores = &omap5430_volts_es2;
*ctrl = &dra7xx_ctrl;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}
void get_ioregs(const struct ctrl_ioregs **regs)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
break;
case OMAP5432_ES2_0:
case DRA752_ES1_0:
*regs = &ioregs_omap5432_es2;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}

284
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -32,6 +32,7 @@
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clocks.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
@ -56,76 +57,58 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
const struct ctrl_ioregs *ioregs;
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_1));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_0));
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_1));
writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
&(ioregs_base->control_ddrio_0));
writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
&(ioregs_base->control_ddrio_1));
writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
&(ioregs_base->control_ddrio_2));
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
const struct ctrl_ioregs *ioregs;
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch1_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_1));
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch2_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_0));
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_1));
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_0));
writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_1));
writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_2));
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
/* omap5432 does not use lpddr2 */
writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif1_sdram_config));
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif2_sdram_config));
(*ctrl)->control_port_emif2_sdram_config);
}
/*
@ -134,88 +117,198 @@ static void io_settings_ddr3(void)
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
if (omap_revision() <= OMAP5430_ES1_0)
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));
writel(EFUSE_2, &(ioregs_base->control_efuse_2));
writel(EFUSE_3, &(ioregs_base->control_efuse_3));
writel(EFUSE_4, &(ioregs_base->control_efuse_4));
writel(EFUSE_1, (*ctrl)->control_efuse_1);
writel(EFUSE_2, (*ctrl)->control_efuse_2);
writel(EFUSE_3, (*ctrl)->control_efuse_3);
writel(EFUSE_4, (*ctrl)->control_efuse_4);
}
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
{0x45, 0x1}, /* 12 MHz */
{-1, -1}, /* 13 MHz */
{0x63, 0x2}, /* 16.8 MHz */
{0x57, 0x2}, /* 19.2 MHz */
{0x20, 0x1}, /* 26 MHz */
{-1, -1}, /* 27 MHz */
{0x41, 0x3} /* 38.4 MHz */
};
void srcomp_enable(void)
{
u32 srcomp_value, mul_factor, div_factor, clk_val, i;
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev = omap_revision();
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
for (i = 0; i < 4; i++) {
srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &=
~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
}
if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~PWRDWN_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
} else {
srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
}
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)
@ -227,17 +320,25 @@ void init_omap_revision(void)
*/
unsigned int rev = cortex_rev();
switch (rev) {
case MIDR_CORTEX_A15_R0P0:
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5430_ES1_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES1_0:
default:
*omap_si_rev = OMAP5432_ES1_0;
break;
}
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5430_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5432_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5432_ES2_0;
break;
case OMAP5430_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA752_ES1_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
@ -253,7 +354,12 @@ void reset_cpu(ulong ignored)
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}
u32 warm_reset(void)
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

958
arch/arm/cpu/armv7/omap5/prcm-regs.c Normal file
View File

@ -0,0 +1,958 @@
/*
*
* HW regs data for OMAP5 Soc
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/omap_common.h>
struct prcm_regs const omap5_es1_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a004100,
.cm_clksel_abe = 0x4a004108,
.cm_dll_ctrl = 0x4a004110,
.cm_clkmode_dpll_core = 0x4a004120,
.cm_idlest_dpll_core = 0x4a004124,
.cm_autoidle_dpll_core = 0x4a004128,
.cm_clksel_dpll_core = 0x4a00412c,
.cm_div_m2_dpll_core = 0x4a004130,
.cm_div_m3_dpll_core = 0x4a004134,
.cm_div_h11_dpll_core = 0x4a004138,
.cm_div_h12_dpll_core = 0x4a00413c,
.cm_div_h13_dpll_core = 0x4a004140,
.cm_div_h14_dpll_core = 0x4a004144,
.cm_ssc_deltamstep_dpll_core = 0x4a004148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
.cm_emu_override_dpll_core = 0x4a004150,
.cm_div_h22_dpllcore = 0x4a004154,
.cm_div_h23_dpll_core = 0x4a004158,
.cm_clkmode_dpll_mpu = 0x4a004160,
.cm_idlest_dpll_mpu = 0x4a004164,
.cm_autoidle_dpll_mpu = 0x4a004168,
.cm_clksel_dpll_mpu = 0x4a00416c,
.cm_div_m2_dpll_mpu = 0x4a004170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
.cm_bypclk_dpll_mpu = 0x4a00419c,
.cm_clkmode_dpll_iva = 0x4a0041a0,
.cm_idlest_dpll_iva = 0x4a0041a4,
.cm_autoidle_dpll_iva = 0x4a0041a8,
.cm_clksel_dpll_iva = 0x4a0041ac,
.cm_div_h11_dpll_iva = 0x4a0041b8,
.cm_div_h12_dpll_iva = 0x4a0041bc,
.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
.cm_bypclk_dpll_iva = 0x4a0041dc,
.cm_clkmode_dpll_abe = 0x4a0041e0,
.cm_idlest_dpll_abe = 0x4a0041e4,
.cm_autoidle_dpll_abe = 0x4a0041e8,
.cm_clksel_dpll_abe = 0x4a0041ec,
.cm_div_m2_dpll_abe = 0x4a0041f0,
.cm_div_m3_dpll_abe = 0x4a0041f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
.cm_clkmode_dpll_ddrphy = 0x4a004220,
.cm_idlest_dpll_ddrphy = 0x4a004224,
.cm_autoidle_dpll_ddrphy = 0x4a004228,
.cm_clksel_dpll_ddrphy = 0x4a00422c,
.cm_div_m2_dpll_ddrphy = 0x4a004230,
.cm_div_h11_dpll_ddrphy = 0x4a004238,
.cm_div_h12_dpll_ddrphy = 0x4a00423c,
.cm_div_h13_dpll_ddrphy = 0x4a004240,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
.cm_shadow_freq_config1 = 0x4a004260,
.cm_mpu_mpu_clkctrl = 0x4a004320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a004400,
.cm_dsp_dsp_clkctrl = 0x4a004420,
/* cm1.abe */
.cm1_abe_clkstctrl = 0x4a004500,
.cm1_abe_l4abe_clkctrl = 0x4a004520,
.cm1_abe_aess_clkctrl = 0x4a004528,
.cm1_abe_pdm_clkctrl = 0x4a004530,
.cm1_abe_dmic_clkctrl = 0x4a004538,
.cm1_abe_mcasp_clkctrl = 0x4a004540,
.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
.cm1_abe_slimbus_clkctrl = 0x4a004560,
.cm1_abe_timer5_clkctrl = 0x4a004568,
.cm1_abe_timer6_clkctrl = 0x4a004570,
.cm1_abe_timer7_clkctrl = 0x4a004578,
.cm1_abe_timer8_clkctrl = 0x4a004580,
.cm1_abe_wdt3_clkctrl = 0x4a004588,
/* cm2.ckgen */
.cm_clksel_mpu_m3_iss_root = 0x4a008100,
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_scale_fclk = 0x4a008108,
.cm_core_dvfs_perf1 = 0x4a008110,
.cm_core_dvfs_perf2 = 0x4a008114,
.cm_core_dvfs_perf3 = 0x4a008118,
.cm_core_dvfs_perf4 = 0x4a00811c,
.cm_core_dvfs_current = 0x4a008124,
.cm_iva_dvfs_perf_tesla = 0x4a008128,
.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
.cm_iva_dvfs_perf_abe = 0x4a008130,
.cm_iva_dvfs_current = 0x4a008138,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_h11_dpll_per = 0x4a008158,
.cm_div_h12_dpll_per = 0x4a00815c,
.cm_div_h14_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_emu_override_dpll_per = 0x4a008170,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_unipro = 0x4a0081c0,
.cm_idlest_dpll_unipro = 0x4a0081c4,
.cm_autoidle_dpll_unipro = 0x4a0081c8,
.cm_clksel_dpll_unipro = 0x4a0081cc,
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
/* cm2.core */
.cm_coreaon_bandgap_clkctrl = 0x4a008648,
.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_memif_emif_h1_clkctrl = 0x4a008b50,
.cm_memif_emif_h2_clkctrl = 0x4a008b58,
.cm_memif_dll_h_clkctrl = 0x4a008b60,
.cm_c2c_clkstctrl = 0x4a008c00,
.cm_c2c_staticdep = 0x4a008c04,
.cm_c2c_dynamicdep = 0x4a008c08,
.cm_c2c_sad2d_clkctrl = 0x4a008c20,
.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
/* cm2.ivahd */
.cm_ivahd_clkstctrl = 0x4a008f00,
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009000,
.cm_cam_iss_clkctrl = 0x4a009020,
.cm_cam_fdif_clkctrl = 0x4a009028,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009100,
.cm_dss_dss_clkctrl = 0x4a009120,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009200,
.cm_sgx_sgx_clkctrl = 0x4a009220,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009300,
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
.cm_l3init_hsi_clkctrl = 0x4a009338,
.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
.cm_l3init_p1500_clkctrl = 0x4a009378,
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009400,
.cm_l4per_dynamicdep = 0x4a009408,
.cm_l4per_adc_clkctrl = 0x4a009420,
.cm_l4per_gptimer10_clkctrl = 0x4a009428,
.cm_l4per_gptimer11_clkctrl = 0x4a009430,
.cm_l4per_gptimer2_clkctrl = 0x4a009438,
.cm_l4per_gptimer3_clkctrl = 0x4a009440,
.cm_l4per_gptimer4_clkctrl = 0x4a009448,
.cm_l4per_gptimer9_clkctrl = 0x4a009450,
.cm_l4per_elm_clkctrl = 0x4a009458,
.cm_l4per_gpio2_clkctrl = 0x4a009460,
.cm_l4per_gpio3_clkctrl = 0x4a009468,
.cm_l4per_gpio4_clkctrl = 0x4a009470,
.cm_l4per_gpio5_clkctrl = 0x4a009478,
.cm_l4per_gpio6_clkctrl = 0x4a009480,
.cm_l4per_hdq1w_clkctrl = 0x4a009488,
.cm_l4per_hecc1_clkctrl = 0x4a009490,
.cm_l4per_hecc2_clkctrl = 0x4a009498,
.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
.cm_l4per_l4per_clkctrl = 0x4a0094c0,
.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
.cm_l4per_mgate_clkctrl = 0x4a0094e8,
.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009500,
.cm_l4per_mcspi4_clkctrl = 0x4a009508,
.cm_l4per_gpio7_clkctrl = 0x4a009510,
.cm_l4per_gpio8_clkctrl = 0x4a009518,
.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
.cm_l4per_msprohg_clkctrl = 0x4a009530,
.cm_l4per_slimbus2_clkctrl = 0x4a009538,
.cm_l4per_uart1_clkctrl = 0x4a009540,
.cm_l4per_uart2_clkctrl = 0x4a009548,
.cm_l4per_uart3_clkctrl = 0x4a009550,
.cm_l4per_uart4_clkctrl = 0x4a009558,
.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
.cm_l4per_i2c5_clkctrl = 0x4a009568,
.cm_l4per_uart5_clkctrl = 0x4a009570,
.cm_l4per_uart6_clkctrl = 0x4a009578,
.cm_l4sec_clkstctrl = 0x4a009580,
.cm_l4sec_staticdep = 0x4a009584,
.cm_l4sec_dynamicdep = 0x4a009588,
.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
.cm_l4sec_rng_clkctrl = 0x4a0095c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
.cm_wkup_gpio1_clkctrl = 0x4ae07838,
.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
.cm_wkup_synctimer_clkctrl = 0x4ae07850,
.cm_wkup_usim_clkctrl = 0x4ae07858,
.cm_wkup_sarram_clkctrl = 0x4ae07860,
.cm_wkup_keyboard_clkctrl = 0x4ae07878,
.cm_wkup_rtc_clkctrl = 0x4ae07880,
.cm_wkup_bandgap_clkctrl = 0x4ae07888,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
.prm_rstctrl = 0x4ae07b00,
.prm_rstst = 0x4ae07b04,
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
.prm_sldo_core_setup = 0x4ae07bc4,
.prm_sldo_core_ctrl = 0x4ae07bc8,
.prm_sldo_mpu_setup = 0x4ae07bcc,
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
};
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
.control_smart1io_padconf_1 = 0x4A002DAC,
.control_smart1io_padconf_2 = 0x4A002DB0,
.control_smart2io_padconf_0 = 0x4A002DB4,
.control_smart2io_padconf_1 = 0x4A002DB8,
.control_smart2io_padconf_2 = 0x4A002DBC,
.control_smart3io_padconf_0 = 0x4A002DC0,
.control_smart3io_padconf_1 = 0x4A002DC4,
.control_pbias = 0x4A002E00,
.control_i2c_0 = 0x4A002E04,
.control_camera_rx = 0x4A002E08,
.control_hdmi_tx_phy = 0x4A002E0C,
.control_uniportm = 0x4A002E10,
.control_dsiphy = 0x4A002E14,
.control_mcbsplp = 0x4A002E18,
.control_usb2phycore = 0x4A002E1C,
.control_hdmi_1 = 0x4A002E20,
.control_hsi = 0x4A002E24,
.control_ddr3ch1_0 = 0x4A002E30,
.control_ddr3ch2_0 = 0x4A002E34,
.control_ddrch1_0 = 0x4A002E38,
.control_ddrch1_1 = 0x4A002E3C,
.control_ddrch2_0 = 0x4A002E40,
.control_ddrch2_1 = 0x4A002E44,
.control_lpddr2ch1_0 = 0x4A002E48,
.control_lpddr2ch1_1 = 0x4A002E4C,
.control_ddrio_0 = 0x4A002E50,
.control_ddrio_1 = 0x4A002E54,
.control_ddrio_2 = 0x4A002E58,
.control_hyst_1 = 0x4A002E5C,
.control_usbb_hsic_control = 0x4A002E60,
.control_c2c = 0x4A002E64,
.control_core_control_spare_rw = 0x4A002E68,
.control_core_control_spare_r = 0x4A002E6C,
.control_core_control_spare_r_c0 = 0x4A002E70,
.control_srcomp_north_side = 0x4A002E74,
.control_srcomp_south_side = 0x4A002E78,
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
.control_xtal_oscillator = 0x4AE0CDAC,
.control_i2c_2 = 0x4AE0CDB0,
.control_ckobuffer = 0x4AE0CDB4,
.control_wkup_control_spare_rw = 0x4AE0CDB8,
.control_wkup_control_spare_r = 0x4AE0CDBC,
.control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
.control_srcomp_east_side_wkup = 0x4AE0CDC4,
.control_efuse_1 = 0x4AE0CDC8,
.control_efuse_2 = 0x4AE0CDCC,
.control_efuse_3 = 0x4AE0CDD0,
.control_efuse_4 = 0x4AE0CDD4,
.control_efuse_5 = 0x4AE0CDD8,
.control_efuse_6 = 0x4AE0CDDC,
.control_efuse_7 = 0x4AE0CDE0,
.control_efuse_8 = 0x4AE0CDE4,
.control_efuse_9 = 0x4AE0CDE8,
.control_efuse_10 = 0x4AE0CDEC,
.control_efuse_11 = 0x4AE0CDF0,
.control_efuse_12 = 0x4AE0CDF4,
.control_efuse_13 = 0x4AE0CDF8,
};
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
.control_core_mmr_lock1 = 0x4A002540,
.control_core_mmr_lock2 = 0x4A002544,
.control_core_mmr_lock3 = 0x4A002548,
.control_core_mmr_lock4 = 0x4A00254C,
.control_core_mmr_lock5 = 0x4A002550,
.control_core_control_io1 = 0x4A002554,
.control_core_control_io2 = 0x4A002558,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
.control_smart1io_padconf_1 = 0x4A002DAC,
.control_smart1io_padconf_2 = 0x4A002DB0,
.control_smart2io_padconf_0 = 0x4A002DB4,
.control_smart2io_padconf_1 = 0x4A002DB8,
.control_smart2io_padconf_2 = 0x4A002DBC,
.control_smart3io_padconf_0 = 0x4A002DC0,
.control_smart3io_padconf_1 = 0x4A002DC4,
.control_pbias = 0x4A002E00,
.control_i2c_0 = 0x4A002E04,
.control_camera_rx = 0x4A002E08,
.control_hdmi_tx_phy = 0x4A002E0C,
.control_uniportm = 0x4A002E10,
.control_dsiphy = 0x4A002E14,
.control_mcbsplp = 0x4A002E18,
.control_usb2phycore = 0x4A002E1C,
.control_hdmi_1 = 0x4A002E20,
.control_hsi = 0x4A002E24,
.control_ddr3ch1_0 = 0x4A002E30,
.control_ddr3ch2_0 = 0x4A002E34,
.control_ddrch1_0 = 0x4A002E38,
.control_ddrch1_1 = 0x4A002E3C,
.control_ddrch2_0 = 0x4A002E40,
.control_ddrch2_1 = 0x4A002E44,
.control_lpddr2ch1_0 = 0x4A002E48,
.control_lpddr2ch1_1 = 0x4A002E4C,
.control_ddrio_0 = 0x4A002E50,
.control_ddrio_1 = 0x4A002E54,
.control_ddrio_2 = 0x4A002E58,
.control_hyst_1 = 0x4A002E5C,
.control_usbb_hsic_control = 0x4A002E60,
.control_c2c = 0x4A002E64,
.control_core_control_spare_rw = 0x4A002E68,
.control_core_control_spare_r = 0x4A002E6C,
.control_core_control_spare_r_c0 = 0x4A002E70,
.control_srcomp_north_side = 0x4A002E74,
.control_srcomp_south_side = 0x4A002E78,
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
.control_padconf_core_base = 0x4A003400,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
.control_padconf_mode = 0x4AE0C5A0,
.control_xtal_oscillator = 0x4AE0C5A4,
.control_i2c_2 = 0x4AE0C5A8,
.control_ckobuffer = 0x4AE0C5AC,
.control_wkup_control_spare_rw = 0x4AE0C5B0,
.control_wkup_control_spare_r = 0x4AE0C5B4,
.control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
.control_srcomp_east_side_wkup = 0x4AE0C5BC,
.control_efuse_1 = 0x4AE0C5C0,
.control_efuse_2 = 0x4AE0C5C4,
.control_efuse_3 = 0x4AE0C5C8,
.control_efuse_4 = 0x4AE0C5CC,
.control_efuse_13 = 0x4AE0C5F0,
};
struct prcm_regs const omap5_es2_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a004100,
.cm_clksel_abe = 0x4a004108,
.cm_dll_ctrl = 0x4a004110,
.cm_clkmode_dpll_core = 0x4a004120,
.cm_idlest_dpll_core = 0x4a004124,
.cm_autoidle_dpll_core = 0x4a004128,
.cm_clksel_dpll_core = 0x4a00412c,
.cm_div_m2_dpll_core = 0x4a004130,
.cm_div_m3_dpll_core = 0x4a004134,
.cm_div_h11_dpll_core = 0x4a004138,
.cm_div_h12_dpll_core = 0x4a00413c,
.cm_div_h13_dpll_core = 0x4a004140,
.cm_div_h14_dpll_core = 0x4a004144,
.cm_ssc_deltamstep_dpll_core = 0x4a004148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
.cm_div_h21_dpll_core = 0x4a004150,
.cm_div_h22_dpllcore = 0x4a004154,
.cm_div_h23_dpll_core = 0x4a004158,
.cm_div_h24_dpll_core = 0x4a00415c,
.cm_clkmode_dpll_mpu = 0x4a004160,
.cm_idlest_dpll_mpu = 0x4a004164,
.cm_autoidle_dpll_mpu = 0x4a004168,
.cm_clksel_dpll_mpu = 0x4a00416c,
.cm_div_m2_dpll_mpu = 0x4a004170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
.cm_bypclk_dpll_mpu = 0x4a00419c,
.cm_clkmode_dpll_iva = 0x4a0041a0,
.cm_idlest_dpll_iva = 0x4a0041a4,
.cm_autoidle_dpll_iva = 0x4a0041a8,
.cm_clksel_dpll_iva = 0x4a0041ac,
.cm_div_h11_dpll_iva = 0x4a0041b8,
.cm_div_h12_dpll_iva = 0x4a0041bc,
.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
.cm_bypclk_dpll_iva = 0x4a0041dc,
.cm_clkmode_dpll_abe = 0x4a0041e0,
.cm_idlest_dpll_abe = 0x4a0041e4,
.cm_autoidle_dpll_abe = 0x4a0041e8,
.cm_clksel_dpll_abe = 0x4a0041ec,
.cm_div_m2_dpll_abe = 0x4a0041f0,
.cm_div_m3_dpll_abe = 0x4a0041f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
.cm_clkmode_dpll_ddrphy = 0x4a004220,
.cm_idlest_dpll_ddrphy = 0x4a004224,
.cm_autoidle_dpll_ddrphy = 0x4a004228,
.cm_clksel_dpll_ddrphy = 0x4a00422c,
.cm_div_m2_dpll_ddrphy = 0x4a004230,
.cm_div_h11_dpll_ddrphy = 0x4a004238,
.cm_div_h12_dpll_ddrphy = 0x4a00423c,
.cm_div_h13_dpll_ddrphy = 0x4a004240,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
.cm_shadow_freq_config1 = 0x4a004260,
.cm_mpu_mpu_clkctrl = 0x4a004320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a004400,
.cm_dsp_dsp_clkctrl = 0x4a004420,
/* cm1.abe */
.cm1_abe_clkstctrl = 0x4a004500,
.cm1_abe_l4abe_clkctrl = 0x4a004520,
.cm1_abe_aess_clkctrl = 0x4a004528,
.cm1_abe_pdm_clkctrl = 0x4a004530,
.cm1_abe_dmic_clkctrl = 0x4a004538,
.cm1_abe_mcasp_clkctrl = 0x4a004540,
.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
.cm1_abe_slimbus_clkctrl = 0x4a004560,
.cm1_abe_timer5_clkctrl = 0x4a004568,
.cm1_abe_timer6_clkctrl = 0x4a004570,
.cm1_abe_timer7_clkctrl = 0x4a004578,
.cm1_abe_timer8_clkctrl = 0x4a004580,
.cm1_abe_wdt3_clkctrl = 0x4a004588,
/* cm2.ckgen */
.cm_clksel_mpu_m3_iss_root = 0x4a008100,
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_scale_fclk = 0x4a008108,
.cm_core_dvfs_perf1 = 0x4a008110,
.cm_core_dvfs_perf2 = 0x4a008114,
.cm_core_dvfs_perf3 = 0x4a008118,
.cm_core_dvfs_perf4 = 0x4a00811c,
.cm_core_dvfs_current = 0x4a008124,
.cm_iva_dvfs_perf_tesla = 0x4a008128,
.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
.cm_iva_dvfs_perf_abe = 0x4a008130,
.cm_iva_dvfs_current = 0x4a008138,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_h11_dpll_per = 0x4a008158,
.cm_div_h12_dpll_per = 0x4a00815c,
.cm_div_h13_dpll_per = 0x4a008160,
.cm_div_h14_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_emu_override_dpll_per = 0x4a008170,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_unipro = 0x4a0081c0,
.cm_idlest_dpll_unipro = 0x4a0081c4,
.cm_autoidle_dpll_unipro = 0x4a0081c8,
.cm_clksel_dpll_unipro = 0x4a0081cc,
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
.cm_coreaon_bandgap_clkctrl = 0x4a008648,
.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_2_clkstctrl = 0x4a008800,
.cm_l3_2_dynamicdep = 0x4a008808,
.cm_l3_2_l3_2_clkctrl = 0x4a008820,
.cm_l3_gpmc_clkctrl = 0x4a008828,
.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_memif_emif_h1_clkctrl = 0x4a008b50,
.cm_memif_emif_h2_clkctrl = 0x4a008b58,
.cm_memif_dll_h_clkctrl = 0x4a008b60,
.cm_c2c_clkstctrl = 0x4a008c00,
.cm_c2c_staticdep = 0x4a008c04,
.cm_c2c_dynamicdep = 0x4a008c08,
.cm_c2c_sad2d_clkctrl = 0x4a008c20,
.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
.cm_l4per_clkstctrl = 0x4a009000,
.cm_l4per_dynamicdep = 0x4a009008,
.cm_l4per_adc_clkctrl = 0x4a009020,
.cm_l4per_gptimer10_clkctrl = 0x4a009028,
.cm_l4per_gptimer11_clkctrl = 0x4a009030,
.cm_l4per_gptimer2_clkctrl = 0x4a009038,
.cm_l4per_gptimer3_clkctrl = 0x4a009040,
.cm_l4per_gptimer4_clkctrl = 0x4a009048,
.cm_l4per_gptimer9_clkctrl = 0x4a009050,
.cm_l4per_elm_clkctrl = 0x4a009058,
.cm_l4per_gpio2_clkctrl = 0x4a009060,
.cm_l4per_gpio3_clkctrl = 0x4a009068,
.cm_l4per_gpio4_clkctrl = 0x4a009070,
.cm_l4per_gpio5_clkctrl = 0x4a009078,
.cm_l4per_gpio6_clkctrl = 0x4a009080,
.cm_l4per_hdq1w_clkctrl = 0x4a009088,
.cm_l4per_hecc1_clkctrl = 0x4a009090,
.cm_l4per_hecc2_clkctrl = 0x4a009098,
.cm_l4per_i2c1_clkctrl = 0x4a0090a0,
.cm_l4per_i2c2_clkctrl = 0x4a0090a8,
.cm_l4per_i2c3_clkctrl = 0x4a0090b0,
.cm_l4per_i2c4_clkctrl = 0x4a0090b8,
.cm_l4per_l4per_clkctrl = 0x4a0090c0,
.cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
.cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
.cm_l4per_mgate_clkctrl = 0x4a0090e8,
.cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009100,
.cm_l4per_mcspi4_clkctrl = 0x4a009108,
.cm_l4per_gpio7_clkctrl = 0x4a009110,
.cm_l4per_gpio8_clkctrl = 0x4a009118,
.cm_l4per_mmcsd3_clkctrl = 0x4a009120,
.cm_l4per_mmcsd4_clkctrl = 0x4a009128,
.cm_l4per_msprohg_clkctrl = 0x4a009130,
.cm_l4per_slimbus2_clkctrl = 0x4a009138,
.cm_l4per_uart1_clkctrl = 0x4a009140,
.cm_l4per_uart2_clkctrl = 0x4a009148,
.cm_l4per_uart3_clkctrl = 0x4a009150,
.cm_l4per_uart4_clkctrl = 0x4a009158,
.cm_l4per_mmcsd5_clkctrl = 0x4a009160,
.cm_l4per_i2c5_clkctrl = 0x4a009168,
.cm_l4per_uart5_clkctrl = 0x4a009170,
.cm_l4per_uart6_clkctrl = 0x4a009178,
.cm_l4sec_clkstctrl = 0x4a009180,
.cm_l4sec_staticdep = 0x4a009184,
.cm_l4sec_dynamicdep = 0x4a009188,
.cm_l4sec_aes1_clkctrl = 0x4a0091a0,
.cm_l4sec_aes2_clkctrl = 0x4a0091a8,
.cm_l4sec_des3des_clkctrl = 0x4a0091b0,
.cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
.cm_l4sec_rng_clkctrl = 0x4a0091c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
/* cm2.ivahd */
.cm_ivahd_clkstctrl = 0x4a009200,
.cm_ivahd_ivahd_clkctrl = 0x4a009220,
.cm_ivahd_sl2_clkctrl = 0x4a009228,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009300,
.cm_cam_iss_clkctrl = 0x4a009320,
.cm_cam_fdif_clkctrl = 0x4a009328,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009400,
.cm_dss_dss_clkctrl = 0x4a009420,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009500,
.cm_sgx_sgx_clkctrl = 0x4a009520,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009600,
/* cm2.l3init */
.cm_l3init_hsmmc1_clkctrl = 0x4a009628,
.cm_l3init_hsmmc2_clkctrl = 0x4a009630,
.cm_l3init_hsi_clkctrl = 0x4a009638,
.cm_l3init_hsusbhost_clkctrl = 0x4a009658,
.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
.cm_l3init_p1500_clkctrl = 0x4a009678,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
.cm_wkup_clkstctrl = 0x4ae07900,
.cm_wkup_l4wkup_clkctrl = 0x4ae07920,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
.cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
.cm_wkup_gpio1_clkctrl = 0x4ae07938,
.cm_wkup_gptimer1_clkctrl = 0x4ae07940,
.cm_wkup_gptimer12_clkctrl = 0x4ae07948,
.cm_wkup_synctimer_clkctrl = 0x4ae07950,
.cm_wkup_usim_clkctrl = 0x4ae07958,
.cm_wkup_sarram_clkctrl = 0x4ae07960,
.cm_wkup_keyboard_clkctrl = 0x4ae07978,
.cm_wkup_rtc_clkctrl = 0x4ae07980,
.cm_wkup_bandgap_clkctrl = 0x4ae07988,
.cm_wkupaon_scrm_clkctrl = 0x4ae07990,
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
.prm_rstctrl = 0x4ae07c00,
.prm_rstst = 0x4ae07c04,
.prm_vc_val_bypass = 0x4ae07ca0,
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
.prm_sldo_core_setup = 0x4ae07cc4,
.prm_sldo_core_ctrl = 0x4ae07cc8,
.prm_sldo_mpu_setup = 0x4ae07ccc,
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
};
struct prcm_regs const dra7xx_prcm = {
/* cm1.ckgen */
.cm_clksel_core = 0x4a005100,
.cm_clksel_abe = 0x4a005108,
.cm_dll_ctrl = 0x4a005110,
.cm_clkmode_dpll_core = 0x4a005120,
.cm_idlest_dpll_core = 0x4a005124,
.cm_autoidle_dpll_core = 0x4a005128,
.cm_clksel_dpll_core = 0x4a00512c,
.cm_div_m2_dpll_core = 0x4a005130,
.cm_div_m3_dpll_core = 0x4a005134,
.cm_div_h11_dpll_core = 0x4a005138,
.cm_div_h12_dpll_core = 0x4a00513c,
.cm_div_h13_dpll_core = 0x4a005140,
.cm_div_h14_dpll_core = 0x4a005144,
.cm_ssc_deltamstep_dpll_core = 0x4a005148,
.cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
.cm_div_h21_dpll_core = 0x4a005150,
.cm_div_h22_dpllcore = 0x4a005154,
.cm_div_h23_dpll_core = 0x4a005158,
.cm_div_h24_dpll_core = 0x4a00515c,
.cm_clkmode_dpll_mpu = 0x4a005160,
.cm_idlest_dpll_mpu = 0x4a005164,
.cm_autoidle_dpll_mpu = 0x4a005168,
.cm_clksel_dpll_mpu = 0x4a00516c,
.cm_div_m2_dpll_mpu = 0x4a005170,
.cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
.cm_bypclk_dpll_mpu = 0x4a00519c,
.cm_clkmode_dpll_iva = 0x4a0051a0,
.cm_idlest_dpll_iva = 0x4a0051a4,
.cm_autoidle_dpll_iva = 0x4a0051a8,
.cm_clksel_dpll_iva = 0x4a0051ac,
.cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
.cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
.cm_bypclk_dpll_iva = 0x4a0051dc,
.cm_clkmode_dpll_abe = 0x4a0051e0,
.cm_idlest_dpll_abe = 0x4a0051e4,
.cm_autoidle_dpll_abe = 0x4a0051e8,
.cm_clksel_dpll_abe = 0x4a0051ec,
.cm_div_m2_dpll_abe = 0x4a0051f0,
.cm_div_m3_dpll_abe = 0x4a0051f4,
.cm_ssc_deltamstep_dpll_abe = 0x4a005208,
.cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
.cm_clkmode_dpll_ddrphy = 0x4a005210,
.cm_idlest_dpll_ddrphy = 0x4a005214,
.cm_autoidle_dpll_ddrphy = 0x4a005218,
.cm_clksel_dpll_ddrphy = 0x4a00521c,
.cm_div_m2_dpll_ddrphy = 0x4a005220,
.cm_div_h11_dpll_ddrphy = 0x4a005228,
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
/* cm1.dsp */
.cm_dsp_clkstctrl = 0x4a005400,
.cm_dsp_dsp_clkctrl = 0x4a005420,
/* cm2.ckgen */
.cm_clksel_usb_60mhz = 0x4a008104,
.cm_clkmode_dpll_per = 0x4a008140,
.cm_idlest_dpll_per = 0x4a008144,
.cm_autoidle_dpll_per = 0x4a008148,
.cm_clksel_dpll_per = 0x4a00814c,
.cm_div_m2_dpll_per = 0x4a008150,
.cm_div_m3_dpll_per = 0x4a008154,
.cm_div_h11_dpll_per = 0x4a008158,
.cm_div_h12_dpll_per = 0x4a00815c,
.cm_div_h13_dpll_per = 0x4a008160,
.cm_div_h14_dpll_per = 0x4a008164,
.cm_ssc_deltamstep_dpll_per = 0x4a008168,
.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
.cm_clkmode_dpll_usb = 0x4a008180,
.cm_idlest_dpll_usb = 0x4a008184,
.cm_autoidle_dpll_usb = 0x4a008188,
.cm_clksel_dpll_usb = 0x4a00818c,
.cm_div_m2_dpll_usb = 0x4a008190,
.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
.cm_clkmode_dpll_pcie_ref = 0x4a008200,
.cm_clkmode_apll_pcie = 0x4a00821c,
.cm_idlest_apll_pcie = 0x4a008220,
.cm_div_m2_apll_pcie = 0x4a008224,
.cm_clkvcoldo_apll_pcie = 0x4a008228,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
.cm_l3_1_dynamicdep = 0x4a008708,
.cm_l3_1_l3_1_clkctrl = 0x4a008720,
.cm_l3_gpmc_clkctrl = 0x4a008728,
.cm_mpu_m3_clkstctrl = 0x4a008900,
.cm_mpu_m3_staticdep = 0x4a008904,
.cm_mpu_m3_dynamicdep = 0x4a008908,
.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
.cm_sdma_clkstctrl = 0x4a008a00,
.cm_sdma_staticdep = 0x4a008a04,
.cm_sdma_dynamicdep = 0x4a008a08,
.cm_sdma_sdma_clkctrl = 0x4a008a20,
.cm_memif_clkstctrl = 0x4a008b00,
.cm_memif_dmm_clkctrl = 0x4a008b20,
.cm_memif_emif_fw_clkctrl = 0x4a008b28,
.cm_memif_emif_1_clkctrl = 0x4a008b30,
.cm_memif_emif_2_clkctrl = 0x4a008b38,
.cm_memif_dll_clkctrl = 0x4a008b40,
.cm_l4cfg_clkstctrl = 0x4a008d00,
.cm_l4cfg_dynamicdep = 0x4a008d08,
.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
.cm_l3instr_clkstctrl = 0x4a008e00,
.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
/* cm2.ivahd */
.cm_ivahd_clkstctrl = 0x4a008f00,
.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
.cm_ivahd_sl2_clkctrl = 0x4a008f28,
/* cm2.cam */
.cm_cam_clkstctrl = 0x4a009000,
.cm_cam_vip1_clkctrl = 0x4a009020,
.cm_cam_vip2_clkctrl = 0x4a009028,
.cm_cam_vip3_clkctrl = 0x4a009030,
.cm_cam_lvdsrx_clkctrl = 0x4a009038,
.cm_cam_csi1_clkctrl = 0x4a009040,
.cm_cam_csi2_clkctrl = 0x4a009048,
/* cm2.dss */
.cm_dss_clkstctrl = 0x4a009100,
.cm_dss_dss_clkctrl = 0x4a009120,
/* cm2.sgx */
.cm_sgx_clkstctrl = 0x4a009200,
.cm_sgx_sgx_clkctrl = 0x4a009220,
/* cm2.l3init */
.cm_l3init_clkstctrl = 0x4a009300,
/* cm2.l3init */
.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
.cm_l4per_dynamicdep = 0x4a009708,
.cm_l4per_gptimer10_clkctrl = 0x4a009728,
.cm_l4per_gptimer11_clkctrl = 0x4a009730,
.cm_l4per_gptimer2_clkctrl = 0x4a009738,
.cm_l4per_gptimer3_clkctrl = 0x4a009740,
.cm_l4per_gptimer4_clkctrl = 0x4a009748,
.cm_l4per_gptimer9_clkctrl = 0x4a009750,
.cm_l4per_elm_clkctrl = 0x4a009758,
.cm_l4per_gpio2_clkctrl = 0x4a009760,
.cm_l4per_gpio3_clkctrl = 0x4a009768,
.cm_l4per_gpio4_clkctrl = 0x4a009770,
.cm_l4per_gpio5_clkctrl = 0x4a009778,
.cm_l4per_gpio6_clkctrl = 0x4a009780,
.cm_l4per_hdq1w_clkctrl = 0x4a009788,
.cm_l4per_i2c1_clkctrl = 0x4a0097a0,
.cm_l4per_i2c2_clkctrl = 0x4a0097a8,
.cm_l4per_i2c3_clkctrl = 0x4a0097b0,
.cm_l4per_i2c4_clkctrl = 0x4a0097b8,
.cm_l4per_l4per_clkctrl = 0x4a0097c0,
.cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
.cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
.cm_l4per_mcspi3_clkctrl = 0x4a009800,
.cm_l4per_mcspi4_clkctrl = 0x4a009808,
.cm_l4per_gpio7_clkctrl = 0x4a009810,
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl = 0x4a009820,
.cm_l4per_mmcsd4_clkctrl = 0x4a009828,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
.cm_l4per_uart4_clkctrl = 0x4a009858,
.cm_l4per_uart5_clkctrl = 0x4a009870,
.cm_l4sec_clkstctrl = 0x4a009880,
.cm_l4sec_staticdep = 0x4a009884,
.cm_l4sec_dynamicdep = 0x4a009888,
.cm_l4sec_aes1_clkctrl = 0x4a0098a0,
.cm_l4sec_aes2_clkctrl = 0x4a0098a8,
.cm_l4sec_des3des_clkctrl = 0x4a0098b0,
.cm_l4sec_rng_clkctrl = 0x4a0098c0,
.cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
.cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
.cm_wkup_gpio1_clkctrl = 0x4ae07838,
.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
.cm_wkup_sarram_clkctrl = 0x4ae07860,
.cm_wkup_keyboard_clkctrl = 0x4ae07878,
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.prm_rstctrl = 0x4ae07d00,
.prm_rstst = 0x4ae07d04,
.prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8,
};

232
arch/arm/cpu/armv7/omap5/sdram.c
View File

@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = {
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.ref_ctrl = 0x0000081A,
.sdram_tim1 = 0x772F6873,
.sdram_tim2 = 0x304a129a,
.sdram_tim3 = 0x02f7e45f,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x100b3215,
.temp_alert_config = 0x08000a05,
.emif_ddr_phy_ctlr_1_init = 0x0E30400d,
.emif_ddr_phy_ctlr_1 = 0x0E30400d,
.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
.emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
};
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
@ -109,76 +128,86 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0030400A,
.emif_ddr_phy_ctlr_1 = 0x0034400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x40000305
};
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000001,
0x540A8150,
0xA81502a0,
0x002A0540,
0x00000000,
0x00000000,
0x00000000,
0x00000077
};
const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x0,
0x0,
0x0,
0x00000000,
0x00000000,
0x00000000,
0x00000057
const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x0,
.dmm_lisa_map_3 = 0x80500100,
.is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
if (omap_revision() == OMAP5432_ES1_0)
*regs = &emif_regs_ddr3_532_mhz_1cs;
else
switch (omap_revision()) {
case OMAP5430_ES1_0:
*regs = &emif_regs_532_mhz_2cs;
break;
case OMAP5432_ES1_0:
*regs = &emif_regs_ddr3_532_mhz_1cs;
break;
case OMAP5430_ES2_0:
*regs = &emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
case DRA752_ES1_0:
default:
*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
}
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
**dmm_lisa_regs)
{
*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
case OMAP5432_ES1_0:
case OMAP5432_ES2_0:
*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
break;
case DRA752_ES1_0:
default:
*dmm_lisa_regs = &lisa_map_512M_x_1;
}
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
#else
static const struct lpddr2_device_details dev_4G_S4_details = {
@ -204,10 +233,108 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000001,
0x540A8150,
0xA81502a0,
0x002A0540,
0x00000000,
0x00000000,
0x00000000,
0x00000077
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x0,
0x0,
0x0,
0x00000000,
0x00000000,
0x00000000,
0x00000057
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x50D4350D,
0x00000D43,
0x04010040,
0x01004010,
0x00001004,
0x00000000,
0x00000000,
0x00000000,
0x80080080,
0x00800800,
0x08102040,
0x00000002,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000057
};
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
.mr2 = 0x6,
.mr3 = 0x1,
.mr10 = MR10_ZQ_ZQINIT,
.mr16 = MR16_REF_FULL_ARRAY
};
static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
break;
case OMAP5432_ES2_0:
case DRA752_ES1_0:
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
}
}
void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@ -226,12 +353,13 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_base[i],
emif_ext_phy_ctrl_base++);
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
}
}

19
arch/arm/cpu/armv7/start.S
View File

@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15)
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
#endif
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_ARM_ERRATA_742230
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 4 @ set bit #4
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 6 @ set bit #6
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_751472
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 11 @ set bit #11
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)

1
arch/arm/cpu/armv7/tegra20/Makefile
View File

@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
COBJS-$(CONFIG_VIDEO_TEGRA) += display.o

567
arch/arm/cpu/armv7/tegra20/usb.c
View File

@ -1,567 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
#include <usb/ulpi.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <libfdt.h>
#include <fdtdec.h>
#ifdef CONFIG_USB_ULPI
#ifndef CONFIG_USB_ULPI_VIEWPORT
#error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
define CONFIG_USB_ULPI_VIEWPORT"
#endif
#endif
enum {
USB_PORTS_MAX = 4, /* Maximum ports we allow */
};
/* Parameters we need for USB */
enum {
PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
PARAM_DIVM, /* PLL INPUT DIVIDER */
PARAM_DIVP, /* POST DIVIDER (2^N) */
PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
PARAM_STABLE_COUNT, /* PLL-U STABLE count */
PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
PARAM_COUNT
};
/* Possible port types (dual role mode) */
enum dr_mode {
DR_MODE_NONE = 0,
DR_MODE_HOST, /* supports host operation */
DR_MODE_DEVICE, /* supports device operation */
DR_MODE_OTG, /* supports both */
};
/* Information about a USB port */
struct fdt_usb {
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
enum dr_mode dr_mode; /* dual role mode */
enum periph_id periph_id;/* peripheral id */
struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
};
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
static unsigned port_count; /* Number of available ports */
/*
* This table has USB timing parameters for each Oscillator frequency we
* support. There are four sets of values:
*
* 1. PLLU configuration information (reference clock is osc/clk_m and
* PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
*
* Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
* ----------------------------------------------------------------------
* DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
* DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
* Filter frequency (MHz) 1 4.8 6 2
* CPCON 1100b 0011b 1100b 1100b
* LFCON0 0 0 0 0
*
* 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
*
* Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
* ---------------------------------------------------------------------------
* PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
* PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
* PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
* XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
*
* 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
* SessEnd. Each of these signals have their own debouncer and for each of
* those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
* BIAS_DEBOUNCE_B).
*
* The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
* 0xffff -> No debouncing at all
* <n> ms = <n> *1000 / (1/19.2MHz) / 4
*
* So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
* BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
*
* We need to use only DebounceA for BOOTROM. We don't need the DebounceB
* values, so we can keep those to default.
*
* 4. The 20 microsecond delay after bias cell operation.
*/
static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
/* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
{ 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
{ 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
{ 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
{ 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
};
/* UTMIP Idle Wait Delay */
static const u8 utmip_idle_wait_delay = 17;
/* UTMIP Elastic limit */
static const u8 utmip_elastic_limit = 16;
/* UTMIP High Speed Sync Start Delay */
static const u8 utmip_hs_sync_start_delay = 9;
/* Put the port into host mode */
static void set_host_mode(struct fdt_usb *config)
{
/*
* If we are an OTG port, check if remote host is driving VBus and
* bail out in this case.
*/
if (config->dr_mode == DR_MODE_OTG &&
(readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
return;
/*
* If not driving, we set the GPIO to enable VBUS. We assume
* that the pinmux is set up correctly for this.
*/
if (fdt_gpio_isvalid(&config->vbus_gpio)) {
fdtdec_setup_gpio(&config->vbus_gpio);
gpio_direction_output(config->vbus_gpio.gpio,
(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
0 : 1);
debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
"low" : "high");
}
}
void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
{
/* Reset the USB controller with 2us delay */
reset_periph(config->periph_id, 2);
/*
* Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
* base address
*/
if (config->has_legacy_mode)
setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
/* Put UTMIP1/3 in reset */
setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
/* Enable the UTMIP PHY */
if (config->utmi)
setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
/*
* TODO: where do we take the USB1 out of reset? The old code would
* take USB3 out of reset, but not USB1. This code doesn't do either.
*/
}
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr, const u32 timing[])
{
u32 val;
int loop_count;
clock_enable(config->periph_id);
/* Reset the usb controller */
usbf_reset_controller(config, usbctlr);
/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
*/
if (fdt_gpio_isvalid(&config->vbus_gpio)) {
clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
VBUS_SENSE_CTL_MASK,
VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
}
/*
* PLL Delay CONFIGURATION settings. The following parameters control
* the bring up of the plls.
*/
val = readl(&usbctlr->utmip_misc_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &usbctlr->utmip_misc_cfg1);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&usbctlr->utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &usbctlr->utmip_pll_cfg1);
/* Setting the tracking length time */
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_PDTRK_COUNT_MASK,
timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
/* Program debounce time for VBUS to become valid */
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
/* Disable battery charge enabling bit */
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
* Setting these fields, together with default values of the
* other fields, results in programming the registers below as
* follows:
* UTMIP_HSRX_CFG0 = 0x9168c000
* UTMIP_HSRX_CFG1 = 0x13
*/
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Finished the per-controller init. */
/* De-assert UTMIP_RESET to bring out of reset. */
clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
/* Wait for the phy clock to become valid in 100 ms */
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
/* Disable ICUSB FS/LS transceiver */
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
return 0;
}
#ifdef CONFIG_USB_ULPI
/* if board file does not set a ULPI reference frequency we default to 24MHz */
#ifndef CONFIG_ULPI_REF_CLK
#define CONFIG_ULPI_REF_CLK 24000000
#endif
/* set up the ULPI USB controller with the parameters provided */
static int init_ulpi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr)
{
u32 val;
int loop_count;
struct ulpi_viewport ulpi_vp;
/* set up ULPI reference clock on pllp_out4 */
clock_enable(PERIPH_ID_DEV2_OUT);
clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
/* reset ULPI phy */
if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
fdtdec_setup_gpio(&config->phy_reset_gpio);
gpio_direction_output(config->phy_reset_gpio.gpio, 0);
mdelay(5);
gpio_set_value(config->phy_reset_gpio.gpio, 1);
}
/* Reset the usb controller */
clock_enable(config->periph_id);
usbf_reset_controller(config, usbctlr);
/* enable pinmux bypass */
setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
/* configure ULPI transceiver timings */
val = 0;
writel(val, &usbctlr->ulpi_timing_ctrl_1);
val |= ULPI_DATA_TRIMMER_SEL(4);
val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
val |= ULPI_DIR_TRIMMER_SEL(4);
writel(val, &usbctlr->ulpi_timing_ctrl_1);
udelay(10);
val |= ULPI_DATA_TRIMMER_LOAD;
val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
val |= ULPI_DIR_TRIMMER_LOAD;
writel(val, &usbctlr->ulpi_timing_ctrl_1);
/* set up phy for host operation with external vbus supply */
ulpi_vp.port_num = 0;
ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
if (ulpi_init(&ulpi_vp)) {
printf("Tegra ULPI viewport init failed\n");
return -1;
}
ulpi_set_vbus(&ulpi_vp, 1, 1);
ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
/* enable wakeup events */
setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
/* Enable and wait for the phy clock to become valid in 100 ms */
setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
return 0;
}
#else
static int init_ulpi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr)
{
printf("No code to set up ULPI controller, please enable"
"CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
return -1;
}
#endif
static void config_clock(const u32 timing[])
{
clock_start_pll(CLOCK_ID_USB,
timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
timing[PARAM_CPCON], timing[PARAM_LFCON]);
}
/**
* Add a new USB port to the list of available ports.
*
* @param config USB port configuration
* @return 0 if ok, -1 if error (too many ports)
*/
static int add_port(struct fdt_usb *config, const u32 timing[])
{
struct usb_ctlr *usbctlr = config->reg;
if (port_count == USB_PORTS_MAX) {
printf("tegrausb: Cannot register more than %d ports\n",
USB_PORTS_MAX);
return -1;
}
if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
printf("tegrausb: Cannot init port\n");
return -1;
}
if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
printf("tegrausb: Cannot init port\n");
return -1;
}
port[port_count++] = *config;
return 0;
}
int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
{
struct usb_ctlr *usbctlr;
if (portnum >= port_count)
return -1;
set_host_mode(&port[portnum]);
usbctlr = port[portnum].reg;
*hccr = (u32)&usbctlr->cap_length;
*hcor = (u32)&usbctlr->usb_cmd;
return 0;
}
int tegrausb_stop_port(int portnum)
{
struct usb_ctlr *usbctlr;
usbctlr = port[portnum].reg;
/* Stop controller */
writel(0, &usbctlr->usb_cmd);
udelay(1000);
/* Initiate controller reset */
writel(2, &usbctlr->usb_cmd);
udelay(1000);
return 0;
}
int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
struct fdt_usb *config)
{
const char *phy, *mode;
config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
mode = fdt_getprop(blob, node, "dr_mode", NULL);
if (mode) {
if (0 == strcmp(mode, "host"))
config->dr_mode = DR_MODE_HOST;
else if (0 == strcmp(mode, "peripheral"))
config->dr_mode = DR_MODE_DEVICE;
else if (0 == strcmp(mode, "otg"))
config->dr_mode = DR_MODE_OTG;
else {
debug("%s: Cannot decode dr_mode '%s'\n", __func__,
mode);
return -FDT_ERR_NOTFOUND;
}
} else {
config->dr_mode = DR_MODE_HOST;
}
phy = fdt_getprop(blob, node, "phy_type", NULL);
config->utmi = phy && 0 == strcmp("utmi", phy);
config->ulpi = phy && 0 == strcmp("ulpi", phy);
config->enabled = fdtdec_get_is_enabled(blob, node);
config->has_legacy_mode = fdtdec_get_bool(blob, node,
"nvidia,has-legacy-mode");
config->periph_id = clock_decode_periph_id(blob, node);
if (config->periph_id == PERIPH_ID_NONE) {
debug("%s: Missing/invalid peripheral ID\n", __func__);
return -FDT_ERR_NOTFOUND;
}
fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
&config->phy_reset_gpio);
debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
"vbus=%d, phy_reset=%d, dr_mode=%d\n",
config->enabled, config->has_legacy_mode, config->utmi,
config->ulpi, config->periph_id, config->vbus_gpio.gpio,
config->phy_reset_gpio.gpio, config->dr_mode);
return 0;
}
int board_usb_init(const void *blob)
{
struct fdt_usb config;
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
enum clock_osc_freq freq;
int node_list[USB_PORTS_MAX];
int node, count, i;
/* Set up the USB clocks correctly based on our oscillator frequency */
freq = clock_get_osc_freq();
config_clock(usb_pll[freq]);
/* count may return <0 on error */
count = fdtdec_find_aliases_for_id(blob, "usb",
COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
for (i = 0; i < count; i++) {
debug("USB %d: ", i);
node = node_list[i];
if (!node)
continue;
if (fdt_decode_usb(blob, node, osc_freq, &config)) {
debug("Cannot decode USB node %s\n",
fdt_get_name(blob, node, NULL));
return -1;
}
if (add_port(&config, usb_pll[freq]))
return -1;
set_host_mode(&config);
}
return 0;
}

1
arch/arm/cpu/armv7/zynq/Makefile
View File

@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-y := timer.o
COBJS-y += cpu.o
COBJS-y += slcr.o
COBJS := $(COBJS-y)

28
arch/arm/cpu/armv7/zynq/cpu.c
View File

@ -21,11 +21,37 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
inline void lowlevel_init(void) {}
void lowlevel_init(void)
{
zynq_slcr_unlock();
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl);
/* TZ_DDR_RAM, Set DDR trust zone non-secure */
writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
zynq_slcr_lock();
}
void reset_cpu(ulong addr)
{
zynq_slcr_cpu_reset();
while (1)
;
}

63
arch/arm/cpu/armv7/zynq/slcr.c Normal file
View File

@ -0,0 +1,63 @@
/*
* Copyright (c) 2013 Xilinx Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
{
if (!slcr_lock)
writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
}
void zynq_slcr_unlock(void)
{
if (slcr_lock)
writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
}
/* Reset the entire system */
void zynq_slcr_cpu_reset(void)
{
/*
* Unlock the SLCR then reset the system.
* Note that this seems to require raw i/o
* functions or there's a lockup?
*/
zynq_slcr_unlock();
/*
* Clear 0x0F000000 bits of reboot status register to workaround
* the FSBL not loading the bitstream after soft-reboot
* This is a temporary solution until we know more.
*/
clrbits_le32(&slcr_base->reboot_status, 0xF000000);
writel(1, &slcr_base->pss_rst_ctrl);
}

14
arch/arm/cpu/ixp/u-boot.lds
View File

@ -49,7 +49,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
@ -67,11 +67,17 @@ SECTIONS
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
}
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_end = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

410
arch/arm/cpu/tegra114-common/pinmux.c
View File

@ -37,6 +37,20 @@ struct tegra_pingroup_desc {
#define PMUX_OD_SHIFT 6
#define PMUX_LOCK_SHIFT 7
#define PMUX_IO_RESET_SHIFT 8
#define PMUX_RCV_SEL_SHIFT 9
#define PGRP_HSM_SHIFT 2
#define PGRP_SCHMT_SHIFT 3
#define PGRP_LPMD_SHIFT 4
#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
#define PGRP_DRVDN_SHIFT 12
#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
#define PGRP_DRVUP_SHIFT 20
#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
#define PGRP_SLWR_SHIFT 28
#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
#define PGRP_SLWF_SHIFT 30
#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
@ -58,6 +72,10 @@ struct tegra_pingroup_desc {
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
/* A pin group number which is not used */
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
@ -84,71 +102,71 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
PINI(GPIO_PV2, BB, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PV3, BB, RSVD1, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
PIN_RESERVED,
PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
PINO(LCD_PWR1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_PWR2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_SDIN, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_SDOUT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_WR_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_CS0_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_DC0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_SCK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_PWR0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_PCLK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_DE, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D3, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D4, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D5, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D6, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D7, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D8, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D9, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D10, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D11, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D12, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D13, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D14, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D15, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D16, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D17, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D18, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D19, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D20, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D21, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D22, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_D23, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_CS1_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_M1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINO(LCD_DC1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
PINI(CRT_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(CRT_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D0, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D1, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D2, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D3, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D4, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D5, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D6, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D7, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D8, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D9, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D10, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_D11, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_PCLK, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_MCLK, VI, RSVD1, RSVD3, RSVD3, RSVD4),
PINI(VI_VSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(VI_HSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
@ -220,8 +238,8 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
PINI(SDMMC4_RST_N, SDMMC4, RSVD1, RSVD2, RSVD3, SDMMC4),
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3280 */
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
@ -246,11 +264,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
PINI(KB_ROW11, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(KB_ROW12, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(KB_ROW13, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(KB_ROW14, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(KB_ROW15, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
@ -278,36 +296,46 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
PINI(SPI2_MOSI, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
PINI(SPI2_MISO, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
PINI(SPI2_CS0_N, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
PINI(SPI2_SCK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
PINI(SPI1_MOSI, AUDIO, RSVD1, SPI1, SPI2, DAP2),
PINI(SPI1_SCK, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
PINI(SPI1_CS0_N, AUDIO, SPI6, SPI1, SPI2, RSVD4),
PINI(SPI1_MISO, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
PINI(SPI2_CS1_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(SPI2_CS2_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
PIN_RESERVED,
PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
PINI(SDMMC3_DAT4, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_DAT5, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_DAT6, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_DAT7, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PIN_RESERVED,
PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
PINI(SDMMC3_CD_N, SDMMC3, SDMMC3, OWR, RSVD3, RSVD4),
PINI(SPI1_CS1_N, AUDIO, SPI6, RSVD2, SPI2, I2C1),
PINI(SPI1_CS2_N, AUDIO, SPI6, SPI1, SPI2, I2C1),
PINI(USB_VBUS_EN0, SYS, USB, RSVD2, RSVD3, RSVD4),
PINI(USB_VBUS_EN1, SYS, USB, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
PINO(NAND_GMI_CLK_LB, GMI, SDMMC2, NAND, GMI, RSVD4),
PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
@ -484,6 +512,30 @@ static int pinmux_set_ioreset(enum pmux_pingrp pin,
return 0;
}
static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
enum pmux_pin_rcv_sel rcv_sel)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and rcv_sel */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
return 0;
reg = readl(pin_rcv_sel);
reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
writel(reg, pin_rcv_sel);
return 0;
}
void pinmux_config_pingroup(struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
@ -495,6 +547,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
pinmux_set_lock(pin, config->lock);
pinmux_set_od(pin, config->od);
pinmux_set_ioreset(pin, config->ioreset);
pinmux_set_rcv_sel(pin, config->rcv_sel);
}
void pinmux_config_table(struct pingroup_config *config, int len)
@ -504,3 +557,184 @@ void pinmux_config_table(struct pingroup_config *config, int len)
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwf = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwf */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwf));
/* NONE means unspecified/do not change/use POR value */
if (slwf == PGRP_SLWF_NONE)
return 0;
reg = readl(pad_slwf);
reg &= ~PGRP_SLWF_MASK;
reg |= (slwf << PGRP_SLWF_SHIFT);
writel(reg, pad_slwf);
return 0;
}
static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwr = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwr */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwr));
/* NONE means unspecified/do not change/use POR value */
if (slwr == PGRP_SLWR_NONE)
return 0;
reg = readl(pad_slwr);
reg &= ~PGRP_SLWR_MASK;
reg |= (slwr << PGRP_SLWR_SHIFT);
writel(reg, pad_slwr);
return 0;
}
static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvup = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvup */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvup));
/* NONE means unspecified/do not change/use POR value */
if (drvup == PGRP_DRVUP_NONE)
return 0;
reg = readl(pad_drvup);
reg &= ~PGRP_DRVUP_MASK;
reg |= (drvup << PGRP_DRVUP_SHIFT);
writel(reg, pad_drvup);
return 0;
}
static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvdn = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvdn */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvdn));
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PGRP_DRVDN_NONE)
return 0;
reg = readl(pad_drvdn);
reg &= ~PGRP_DRVDN_MASK;
reg |= (drvdn << PGRP_DRVDN_SHIFT);
writel(reg, pad_drvdn);
return 0;
}
static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_lpmd = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad and lpmd value */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_lpmd_isvalid(lpmd));
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PGRP_LPMD_NONE)
return 0;
reg = readl(pad_lpmd);
reg &= ~PGRP_LPMD_MASK;
reg |= (lpmd << PGRP_LPMD_SHIFT);
writel(reg, pad_lpmd);
return 0;
}
static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_schmt = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
/* NONE means unspecified/do not change/use POR value */
if (schmt == PGRP_SCHMT_NONE)
return 0;
reg = readl(pad_schmt);
reg &= ~(1 << PGRP_SCHMT_SHIFT);
if (schmt == PGRP_SCHMT_ENABLE)
reg |= (0x1 << PGRP_SCHMT_SHIFT);
writel(reg, pad_schmt);
return 0;
}
static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_hsm = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
/* NONE means unspecified/do not change/use POR value */
if (hsm == PGRP_HSM_NONE)
return 0;
reg = readl(pad_hsm);
reg &= ~(1 << PGRP_HSM_SHIFT);
if (hsm == PGRP_HSM_ENABLE)
reg |= (0x1 << PGRP_HSM_SHIFT);
writel(reg, pad_hsm);
return 0;
}
void padctrl_config_pingroup(struct padctrl_config *config)
{
enum pdrive_pingrp pad = config->padgrp;
padgrp_set_drvup_slwf(pad, config->slwf);
padgrp_set_drvdn_slwr(pad, config->slwr);
padgrp_set_drvup(pad, config->drvup);
padgrp_set_drvdn(pad, config->drvdn);
padgrp_set_lpmd(pad, config->lpmd);
padgrp_set_schmt(pad, config->schmt);
padgrp_set_hsm(pad, config->hsm);
}
void padgrp_config_table(struct padctrl_config *config, int len)
{
int i;
for (i = 0; i < len; i++)
padctrl_config_pingroup(&config[i]);
}

190
arch/arm/cpu/tegra30-common/pinmux.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@ -38,6 +38,19 @@ struct tegra_pingroup_desc {
#define PMUX_LOCK_SHIFT 7
#define PMUX_IO_RESET_SHIFT 8
#define PGRP_HSM_SHIFT 2
#define PGRP_SCHMT_SHIFT 3
#define PGRP_LPMD_SHIFT 4
#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
#define PGRP_DRVDN_SHIFT 12
#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
#define PGRP_DRVUP_SHIFT 20
#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
#define PGRP_SLWR_SHIFT 28
#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
#define PGRP_SLWF_SHIFT 30
#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
@ -504,3 +517,178 @@ void pinmux_config_table(struct pingroup_config *config, int len)
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
}
static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
int slwf)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwf = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwf */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwf));
/* NONE means unspecified/do not change/use POR value */
if (slwf == PGRP_SLWF_NONE)
return 0;
reg = readl(pad_slwf);
reg &= ~PGRP_SLWF_MASK;
reg |= (slwf << PGRP_SLWF_SHIFT);
writel(reg, pad_slwf);
return 0;
}
static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_slwr = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and slwr */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_slw_isvalid(slwr));
/* NONE means unspecified/do not change/use POR value */
if (slwr == PGRP_SLWR_NONE)
return 0;
reg = readl(pad_slwr);
reg &= ~PGRP_SLWR_MASK;
reg |= (slwr << PGRP_SLWR_SHIFT);
writel(reg, pad_slwr);
return 0;
}
static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvup = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvup */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvup));
/* NONE means unspecified/do not change/use POR value */
if (drvup == PGRP_DRVUP_NONE)
return 0;
reg = readl(pad_drvup);
reg &= ~PGRP_DRVUP_MASK;
reg |= (drvup << PGRP_DRVUP_SHIFT);
writel(reg, pad_drvup);
return 0;
}
static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_drvdn = &pmt->pmt_drive[pad];
u32 reg;
/* Error check on pad and drvdn */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_drv_isvalid(drvdn));
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PGRP_DRVDN_NONE)
return 0;
reg = readl(pad_drvdn);
reg &= ~PGRP_DRVDN_MASK;
reg |= (drvdn << PGRP_DRVDN_SHIFT);
writel(reg, pad_drvdn);
return 0;
}
static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_lpmd = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad and lpmd value */
assert(pmux_padgrp_isvalid(pad));
assert(pmux_pad_lpmd_isvalid(lpmd));
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PGRP_LPMD_NONE)
return 0;
reg = readl(pad_lpmd);
reg &= ~PGRP_LPMD_MASK;
reg |= (lpmd << PGRP_LPMD_SHIFT);
writel(reg, pad_lpmd);
return 0;
}
static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_schmt = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
reg = readl(pad_schmt);
reg &= ~(1 << PGRP_SCHMT_SHIFT);
if (schmt == PGRP_SCHMT_ENABLE)
reg |= (0x1 << PGRP_SCHMT_SHIFT);
writel(reg, pad_schmt);
return 0;
}
static int padgrp_set_hsm(enum pdrive_pingrp pad,
enum pgrp_hsm hsm)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pad_hsm = &pmt->pmt_drive[pad];
u32 reg;
/* Error check pad */
assert(pmux_padgrp_isvalid(pad));
reg = readl(pad_hsm);
reg &= ~(1 << PGRP_HSM_SHIFT);
if (hsm == PGRP_HSM_ENABLE)
reg |= (0x1 << PGRP_HSM_SHIFT);
writel(reg, pad_hsm);
return 0;
}
void padctrl_config_pingroup(struct padctrl_config *config)
{
enum pdrive_pingrp pad = config->padgrp;
padgrp_set_drvup_slwf(pad, config->slwf);
padgrp_set_drvdn_slwr(pad, config->slwr);
padgrp_set_drvup(pad, config->drvup);
padgrp_set_drvdn(pad, config->drvdn);
padgrp_set_lpmd(pad, config->lpmd);
padgrp_set_schmt(pad, config->schmt);
padgrp_set_hsm(pad, config->hsm);
}
void padgrp_config_table(struct padctrl_config *config, int len)
{
int i;
for (i = 0; i < len; i++)
padctrl_config_pingroup(&config[i]);
}

93
arch/arm/cpu/u-boot-spl.lds Normal file
View File

@ -0,0 +1,93 @@
/*
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
__image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
. = .;
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
}
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#endif

15
arch/arm/cpu/u-boot.lds
View File

@ -52,7 +52,7 @@ SECTIONS
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
@ -81,11 +81,18 @@ SECTIONS
*(.mmutable)
}
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
}
.bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_end = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

75
arch/arm/dts/tegra114.dtsi
View File

@ -1,5 +1,78 @@
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra114";
tegra_car: clock {
compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
gpio: gpio {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04
0 125 0x04>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
i2c@7000c000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
};

18
arch/arm/dts/tegra20.dtsi
View File

@ -1,4 +1,4 @@
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
@ -318,24 +318,32 @@
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = < 46 >;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
status = "disabled";
};
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = < 47 >;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
status = "disabled";
};
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = < 51 >;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
status = "disabled";
};
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = < 63 >;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
status = "disabled";
};
};

124
arch/arm/dts/tegra30.dtsi
View File

@ -1,10 +1,10 @@
/include/ "skeleton.dtsi"
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra30";
tegra_car: clock@60006000 {
compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
tegra_car: clock {
compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
@ -44,51 +44,79 @@
0 141 0x04
0 142 0x04
0 143 0x04>;
clocks = <&tegra_car 34>;
};
gpio: gpio {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04
0 125 0x04>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C000 0x100>;
/* PERIPH_ID_I2C1, CLK_M */
clocks = <&tegra_car 12>;
clocks = <&tegra_car 12>, <&tegra_car 182>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C400 0x100>;
/* PERIPH_ID_I2C2, CLK_M */
clocks = <&tegra_car 54>;
clocks = <&tegra_car 54>, <&tegra_car 182>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C500 0x100>;
/* PERIPH_ID_I2C3, CLK_M */
clocks = <&tegra_car 67>;
clocks = <&tegra_car 67>, <&tegra_car 182>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000C700 0x100>;
/* PERIPH_ID_I2C4, CLK_M */
clocks = <&tegra_car 103>;
clocks = <&tegra_car 103>, <&tegra_car 182>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000D000 0x100>;
/* PERIPH_ID_I2C_DVC, CLK_M */
clocks = <&tegra_car 47>;
clocks = <&tegra_car 47>, <&tegra_car 182>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
spi@7000d400 {
@ -98,9 +126,8 @@
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC1, PLLP_OUT0 */
clocks = <&tegra_car 41>;
status = "disabled";
};
spi@7000d600 {
@ -110,9 +137,8 @@
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC2, PLLP_OUT0 */
clocks = <&tegra_car 44>;
status = "disabled";
};
spi@7000d800 {
@ -122,9 +148,8 @@
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC3, PLLP_OUT0 */
clocks = <&tegra_car 46>;
status = "disabled";
};
spi@7000da00 {
@ -134,9 +159,8 @@
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC4, PLLP_OUT0 */
clocks = <&tegra_car 68>;
status = "disabled";
};
spi@7000dc00 {
@ -146,9 +170,8 @@
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC5, PLLP_OUT0 */
clocks = <&tegra_car 104>;
status = "disabled";
};
spi@7000de00 {
@ -158,8 +181,39 @@
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* PERIPH_ID_SBC6, PLLP_OUT0 */
clocks = <&tegra_car 105>;
status = "disabled";
};
sdhci@78000000 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
status = "disabled";
};
sdhci@78000200 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
status = "disabled";
};
sdhci@78000400 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
status = "disabled";
};
sdhci@78000600 {
compatible = "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
status = "disabled";
};
};

140
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
View File

@ -16,148 +16,12 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
#include <asm/omap_mmc.h>
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x48060100
#define OMAP_HSMMC2_BASE 0x481D8100
typedef struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
} hsmmc_t;
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */

1
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -29,6 +29,7 @@
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif

2
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -35,5 +35,7 @@ void ddr_pll_config(unsigned int ddrpll_M);
void sdelay(unsigned long);
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
void omap_nand_switch_ecc(int);
#endif

6
arch/arm/include/asm/arch-at91/at91sam9x5.h
View File

@ -140,12 +140,6 @@
/*
* Cpu Name
*/
#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
#define ATMEL_CPU_NAME get_cpu_name()
/*

7
arch/arm/include/asm/arch-davinci/gpio.h
View File

@ -65,15 +65,16 @@ struct davinci_gpio_bank {
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
#define MAX_NUM_GPIOS 70
#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
#endif
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
#define GPIO_BIT(gp) ((gp) & 0x1F)

2
arch/arm/include/asm/arch-mx35/spl.h
View File

@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
#define BOOT_DEVICE_ONE_NAND 4
#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7

12
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@ -20,6 +20,17 @@
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define CCM_CCGR0 0x020C4068
#define CCM_CCGR1 0x020C406c
#define CCM_CCGR2 0x020C4070
#define CCM_CCGR3 0x020C4074
#define CCM_CCGR4 0x020C4078
#define CCM_CCGR5 0x020C407c
#define CCM_CCGR6 0x020C4080
#define PMU_MISC2 0x020C8170
#ifndef __ASSEMBLY__
struct mxc_ccm_reg {
u32 ccr; /* 0x0000 */
u32 ccdr;
@ -105,6 +116,7 @@ struct mxc_ccm_reg {
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
};
#endif
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)

8
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -601,5 +601,13 @@ struct iomuxc_base_regs {
u32 daisy[104]; /* 0x7b0..94c */
};
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Miscellaneous Control */
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

5
arch/arm/include/asm/arch-mx6/iomux.h
View File

@ -16,6 +16,11 @@
#ifndef __ASM_ARCH_IOMUX_H__
#define __ASM_ARCH_IOMUX_H__
#define MX6_IOMUXC_GPR4 0x020e0010
#define MX6_IOMUXC_GPR6 0x020e0018
#define MX6_IOMUXC_GPR7 0x020e001c
/*
* IOMUXC_GPR13 bit fields
*/

85
arch/arm/include/asm/arch-mx6/mx6-ddr.h Normal file
View File

@ -0,0 +1,85 @@
/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
#define MX6_MMDC_P0_MDOTC 0x021b0008
#define MX6_MMDC_P0_MDCFG0 0x021b000c
#define MX6_MMDC_P0_MDCFG1 0x021b0010
#define MX6_MMDC_P0_MDCFG2 0x021b0014
#define MX6_MMDC_P0_MDMISC 0x021b0018
#define MX6_MMDC_P0_MDSCR 0x021b001c
#define MX6_MMDC_P0_MDREF 0x021b0020
#define MX6_MMDC_P0_MDRWD 0x021b002c
#define MX6_MMDC_P0_MDOR 0x021b0030
#define MX6_MMDC_P0_MDASP 0x021b0040
#define MX6_MMDC_P0_MAPSR 0x021b0404
#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
#define MX6_MMDC_P1_MDPDC 0x021b4004
#define MX6_MMDC_P1_MDOTC 0x021b4008
#define MX6_MMDC_P1_MDCFG0 0x021b400c
#define MX6_MMDC_P1_MDCFG1 0x021b4010
#define MX6_MMDC_P1_MDCFG2 0x021b4014
#define MX6_MMDC_P1_MDMISC 0x021b4018
#define MX6_MMDC_P1_MDSCR 0x021b401c
#define MX6_MMDC_P1_MDREF 0x021b4020
#define MX6_MMDC_P1_MDRWD 0x021b402c
#define MX6_MMDC_P1_MDOR 0x021b4030
#define MX6_MMDC_P1_MDASP 0x021b4040
#define MX6_MMDC_P1_MAPSR 0x021b4404
#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */

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arch/arm/include/asm/arch-mx6/mx6-pins.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
#ifdef CONFIG_MX6Q
#include "mx6q_pins.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#endif /*__ASM_ARCH_MX6_PINS_H__ */

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/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __ASM_ARCH_MX6DLS_DDR_H__
#define __ASM_ARCH_MX6DLS_DDR_H__
#ifndef CONFIG_MX6DL
#ifndef CONFIG_MX6S
#error "wrong CPU"
#endif
#endif
#define MX6_IOM_DRAM_DQM0 0x020e0470
#define MX6_IOM_DRAM_DQM1 0x020e0474
#define MX6_IOM_DRAM_DQM2 0x020e0478
#define MX6_IOM_DRAM_DQM3 0x020e047c
#define MX6_IOM_DRAM_DQM4 0x020e0480
#define MX6_IOM_DRAM_DQM5 0x020e0484
#define MX6_IOM_DRAM_DQM6 0x020e0488
#define MX6_IOM_DRAM_DQM7 0x020e048c
#define MX6_IOM_DRAM_CAS 0x020e0464
#define MX6_IOM_DRAM_RAS 0x020e0490
#define MX6_IOM_DRAM_RESET 0x020e0494
#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
#define MX6_IOM_DRAM_SDBA2 0x020e04a0
#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
#define MX6_IOM_DRAM_SDODT0 0x020e04b4
#define MX6_IOM_DRAM_SDODT1 0x020e04b8
#define MX6_IOM_DRAM_SDQS0 0x020e04bc
#define MX6_IOM_DRAM_SDQS1 0x020e04c0
#define MX6_IOM_DRAM_SDQS2 0x020e04c4
#define MX6_IOM_DRAM_SDQS3 0x020e04c8
#define MX6_IOM_DRAM_SDQS4 0x020e04cc
#define MX6_IOM_DRAM_SDQS5 0x020e04d0
#define MX6_IOM_DRAM_SDQS6 0x020e04d4
#define MX6_IOM_DRAM_SDQS7 0x020e04d8
#define MX6_IOM_GRP_B0DS 0x020e0764
#define MX6_IOM_GRP_B1DS 0x020e0770
#define MX6_IOM_GRP_B2DS 0x020e0778
#define MX6_IOM_GRP_B3DS 0x020e077c
#define MX6_IOM_GRP_B4DS 0x020e0780
#define MX6_IOM_GRP_B5DS 0x020e0784
#define MX6_IOM_GRP_B6DS 0x020e078c
#define MX6_IOM_GRP_B7DS 0x020e0748
#define MX6_IOM_GRP_ADDDS 0x020e074c
#define MX6_IOM_DDRMODE_CTL 0x020e0750
#define MX6_IOM_GRP_DDRPKE 0x020e0754
#define MX6_IOM_GRP_DDRMODE 0x020e0760
#define MX6_IOM_GRP_CTLDS 0x020e076c
#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
#endif /*__ASM_ARCH_MX6S_DDR_H__ */

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arch/arm/include/asm/arch-mx6/mx6dl_pins.h
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@ -50,100 +50,103 @@
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */

69
arch/arm/include/asm/arch-mx6/mx6q-ddr.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (C) 2013 Boundary Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __ASM_ARCH_MX6Q_DDR_H__
#define __ASM_ARCH_MX6Q_DDR_H__
#ifndef CONFIG_MX6Q
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e05ac
#define MX6_IOM_DRAM_DQM1 0x020e05b4
#define MX6_IOM_DRAM_DQM2 0x020e0528
#define MX6_IOM_DRAM_DQM3 0x020e0520
#define MX6_IOM_DRAM_DQM4 0x020e0514
#define MX6_IOM_DRAM_DQM5 0x020e0510
#define MX6_IOM_DRAM_DQM6 0x020e05bc
#define MX6_IOM_DRAM_DQM7 0x020e05c4
#define MX6_IOM_DRAM_CAS 0x020e056c
#define MX6_IOM_DRAM_RAS 0x020e0578
#define MX6_IOM_DRAM_RESET 0x020e057c
#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
#define MX6_IOM_DRAM_SDBA2 0x020e058c
#define MX6_IOM_DRAM_SDCKE0 0x020e0590
#define MX6_IOM_DRAM_SDCKE1 0x020e0598
#define MX6_IOM_DRAM_SDODT0 0x020e059c
#define MX6_IOM_DRAM_SDODT1 0x020e05a0
#define MX6_IOM_DRAM_SDQS0 0x020e05a8
#define MX6_IOM_DRAM_SDQS1 0x020e05b0
#define MX6_IOM_DRAM_SDQS2 0x020e0524
#define MX6_IOM_DRAM_SDQS3 0x020e051c
#define MX6_IOM_DRAM_SDQS4 0x020e0518
#define MX6_IOM_DRAM_SDQS5 0x020e050c
#define MX6_IOM_DRAM_SDQS6 0x020e05b8
#define MX6_IOM_DRAM_SDQS7 0x020e05c0
#define MX6_IOM_GRP_B0DS 0x020e0784
#define MX6_IOM_GRP_B1DS 0x020e0788
#define MX6_IOM_GRP_B2DS 0x020e0794
#define MX6_IOM_GRP_B3DS 0x020e079c
#define MX6_IOM_GRP_B4DS 0x020e07a0
#define MX6_IOM_GRP_B5DS 0x020e07a4
#define MX6_IOM_GRP_B6DS 0x020e07a8
#define MX6_IOM_GRP_B7DS 0x020e0748
#define MX6_IOM_GRP_ADDDS 0x020e074c
#define MX6_IOM_DDRMODE_CTL 0x020e0750
#define MX6_IOM_GRP_DDRPKE 0x020e0758
#define MX6_IOM_GRP_DDRMODE 0x020e0774
#define MX6_IOM_GRP_CTLDS 0x020e078c
#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
#endif /*__ASM_ARCH_MX6Q_DDR_H__ */

1671
arch/arm/include/asm/arch-mx6/mx6q_pins.h Normal file
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File diff suppressed because it is too large Load Diff

1671
arch/arm/include/asm/arch-mx6/mx6x_pins.h
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File diff suppressed because it is too large Load Diff

1083
arch/arm/include/asm/arch-mx6/mxc_hdmi.h
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File diff suppressed because it is too large Load Diff

19
arch/arm/include/asm/arch-mxs/dma.h
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@ -40,6 +40,19 @@
/*
* MXS DMA channels
*/
#if defined(CONFIG_MX23)
enum {
MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
@ -53,9 +66,13 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
MXS_DMA_CHANNEL_AHB_APBH_SSP,
MXS_DMA_CHANNEL_AHB_APBH_HSADC,
MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
#endif
/*
* MXS DMA hardware command.

2
arch/arm/include/asm/arch-mxs/imx-regs.h
View File

@ -36,6 +36,8 @@
#include <asm/arch/regs-rtc.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
#include <asm/arch/regs-usb.h>
#include <asm/arch/regs-usbphy.h>
#ifdef CONFIG_MX23
#include <asm/arch/regs-clkctrl-mx23.h>

5
arch/arm/include/asm/arch-mxs/iomux.h
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@ -21,6 +21,10 @@
#ifndef __MACH_MXS_IOMUX_H__
#define __MACH_MXS_IOMUX_H__
#ifndef __ASSEMBLY__
#include <asm/types.h>
/*
* IOMUX/PAD Bit field definitions
*
@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad);
*/
int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
#endif /* __ASSEMBLY__ */
#endif /* __MACH_MXS_IOMUX_H__*/

26
arch/arm/include/asm/arch-mxs/regs-ssp.h
View File

@ -74,6 +74,32 @@ struct mxs_ssp_regs {
};
#endif
static inline int mxs_ssp_bus_id_valid(int bus)
{
#if defined(CONFIG_MX23)
const unsigned int mxs_ssp_chan_count = 2;
#elif defined(CONFIG_MX28)
const unsigned int mxs_ssp_chan_count = 4;
#endif
if (bus >= mxs_ssp_chan_count)
return 0;
if (bus < 0)
return 0;
return 1;
}
static inline int mxs_ssp_clock_by_bus(unsigned int clock)
{
#if defined(CONFIG_MX23)
return 0;
#elif defined(CONFIG_MX28)
return clock;
#endif
}
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
{
switch (port) {

101
arch/arm/include/asm/arch-mxs/regs-timrot.h
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@ -31,6 +31,16 @@
struct mxs_timrot_regs {
mxs_reg_32(hw_timrot_rotctrl)
mxs_reg_32(hw_timrot_rotcount)
#if defined(CONFIG_MX23)
mxs_reg_32(hw_timrot_timctrl0)
mxs_reg_32(hw_timrot_timcount0)
mxs_reg_32(hw_timrot_timctrl1)
mxs_reg_32(hw_timrot_timcount1)
mxs_reg_32(hw_timrot_timctrl2)
mxs_reg_32(hw_timrot_timcount2)
mxs_reg_32(hw_timrot_timctrl3)
mxs_reg_32(hw_timrot_timcount3)
#elif defined(CONFIG_MX28)
mxs_reg_32(hw_timrot_timctrl0)
mxs_reg_32(hw_timrot_running_count0)
mxs_reg_32(hw_timrot_fixed_count0)
@ -47,6 +57,7 @@ struct mxs_timrot_regs {
mxs_reg_32(hw_timrot_running_count3)
mxs_reg_32(hw_timrot_fixed_count3)
mxs_reg_32(hw_timrot_match_count3)
#endif
mxs_reg_32(hw_timrot_version)
};
#endif
@ -71,7 +82,11 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
#if defined(CONFIG_MX23)
#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
#endif
#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
@ -79,12 +94,21 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
#if defined(CONFIG_MX23)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4)
#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
#endif
#if defined(CONFIG_MX23)
#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7
#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
#endif
#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
@ -92,18 +116,25 @@ struct mxs_timrot_regs {
#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
#if defined(CONFIG_MX23)
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7
#elif defined(CONFIG_MX28)
#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
#endif
#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
#define TIMROT_TIMCTRLn_IRQ (1 << 15)
#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
#if defined(CONFIG_MX28)
#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
#endif
#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
@ -121,6 +152,15 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
#if defined(CONFIG_MX23)
#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6
#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7
#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8
#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc
#elif defined(CONFIG_MX28)
#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
@ -131,15 +171,28 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
#endif
#if defined(CONFIG_MX23)
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
#elif defined(CONFIG_MX28)
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
#endif
#if defined(CONFIG_MX23)
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
#elif defined(CONFIG_MX28)
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
#endif
#if defined(CONFIG_MX28)
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
#endif
#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
@ -149,6 +202,15 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
#if defined(CONFIG_MX23)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
#elif defined(CONFIG_MX28)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
@ -159,7 +221,46 @@ struct mxs_timrot_regs {
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
#endif
#if defined(CONFIG_MX23)
#define TIMROT_TIMCTRL3_IRQ (1 << 15)
#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14)
#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10)
#endif
#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
#if defined(CONFIG_MX23)
#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8)
#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8
#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8)
#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8)
#define TIMROT_TIMCTRL3_UPDATE (1 << 7)
#define TIMROT_TIMCTRL3_RELOAD (1 << 6)
#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4)
#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4)
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4)
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4)
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4)
#define TIMROT_TIMCTRL3_SELECT_MASK 0xf
#define TIMROT_TIMCTRL3_SELECT_OFFSET 0
#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0
#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1
#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2
#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3
#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4
#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5
#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6
#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7
#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8
#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9
#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa
#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb
#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc
#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff
#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0
#endif
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
#define TIMROT_VERSION_MAJOR_OFFSET 24

31
arch/arm/include/asm/arch-omap3/dss.h
View File

@ -167,6 +167,36 @@ struct venc_regs {
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
/* LCD display type */
#define PASSIVE_DISPLAY 0
#define ACTIVE_DISPLAY 1
/* TFTDATALINES */
#define LCD_INTERFACE_12_BIT 0
#define LCD_INTERFACE_16_BIT 1
#define LCD_INTERFACE_18_BIT 2
#define LCD_INTERFACE_24_BIT 3
/* Polarity */
#define DSS_IVS (1 << 12)
#define DSS_IHS (1 << 13)
#define DSS_IPC (1 << 14)
#define DSS_IEO (1 << 15)
/* GFX format */
#define GFXFORMAT_BITMAP1 (0x0 << 1)
#define GFXFORMAT_BITMAP2 (0x1 << 1)
#define GFXFORMAT_BITMAP4 (0x2 << 1)
#define GFXFORMAT_BITMAP8 (0x3 << 1)
#define GFXFORMAT_RGB12 (0x4 << 1)
#define GFXFORMAT_ARGB16 (0x5 << 1)
#define GFXFORMAT_RGB16 (0x6 << 1)
#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
#define GFXFORMAT_RGB24_PACKED (0x9 << 1)
#define GFXFORMAT_ARGB32 (0xC << 1)
#define GFXFORMAT_RGBA32 (0xD << 1)
#define GFXFORMAT_RGBx32 (0xE << 1)
/* Panel Configuration */
struct panel_config {
u32 timing_h;
@ -178,6 +208,7 @@ struct panel_config {
u32 data_lines;
u32 load_mode;
u32 panel_color;
u32 gfx_format;
void *frame_buffer;
};

139
arch/arm/include/asm/arch-omap3/mmc_host_def.h
View File

@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
#include <asm/omap_mmc.h>
/* T2 Register definitions */
#define T2_BASE 0x48002000
@ -59,142 +61,5 @@ typedef struct t2 {
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
};
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */

2
arch/arm/include/asm/arch-omap3/spl.h
View File

@ -26,7 +26,7 @@
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_NAND 2
#define BOOT_DEVICE_ONE_NAND 3
#define BOOT_DEVICE_ONENAND 3
#define BOOT_DEVICE_MMC2 5 /*emmc*/
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7

562
arch/arm/include/asm/arch-omap4/clocks.h
View File

@ -25,6 +25,7 @@
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
#include <common.h>
#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@ -38,479 +39,6 @@
#define CM_CLKMODE_DPLL_MPU 0x4A004160
#define CM_CLKSEL_CORE 0x4A004100
struct omap4_prcm_regs {
/* cm1.ckgen */
u32 cm_clksel_core;
u32 pad001[1];
u32 cm_clksel_abe;
u32 pad002[1];
u32 cm_dll_ctrl;
u32 pad003[3];
u32 cm_clkmode_dpll_core;
u32 cm_idlest_dpll_core;
u32 cm_autoidle_dpll_core;
u32 cm_clksel_dpll_core;
u32 cm_div_m2_dpll_core;
u32 cm_div_m3_dpll_core;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
u32 cm_div_m6_dpll_core;
u32 cm_div_m7_dpll_core;
u32 cm_ssc_deltamstep_dpll_core;
u32 cm_ssc_modfreqdiv_dpll_core;
u32 cm_emu_override_dpll_core;
u32 pad004[3];
u32 cm_clkmode_dpll_mpu;
u32 cm_idlest_dpll_mpu;
u32 cm_autoidle_dpll_mpu;
u32 cm_clksel_dpll_mpu;
u32 cm_div_m2_dpll_mpu;
u32 pad005[5];
u32 cm_ssc_deltamstep_dpll_mpu;
u32 cm_ssc_modfreqdiv_dpll_mpu;
u32 pad006[3];
u32 cm_bypclk_dpll_mpu;
u32 cm_clkmode_dpll_iva;
u32 cm_idlest_dpll_iva;
u32 cm_autoidle_dpll_iva;
u32 cm_clksel_dpll_iva;
u32 pad007[2];
u32 cm_div_m4_dpll_iva;
u32 cm_div_m5_dpll_iva;
u32 pad008[2];
u32 cm_ssc_deltamstep_dpll_iva;
u32 cm_ssc_modfreqdiv_dpll_iva;
u32 pad009[3];
u32 cm_bypclk_dpll_iva;
u32 cm_clkmode_dpll_abe;
u32 cm_idlest_dpll_abe;
u32 cm_autoidle_dpll_abe;
u32 cm_clksel_dpll_abe;
u32 cm_div_m2_dpll_abe;
u32 cm_div_m3_dpll_abe;
u32 pad010[4];
u32 cm_ssc_deltamstep_dpll_abe;
u32 cm_ssc_modfreqdiv_dpll_abe;
u32 pad011[4];
u32 cm_clkmode_dpll_ddrphy;
u32 cm_idlest_dpll_ddrphy;
u32 cm_autoidle_dpll_ddrphy;
u32 cm_clksel_dpll_ddrphy;
u32 cm_div_m2_dpll_ddrphy;
u32 pad012[1];
u32 cm_div_m4_dpll_ddrphy;
u32 cm_div_m5_dpll_ddrphy;
u32 cm_div_m6_dpll_ddrphy;
u32 pad013[1];
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 pad014[5];
u32 cm_shadow_freq_config1;
u32 pad0141[47];
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
u32 pad015[55];
u32 cm_dsp_clkstctrl;
u32 pad016[7];
u32 cm_dsp_dsp_clkctrl;
/* cm1.abe */
u32 pad017[55];
u32 cm1_abe_clkstctrl;
u32 pad018[7];
u32 cm1_abe_l4abe_clkctrl;
u32 pad019[1];
u32 cm1_abe_aess_clkctrl;
u32 pad020[1];
u32 cm1_abe_pdm_clkctrl;
u32 pad021[1];
u32 cm1_abe_dmic_clkctrl;
u32 pad022[1];
u32 cm1_abe_mcasp_clkctrl;
u32 pad023[1];
u32 cm1_abe_mcbsp1_clkctrl;
u32 pad024[1];
u32 cm1_abe_mcbsp2_clkctrl;
u32 pad025[1];
u32 cm1_abe_mcbsp3_clkctrl;
u32 pad026[1];
u32 cm1_abe_slimbus_clkctrl;
u32 pad027[1];
u32 cm1_abe_timer5_clkctrl;
u32 pad028[1];
u32 cm1_abe_timer6_clkctrl;
u32 pad029[1];
u32 cm1_abe_timer7_clkctrl;
u32 pad030[1];
u32 cm1_abe_timer8_clkctrl;
u32 pad031[1];
u32 cm1_abe_wdt3_clkctrl;
/* cm2.ckgen */
u32 pad032[3805];
u32 cm_clksel_mpu_m3_iss_root;
u32 cm_clksel_usb_60mhz;
u32 cm_scale_fclk;
u32 pad033[1];
u32 cm_core_dvfs_perf1;
u32 cm_core_dvfs_perf2;
u32 cm_core_dvfs_perf3;
u32 cm_core_dvfs_perf4;
u32 pad034[1];
u32 cm_core_dvfs_current;
u32 cm_iva_dvfs_perf_tesla;
u32 cm_iva_dvfs_perf_ivahd;
u32 cm_iva_dvfs_perf_abe;
u32 pad035[1];
u32 cm_iva_dvfs_current;
u32 pad036[1];
u32 cm_clkmode_dpll_per;
u32 cm_idlest_dpll_per;
u32 cm_autoidle_dpll_per;
u32 cm_clksel_dpll_per;
u32 cm_div_m2_dpll_per;
u32 cm_div_m3_dpll_per;
u32 cm_div_m4_dpll_per;
u32 cm_div_m5_dpll_per;
u32 cm_div_m6_dpll_per;
u32 cm_div_m7_dpll_per;
u32 cm_ssc_deltamstep_dpll_per;
u32 cm_ssc_modfreqdiv_dpll_per;
u32 cm_emu_override_dpll_per;
u32 pad037[3];
u32 cm_clkmode_dpll_usb;
u32 cm_idlest_dpll_usb;
u32 cm_autoidle_dpll_usb;
u32 cm_clksel_dpll_usb;
u32 cm_div_m2_dpll_usb;
u32 pad038[5];
u32 cm_ssc_deltamstep_dpll_usb;
u32 cm_ssc_modfreqdiv_dpll_usb;
u32 pad039[1];
u32 cm_clkdcoldo_dpll_usb;
u32 pad040[2];
u32 cm_clkmode_dpll_unipro;
u32 cm_idlest_dpll_unipro;
u32 cm_autoidle_dpll_unipro;
u32 cm_clksel_dpll_unipro;
u32 cm_div_m2_dpll_unipro;
u32 pad041[5];
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
/* cm2.core */
u32 pad0411[324];
u32 cm_l3_1_clkstctrl;
u32 pad042[1];
u32 cm_l3_1_dynamicdep;
u32 pad043[5];
u32 cm_l3_1_l3_1_clkctrl;
u32 pad044[55];
u32 cm_l3_2_clkstctrl;
u32 pad045[1];
u32 cm_l3_2_dynamicdep;
u32 pad046[5];
u32 cm_l3_2_l3_2_clkctrl;
u32 pad047[1];
u32 cm_l3_2_gpmc_clkctrl;
u32 pad048[1];
u32 cm_l3_2_ocmc_ram_clkctrl;
u32 pad049[51];
u32 cm_mpu_m3_clkstctrl;
u32 cm_mpu_m3_staticdep;
u32 cm_mpu_m3_dynamicdep;
u32 pad050[5];
u32 cm_mpu_m3_mpu_m3_clkctrl;
u32 pad051[55];
u32 cm_sdma_clkstctrl;
u32 cm_sdma_staticdep;
u32 cm_sdma_dynamicdep;
u32 pad052[5];
u32 cm_sdma_sdma_clkctrl;
u32 pad053[55];
u32 cm_memif_clkstctrl;
u32 pad054[7];
u32 cm_memif_dmm_clkctrl;
u32 pad055[1];
u32 cm_memif_emif_fw_clkctrl;
u32 pad056[1];
u32 cm_memif_emif_1_clkctrl;
u32 pad057[1];
u32 cm_memif_emif_2_clkctrl;
u32 pad058[1];
u32 cm_memif_dll_clkctrl;
u32 pad059[3];
u32 cm_memif_emif_h1_clkctrl;
u32 pad060[1];
u32 cm_memif_emif_h2_clkctrl;
u32 pad061[1];
u32 cm_memif_dll_h_clkctrl;
u32 pad062[39];
u32 cm_c2c_clkstctrl;
u32 cm_c2c_staticdep;
u32 cm_c2c_dynamicdep;
u32 pad063[5];
u32 cm_c2c_sad2d_clkctrl;
u32 pad064[1];
u32 cm_c2c_modem_icr_clkctrl;
u32 pad065[1];
u32 cm_c2c_sad2d_fw_clkctrl;
u32 pad066[51];
u32 cm_l4cfg_clkstctrl;
u32 pad067[1];
u32 cm_l4cfg_dynamicdep;
u32 pad068[5];
u32 cm_l4cfg_l4_cfg_clkctrl;
u32 pad069[1];
u32 cm_l4cfg_hw_sem_clkctrl;
u32 pad070[1];
u32 cm_l4cfg_mailbox_clkctrl;
u32 pad071[1];
u32 cm_l4cfg_sar_rom_clkctrl;
u32 pad072[49];
u32 cm_l3instr_clkstctrl;
u32 pad073[7];
u32 cm_l3instr_l3_3_clkctrl;
u32 pad074[1];
u32 cm_l3instr_l3_instr_clkctrl;
u32 pad075[5];
u32 cm_l3instr_intrconn_wp1_clkctrl;
/* cm2.ivahd */
u32 pad076[47];
u32 cm_ivahd_clkstctrl;
u32 pad077[7];
u32 cm_ivahd_ivahd_clkctrl;
u32 pad078[1];
u32 cm_ivahd_sl2_clkctrl;
/* cm2.cam */
u32 pad079[53];
u32 cm_cam_clkstctrl;
u32 pad080[7];
u32 cm_cam_iss_clkctrl;
u32 pad081[1];
u32 cm_cam_fdif_clkctrl;
/* cm2.dss */
u32 pad082[53];
u32 cm_dss_clkstctrl;
u32 pad083[7];
u32 cm_dss_dss_clkctrl;
/* cm2.sgx */
u32 pad084[55];
u32 cm_sgx_clkstctrl;
u32 pad085[7];
u32 cm_sgx_sgx_clkctrl;
/* cm2.l3init */
u32 pad086[55];
u32 cm_l3init_clkstctrl;
/* cm2.l3init */
u32 pad087[9];
u32 cm_l3init_hsmmc1_clkctrl;
u32 pad088[1];
u32 cm_l3init_hsmmc2_clkctrl;
u32 pad089[1];
u32 cm_l3init_hsi_clkctrl;
u32 pad090[7];
u32 cm_l3init_hsusbhost_clkctrl;
u32 pad091[1];
u32 cm_l3init_hsusbotg_clkctrl;
u32 pad092[1];
u32 cm_l3init_hsusbtll_clkctrl;
u32 pad093[3];
u32 cm_l3init_p1500_clkctrl;
u32 pad094[21];
u32 cm_l3init_fsusb_clkctrl;
u32 pad095[3];
u32 cm_l3init_usbphy_clkctrl;
/* cm2.l4per */
u32 pad096[7];
u32 cm_l4per_clkstctrl;
u32 pad097[1];
u32 cm_l4per_dynamicdep;
u32 pad098[5];
u32 cm_l4per_adc_clkctrl;
u32 pad100[1];
u32 cm_l4per_gptimer10_clkctrl;
u32 pad101[1];
u32 cm_l4per_gptimer11_clkctrl;
u32 pad102[1];
u32 cm_l4per_gptimer2_clkctrl;
u32 pad103[1];
u32 cm_l4per_gptimer3_clkctrl;
u32 pad104[1];
u32 cm_l4per_gptimer4_clkctrl;
u32 pad105[1];
u32 cm_l4per_gptimer9_clkctrl;
u32 pad106[1];
u32 cm_l4per_elm_clkctrl;
u32 pad107[1];
u32 cm_l4per_gpio2_clkctrl;
u32 pad108[1];
u32 cm_l4per_gpio3_clkctrl;
u32 pad109[1];
u32 cm_l4per_gpio4_clkctrl;
u32 pad110[1];
u32 cm_l4per_gpio5_clkctrl;
u32 pad111[1];
u32 cm_l4per_gpio6_clkctrl;
u32 pad112[1];
u32 cm_l4per_hdq1w_clkctrl;
u32 pad113[1];
u32 cm_l4per_hecc1_clkctrl;
u32 pad114[1];
u32 cm_l4per_hecc2_clkctrl;
u32 pad115[1];
u32 cm_l4per_i2c1_clkctrl;
u32 pad116[1];
u32 cm_l4per_i2c2_clkctrl;
u32 pad117[1];
u32 cm_l4per_i2c3_clkctrl;
u32 pad118[1];
u32 cm_l4per_i2c4_clkctrl;
u32 pad119[1];
u32 cm_l4per_l4per_clkctrl;
u32 pad1191[3];
u32 cm_l4per_mcasp2_clkctrl;
u32 pad120[1];
u32 cm_l4per_mcasp3_clkctrl;
u32 pad121[1];
u32 cm_l4per_mcbsp4_clkctrl;
u32 pad122[1];
u32 cm_l4per_mgate_clkctrl;
u32 pad123[1];
u32 cm_l4per_mcspi1_clkctrl;
u32 pad124[1];
u32 cm_l4per_mcspi2_clkctrl;
u32 pad125[1];
u32 cm_l4per_mcspi3_clkctrl;
u32 pad126[1];
u32 cm_l4per_mcspi4_clkctrl;
u32 pad127[5];
u32 cm_l4per_mmcsd3_clkctrl;
u32 pad128[1];
u32 cm_l4per_mmcsd4_clkctrl;
u32 pad129[1];
u32 cm_l4per_msprohg_clkctrl;
u32 pad130[1];
u32 cm_l4per_slimbus2_clkctrl;
u32 pad131[1];
u32 cm_l4per_uart1_clkctrl;
u32 pad132[1];
u32 cm_l4per_uart2_clkctrl;
u32 pad133[1];
u32 cm_l4per_uart3_clkctrl;
u32 pad134[1];
u32 cm_l4per_uart4_clkctrl;
u32 pad135[1];
u32 cm_l4per_mmcsd5_clkctrl;
u32 pad136[1];
u32 cm_l4per_i2c5_clkctrl;
u32 pad137[5];
u32 cm_l4sec_clkstctrl;
u32 cm_l4sec_staticdep;
u32 cm_l4sec_dynamicdep;
u32 pad138[5];
u32 cm_l4sec_aes1_clkctrl;
u32 pad139[1];
u32 cm_l4sec_aes2_clkctrl;
u32 pad140[1];
u32 cm_l4sec_des3des_clkctrl;
u32 pad141[1];
u32 cm_l4sec_pkaeip29_clkctrl;
u32 pad142[1];
u32 cm_l4sec_rng_clkctrl;
u32 pad143[1];
u32 cm_l4sec_sha2md51_clkctrl;
u32 pad144[3];
u32 cm_l4sec_cryptodma_clkctrl;
u32 pad145[776841];
/* l4 wkup regs */
u32 pad201[6211];
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
u32 pad202[1467];
u32 cm_wkup_clkstctrl;
u32 pad203[7];
u32 cm_wkup_l4wkup_clkctrl;
u32 pad204;
u32 cm_wkup_wdtimer1_clkctrl;
u32 pad205;
u32 cm_wkup_wdtimer2_clkctrl;
u32 pad206;
u32 cm_wkup_gpio1_clkctrl;
u32 pad207;
u32 cm_wkup_gptimer1_clkctrl;
u32 pad208;
u32 cm_wkup_gptimer12_clkctrl;
u32 pad209;
u32 cm_wkup_synctimer_clkctrl;
u32 pad210;
u32 cm_wkup_usim_clkctrl;
u32 pad211;
u32 cm_wkup_sarram_clkctrl;
u32 pad212[5];
u32 cm_wkup_keyboard_clkctrl;
u32 pad213;
u32 cm_wkup_rtc_clkctrl;
u32 pad214;
u32 cm_wkup_bandgap_clkctrl;
u32 pad215[197];
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_channel;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
};
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */
u32 pad00[63];
u32 clksetuptime; /* 0x0100 */
u32 pmicsetuptime; /* 0x0104 */
u32 pad01[2];
u32 altclksrc; /* 0x0110 */
u32 pad02[2];
u32 c2cclkm; /* 0x011c */
u32 pad03[56];
u32 extclkreq; /* 0x0200 */
u32 accclkreq; /* 0x0204 */
u32 pwrreq; /* 0x0208 */
u32 pad04[1];
u32 auxclkreq0; /* 0x0210 */
u32 auxclkreq1; /* 0x0214 */
u32 auxclkreq2; /* 0x0218 */
u32 auxclkreq3; /* 0x021c */
u32 auxclkreq4; /* 0x0220 */
u32 auxclkreq5; /* 0x0224 */
u32 pad05[3];
u32 c2cclkreq; /* 0x0234 */
u32 pad06[54];
u32 auxclk0; /* 0x0310 */
u32 auxclk1; /* 0x0314 */
u32 auxclk2; /* 0x0318 */
u32 auxclk3; /* 0x031c */
u32 auxclk4; /* 0x0320 */
u32 auxclk5; /* 0x0324 */
u32 pad07[54];
u32 rsttime_reg; /* 0x0400 */
u32 pad08[6];
u32 c2crstctrl; /* 0x041c */
u32 extpwronrstctrl; /* 0x0420 */
u32 pad09[59];
u32 extwarmrstst_reg; /* 0x0510 */
u32 apewarmrstst_reg; /* 0x0514 */
u32 pad10[1];
u32 c2cwarmrstst_reg; /* 0x051C */
};
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
@ -714,54 +242,44 @@ struct omap4_scrm_regs {
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
#define NUM_SYS_CLKS 7
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_m4_dpll;
u32 cm_div_m5_dpll;
u32 cm_div_m6_dpll;
u32 cm_div_m7_dpll;
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */
u32 pad00[63];
u32 clksetuptime; /* 0x0100 */
u32 pmicsetuptime; /* 0x0104 */
u32 pad01[2];
u32 altclksrc; /* 0x0110 */
u32 pad02[2];
u32 c2cclkm; /* 0x011c */
u32 pad03[56];
u32 extclkreq; /* 0x0200 */
u32 accclkreq; /* 0x0204 */
u32 pwrreq; /* 0x0208 */
u32 pad04[1];
u32 auxclkreq0; /* 0x0210 */
u32 auxclkreq1; /* 0x0214 */
u32 auxclkreq2; /* 0x0218 */
u32 auxclkreq3; /* 0x021c */
u32 auxclkreq4; /* 0x0220 */
u32 auxclkreq5; /* 0x0224 */
u32 pad05[3];
u32 c2cclkreq; /* 0x0234 */
u32 pad06[54];
u32 auxclk0; /* 0x0310 */
u32 auxclk1; /* 0x0314 */
u32 auxclk2; /* 0x0318 */
u32 auxclk3; /* 0x031c */
u32 auxclk4; /* 0x0320 */
u32 auxclk5; /* 0x0324 */
u32 pad07[54];
u32 rsttime_reg; /* 0x0400 */
u32 pad08[6];
u32 c2crstctrl; /* 0x041c */
u32 extpwronrstctrl; /* 0x0420 */
u32 pad09[59];
u32 extwarmrstst_reg; /* 0x0510 */
u32 apewarmrstst_reg; /* 0x0514 */
u32 pad10[1];
u32 c2cwarmrstst_reg; /* 0x051C */
};
/* DPLL parameter table */
struct dpll_params {
u32 m;
u32 n;
s8 m2;
s8 m3;
s8 m4;
s8 m5;
s8 m6;
s8 m7;
};
extern struct omap4_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */

140
arch/arm/include/asm/arch-omap4/mmc_host_def.h
View File

@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
#include <asm/omap_mmc.h>
/*
* OMAP HSMMC register definitions
*/
@ -33,142 +35,4 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
};
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */

34
arch/arm/include/asm/arch-omap4/omap.h
View File

@ -132,34 +132,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
struct omap_sys_ctrl_regs {
unsigned int pad1[129];
unsigned int control_id_code; /* 0x4A002204 */
unsigned int pad11[22];
unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
unsigned int pad2[24]; /* 0x4a002264 */
unsigned int control_status; /* 0x4a0022c4 */
unsigned int pad3[22]; /* 0x4a0022c8 */
unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad4[260277];
unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad5[63];
unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */
};
struct control_lpddr2io_regs {
unsigned int control_lpddr2io1_0;
unsigned int control_lpddr2io1_1;
unsigned int control_lpddr2io1_2;
unsigned int control_lpddr2io1_3;
unsigned int control_lpddr2io2_0;
unsigned int control_lpddr2io2_1;
unsigned int control_lpddr2io2_2;
unsigned int control_lpddr2io2_3;
};
#endif /* __ASSEMBLY__ */
/*
@ -178,7 +150,11 @@ struct control_lpddr2io_regs {
#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* ROM code defines */
/* Boot device */

2
arch/arm/include/asm/arch-omap4/spl.h
View File

@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
#define BOOT_DEVICE_ONE_NAND 4
#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 0xFF

2
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -44,7 +44,7 @@ void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap4_ddr_clk(void);

539
arch/arm/include/asm/arch-omap5/clocks.h
View File

@ -26,6 +26,7 @@
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@ -39,456 +40,6 @@
#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
struct omap5_prcm_regs {
/* cm1.ckgen */
u32 cm_clksel_core; /* 4a004100 */
u32 pad001[1]; /* 4a004104 */
u32 cm_clksel_abe; /* 4a004108 */
u32 pad002[1]; /* 4a00410c */
u32 cm_dll_ctrl; /* 4a004110 */
u32 pad003[3]; /* 4a004114 */
u32 cm_clkmode_dpll_core; /* 4a004120 */
u32 cm_idlest_dpll_core; /* 4a004124 */
u32 cm_autoidle_dpll_core; /* 4a004128 */
u32 cm_clksel_dpll_core; /* 4a00412c */
u32 cm_div_m2_dpll_core; /* 4a004130 */
u32 cm_div_m3_dpll_core; /* 4a004134 */
u32 cm_div_h11_dpll_core; /* 4a004138 */
u32 cm_div_h12_dpll_core; /* 4a00413c */
u32 cm_div_h13_dpll_core; /* 4a004140 */
u32 cm_div_h14_dpll_core; /* 4a004144 */
u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
u32 cm_emu_override_dpll_core; /* 4a004150 */
u32 cm_div_h22_dpllcore; /* 4a004154 */
u32 cm_div_h23_dpll_core; /* 4a004158 */
u32 pad0041[1]; /* 4a00415c */
u32 cm_clkmode_dpll_mpu; /* 4a004160 */
u32 cm_idlest_dpll_mpu; /* 4a004164 */
u32 cm_autoidle_dpll_mpu; /* 4a004168 */
u32 cm_clksel_dpll_mpu; /* 4a00416c */
u32 cm_div_m2_dpll_mpu; /* 4a004170 */
u32 pad005[5]; /* 4a004174 */
u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
u32 pad006[3]; /* 4a004190 */
u32 cm_bypclk_dpll_mpu; /* 4a00419c */
u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
u32 cm_idlest_dpll_iva; /* 4a0041a4 */
u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
u32 cm_clksel_dpll_iva; /* 4a0041ac */
u32 pad007[2]; /* 4a0041b0 */
u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
u32 cm_div_h12_dpll_iva; /* 4a0041bc */
u32 pad008[2]; /* 4a0041c0 */
u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
u32 pad009[3]; /* 4a0041d0 */
u32 cm_bypclk_dpll_iva; /* 4a0041dc */
u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
u32 cm_idlest_dpll_abe; /* 4a0041e4 */
u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
u32 cm_clksel_dpll_abe; /* 4a0041ec */
u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
u32 pad010[4]; /* 4a0041f8 */
u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
u32 pad011[4]; /* 4a004210 */
u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
u32 pad012[1]; /* 4a004234 */
u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
u32 pad013[1]; /* 4a004244 */
u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
u32 pad014[5]; /* 4a00424c */
u32 cm_shadow_freq_config1; /* 4a004260 */
u32 pad0141[47]; /* 4a004264 */
u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
/* cm1.dsp */
u32 pad015[55]; /* 4a004324 */
u32 cm_dsp_clkstctrl; /* 4a004400 */
u32 pad016[7]; /* 4a004404 */
u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
/* cm1.abe */
u32 pad017[55]; /* 4a004424 */
u32 cm1_abe_clkstctrl; /* 4a004500 */
u32 pad018[7]; /* 4a004504 */
u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
u32 pad019[1]; /* 4a004524 */
u32 cm1_abe_aess_clkctrl; /* 4a004528 */
u32 pad020[1]; /* 4a00452c */
u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
u32 pad021[1]; /* 4a004534 */
u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
u32 pad022[1]; /* 4a00453c */
u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
u32 pad023[1]; /* 4a004544 */
u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
u32 pad024[1]; /* 4a00454c */
u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
u32 pad025[1]; /* 4a004554 */
u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
u32 pad026[1]; /* 4a00455c */
u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
u32 pad027[1]; /* 4a004564 */
u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
u32 pad028[1]; /* 4a00456c */
u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
u32 pad029[1]; /* 4a004574 */
u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
u32 pad030[1]; /* 4a00457c */
u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
u32 pad031[1]; /* 4a004584 */
u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
/* cm2.ckgen */
u32 pad032[3805]; /* 4a00458c */
u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
u32 cm_clksel_usb_60mhz; /* 4a008104 */
u32 cm_scale_fclk; /* 4a008108 */
u32 pad033[1]; /* 4a00810c */
u32 cm_core_dvfs_perf1; /* 4a008110 */
u32 cm_core_dvfs_perf2; /* 4a008114 */
u32 cm_core_dvfs_perf3; /* 4a008118 */
u32 cm_core_dvfs_perf4; /* 4a00811c */
u32 pad034[1]; /* 4a008120 */
u32 cm_core_dvfs_current; /* 4a008124 */
u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
u32 pad035[1]; /* 4a008134 */
u32 cm_iva_dvfs_current; /* 4a008138 */
u32 pad036[1]; /* 4a00813c */
u32 cm_clkmode_dpll_per; /* 4a008140 */
u32 cm_idlest_dpll_per; /* 4a008144 */
u32 cm_autoidle_dpll_per; /* 4a008148 */
u32 cm_clksel_dpll_per; /* 4a00814c */
u32 cm_div_m2_dpll_per; /* 4a008150 */
u32 cm_div_m3_dpll_per; /* 4a008154 */
u32 cm_div_h11_dpll_per; /* 4a008158 */
u32 cm_div_h12_dpll_per; /* 4a00815c */
u32 pad0361[1]; /* 4a008160 */
u32 cm_div_h14_dpll_per; /* 4a008164 */
u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
u32 cm_emu_override_dpll_per; /* 4a008170 */
u32 pad037[3]; /* 4a008174 */
u32 cm_clkmode_dpll_usb; /* 4a008180 */
u32 cm_idlest_dpll_usb; /* 4a008184 */
u32 cm_autoidle_dpll_usb; /* 4a008188 */
u32 cm_clksel_dpll_usb; /* 4a00818c */
u32 cm_div_m2_dpll_usb; /* 4a008190 */
u32 pad038[5]; /* 4a008194 */
u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
u32 pad039[1]; /* 4a0081b0 */
u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
u32 pad040[2]; /* 4a0081b8 */
u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
u32 cm_clksel_dpll_unipro; /* 4a0081cc */
u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
u32 pad041[5]; /* 4a0081d4 */
u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
/* cm2.core */
u32 pad0411[324]; /* 4a0081f0 */
u32 cm_l3_1_clkstctrl; /* 4a008700 */
u32 pad042[1]; /* 4a008704 */
u32 cm_l3_1_dynamicdep; /* 4a008708 */
u32 pad043[5]; /* 4a00870c */
u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
u32 pad044[55]; /* 4a008724 */
u32 cm_l3_2_clkstctrl; /* 4a008800 */
u32 pad045[1]; /* 4a008804 */
u32 cm_l3_2_dynamicdep; /* 4a008808 */
u32 pad046[5]; /* 4a00880c */
u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
u32 pad047[1]; /* 4a008824 */
u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
u32 pad048[1]; /* 4a00882c */
u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
u32 pad049[51]; /* 4a008834 */
u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
u32 cm_mpu_m3_staticdep; /* 4a008904 */
u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
u32 pad050[5]; /* 4a00890c */
u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
u32 pad051[55]; /* 4a008924 */
u32 cm_sdma_clkstctrl; /* 4a008a00 */
u32 cm_sdma_staticdep; /* 4a008a04 */
u32 cm_sdma_dynamicdep; /* 4a008a08 */
u32 pad052[5]; /* 4a008a0c */
u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
u32 pad053[55]; /* 4a008a24 */
u32 cm_memif_clkstctrl; /* 4a008b00 */
u32 pad054[7]; /* 4a008b04 */
u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
u32 pad055[1]; /* 4a008b24 */
u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
u32 pad056[1]; /* 4a008b2c */
u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
u32 pad057[1]; /* 4a008b34 */
u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
u32 pad058[1]; /* 4a008b3c */
u32 cm_memif_dll_clkctrl; /* 4a008b40 */
u32 pad059[3]; /* 4a008b44 */
u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
u32 pad060[1]; /* 4a008b54 */
u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
u32 pad061[1]; /* 4a008b5c */
u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
u32 pad062[39]; /* 4a008b64 */
u32 cm_c2c_clkstctrl; /* 4a008c00 */
u32 cm_c2c_staticdep; /* 4a008c04 */
u32 cm_c2c_dynamicdep; /* 4a008c08 */
u32 pad063[5]; /* 4a008c0c */
u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
u32 pad064[1]; /* 4a008c24 */
u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
u32 pad065[1]; /* 4a008c2c */
u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
u32 pad066[51]; /* 4a008c34 */
u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
u32 pad067[1]; /* 4a008d04 */
u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
u32 pad068[5]; /* 4a008d0c */
u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
u32 pad069[1]; /* 4a008d24 */
u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
u32 pad070[1]; /* 4a008d2c */
u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
u32 pad071[1]; /* 4a008d34 */
u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
u32 pad072[49]; /* 4a008d3c */
u32 cm_l3instr_clkstctrl; /* 4a008e00 */
u32 pad073[7]; /* 4a008e04 */
u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
u32 pad074[1]; /* 4a008e24 */
u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
u32 pad075[5]; /* 4a008e2c */
u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
/* cm2.ivahd */
u32 pad076[47]; /* 4a008e44 */
u32 cm_ivahd_clkstctrl; /* 4a008f00 */
u32 pad077[7]; /* 4a008f04 */
u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
u32 pad078[1]; /* 4a008f24 */
u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
/* cm2.cam */
u32 pad079[53]; /* 4a008f2c */
u32 cm_cam_clkstctrl; /* 4a009000 */
u32 pad080[7]; /* 4a009004 */
u32 cm_cam_iss_clkctrl; /* 4a009020 */
u32 pad081[1]; /* 4a009024 */
u32 cm_cam_fdif_clkctrl; /* 4a009028 */
/* cm2.dss */
u32 pad082[53]; /* 4a00902c */
u32 cm_dss_clkstctrl; /* 4a009100 */
u32 pad083[7]; /* 4a009104 */
u32 cm_dss_dss_clkctrl; /* 4a009120 */
/* cm2.sgx */
u32 pad084[55]; /* 4a009124 */
u32 cm_sgx_clkstctrl; /* 4a009200 */
u32 pad085[7]; /* 4a009204 */
u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
/* cm2.l3init */
u32 pad086[55]; /* 4a009224 */
u32 cm_l3init_clkstctrl; /* 4a009300 */
/* cm2.l3init */
u32 pad087[9]; /* 4a009304 */
u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
u32 pad088[1]; /* 4a00932c */
u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
u32 pad089[1]; /* 4a009334 */
u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
u32 pad090[7]; /* 4a00933c */
u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
u32 pad091[1]; /* 4a00935c */
u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
u32 pad092[1]; /* 4a009364 */
u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
u32 pad093[3]; /* 4a00936c */
u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
u32 pad094[21]; /* 4a00937c */
u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
u32 pad095[3]; /* 4a0093d4 */
u32 cm_l3init_ocp2scp1_clkctrl;
/* cm2.l4per */
u32 pad096[7]; /* 4a0093e4 */
u32 cm_l4per_clkstctrl; /* 4a009400 */
u32 pad097[1]; /* 4a009404 */
u32 cm_l4per_dynamicdep; /* 4a009408 */
u32 pad098[5]; /* 4a00940c */
u32 cm_l4per_adc_clkctrl; /* 4a009420 */
u32 pad100[1]; /* 4a009424 */
u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
u32 pad101[1]; /* 4a00942c */
u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
u32 pad102[1]; /* 4a009434 */
u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
u32 pad103[1]; /* 4a00943c */
u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
u32 pad104[1]; /* 4a009444 */
u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
u32 pad105[1]; /* 4a00944c */
u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
u32 pad106[1]; /* 4a009454 */
u32 cm_l4per_elm_clkctrl; /* 4a009458 */
u32 pad107[1]; /* 4a00945c */
u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
u32 pad108[1]; /* 4a009464 */
u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
u32 pad109[1]; /* 4a00946c */
u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
u32 pad110[1]; /* 4a009474 */
u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
u32 pad111[1]; /* 4a00947c */
u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
u32 pad112[1]; /* 4a009484 */
u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
u32 pad113[1]; /* 4a00948c */
u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
u32 pad114[1]; /* 4a009494 */
u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
u32 pad115[1]; /* 4a00949c */
u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
u32 pad116[1]; /* 4a0094a4 */
u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
u32 pad117[1]; /* 4a0094ac */
u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
u32 pad118[1]; /* 4a0094b4 */
u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
u32 pad119[1]; /* 4a0094bc */
u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
u32 pad1191[3]; /* 4a0094c4 */
u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
u32 pad120[1]; /* 4a0094d4 */
u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
u32 pad121[3]; /* 4a0094dc */
u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
u32 pad123[1]; /* 4a0094ec */
u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
u32 pad124[1]; /* 4a0094f4 */
u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
u32 pad125[1]; /* 4a0094fc */
u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
u32 pad126[1]; /* 4a009504 */
u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
u32 pad127[1]; /* 4a00950c */
u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
u32 pad1271[1]; /* 4a009514 */
u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
u32 pad1272[1]; /* 4a00951c */
u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
u32 pad128[1]; /* 4a009524 */
u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
u32 pad129[1]; /* 4a00952c */
u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
u32 pad130[1]; /* 4a009534 */
u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
u32 pad131[1]; /* 4a00953c */
u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
u32 pad132[1]; /* 4a009544 */
u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
u32 pad133[1]; /* 4a00954c */
u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
u32 pad134[1]; /* 4a009554 */
u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
u32 pad135[1]; /* 4a00955c */
u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
u32 pad136[1]; /* 4a009564 */
u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
u32 pad1371[1]; /* 4a00956c */
u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
u32 pad1372[1]; /* 4a009574 */
u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
u32 pad1374[1]; /* 4a00957c */
u32 cm_l4sec_clkstctrl; /* 4a009580 */
u32 cm_l4sec_staticdep; /* 4a009584 */
u32 cm_l4sec_dynamicdep; /* 4a009588 */
u32 pad138[5]; /* 4a00958c */
u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
u32 pad139[1]; /* 4a0095a4 */
u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
u32 pad140[1]; /* 4a0095ac */
u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
u32 pad141[1]; /* 4a0095b4 */
u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
u32 pad142[1]; /* 4a0095bc */
u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
u32 pad143[1]; /* 4a0095c4 */
u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
u32 pad144[3]; /* 4a0095cc */
u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
u32 pad145[3660425]; /* 4a0095dc */
/* l4 wkup regs */
u32 pad201[6211]; /* 4ae00000 */
u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
u32 cm_sys_clksel; /* 4ae06110 */
u32 pad202[1467]; /* 4ae06114 */
u32 cm_wkup_clkstctrl; /* 4ae07800 */
u32 pad203[7]; /* 4ae07804 */
u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
u32 pad204; /* 4ae07824 */
u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
u32 pad205; /* 4ae0782c */
u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
u32 pad206; /* 4ae07834 */
u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
u32 pad207; /* 4ae0783c */
u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
u32 pad208; /* 4ae07844 */
u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
u32 pad209; /* 4ae0784c */
u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
u32 pad210; /* 4ae07854 */
u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
u32 pad211; /* 4ae0785c */
u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
u32 pad212[5]; /* 4ae07864 */
u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
u32 pad213; /* 4ae0787c */
u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
u32 pad214; /* 4ae07884 */
u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
u32 pad215[1]; /* 4ae0788c */
u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */
u32 pad216[195];
u32 prm_vc_val_bypass; /* 4ae07ba0 */
u32 pad217[4];
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
u32 pad218[2];
u32 prm_sldo_core_setup; /* 4ae07bc4 */
u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
u32 prm_sldo_mpu_setup; /* 4ae07bcc */
u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
u32 prm_sldo_mm_setup; /* 4ae07bd4 */
u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
};
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
@ -625,9 +176,9 @@ struct omap5_prcm_regs {
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT 9
@ -635,6 +186,10 @@ struct omap5_prcm_regs {
#define OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
/* CM_COREAON_IO_SRCOMP_CLKCTRL */
#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
@ -650,12 +205,25 @@ struct omap5_prcm_regs {
#define SMPS_REG_ADDR_8_CORE 0x37
/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
#define VDD_MPU 1000
#define VDD_MM 1000
/* ES1.0 settings */
#define VDD_MPU 1040
#define VDD_MM 1040
#define VDD_CORE 1040
#define VDD_MPU_5432 1150
#define VDD_MM_5432 1150
#define VDD_CORE_5432 1150
#define VDD_MPU_LOW 890
#define VDD_MM_LOW 890
#define VDD_CORE_LOW 890
/* ES2.0 settings */
#define VDD_MPU_ES2 1060
#define VDD_MM_ES2 1025
#define VDD_CORE_ES2 1040
#define VDD_MPU_ES2_HIGH 1250
#define VDD_MM_ES2_OD 1120
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
@ -683,59 +251,4 @@ struct omap5_prcm_regs {
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
#define NUM_SYS_CLKS 7
struct dpll_regs {
u32 cm_clkmode_dpll;
u32 cm_idlest_dpll;
u32 cm_autoidle_dpll;
u32 cm_clksel_dpll;
u32 cm_div_m2_dpll;
u32 cm_div_m3_dpll;
u32 cm_div_h11_dpll;
u32 cm_div_h12_dpll;
u32 cm_div_h13_dpll;
u32 cm_div_h14_dpll;
u32 reserved[3];
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
};
/* DPLL parameter table */
struct dpll_params {
u32 m;
u32 n;
s8 m2;
s8 m3;
s8 h11;
s8 h12;
s8 h13;
s8 h14;
s8 h22;
s8 h23;
};
extern struct omap5_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
u32 get_offset_code(u32 offset);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
void setup_post_dividers(u32 *const base, const struct dpll_params *params);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_non_essential_clocks(void);
void enable_basic_uboot_clocks(void);
void do_enable_clocks(u32 *const *clk_domains,
u32 *const *clk_modules_hw_auto,
u32 *const *clk_modules_explicit_en,
u8 wait_for_enable);
const struct dpll_params *get_mpu_dpll_params(void);
const struct dpll_params *get_core_dpll_params(void);
const struct dpll_params *get_per_dpll_params(void);
const struct dpll_params *get_iva_dpll_params(void);
const struct dpll_params *get_usb_dpll_params(void);
const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP5_H_ */

140
arch/arm/include/asm/arch-omap5/mmc_host_def.h
View File

@ -25,6 +25,8 @@
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
#include <asm/omap_mmc.h>
/*
* OMAP HSMMC register definitions
*/
@ -33,142 +35,4 @@
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con; /* 0x2C */
unsigned char res3[0xD4];
unsigned int blk; /* 0x104 */
unsigned int arg; /* 0x108 */
unsigned int cmd; /* 0x10C */
unsigned int rsp10; /* 0x110 */
unsigned int rsp32; /* 0x114 */
unsigned int rsp54; /* 0x118 */
unsigned int rsp76; /* 0x11C */
unsigned int data; /* 0x120 */
unsigned int pstate; /* 0x124 */
unsigned int hctl; /* 0x128 */
unsigned int sysctl; /* 0x12C */
unsigned int stat; /* 0x130 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
};
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */

344
arch/arm/include/asm/arch-omap5/mux_dra7xx.h Normal file
View File

@ -0,0 +1,344 @@
/*
* (C) Copyright 2013
* Texas Instruments Incorporated
*
* Nishant Kamat <nskamat@ti.com>
* Lokesh Vutla <lokeshvutla@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MUX_DRA7XX_H_
#define _MUX_DRA7XX_H_
#include <asm/types.h>
#define IEN (1 << 18)
#define IDIS (0 << 18)
#define PTU (3 << 16)
#define PTD (1 << 16)
#define PEN (1 << 16)
#define PDIS (0 << 16)
#define WKEN (1 << 24)
#define WKDIS (0 << 24)
#define M0 0
#define M1 1
#define M2 2
#define M3 3
#define M4 4
#define M5 5
#define M6 6
#define M7 7
#define M8 8
#define M9 9
#define M10 10
#define M11 11
#define M12 12
#define M13 13
#define M14 14
#define M15 15
#define SAFE_MODE M15
#define GPMC_AD0 0x000
#define GPMC_AD1 0x004
#define GPMC_AD2 0x008
#define GPMC_AD3 0x00C
#define GPMC_AD4 0x010
#define GPMC_AD5 0x014
#define GPMC_AD6 0x018
#define GPMC_AD7 0x01C
#define GPMC_AD8 0x020
#define GPMC_AD9 0x024
#define GPMC_AD10 0x028
#define GPMC_AD11 0x02C
#define GPMC_AD12 0x030
#define GPMC_AD13 0x034
#define GPMC_AD14 0x038
#define GPMC_AD15 0x03C
#define GPMC_A0 0x040
#define GPMC_A1 0x044
#define GPMC_A2 0x048
#define GPMC_A3 0x04C
#define GPMC_A4 0x050
#define GPMC_A5 0x054
#define GPMC_A6 0x058
#define GPMC_A7 0x05C
#define GPMC_A8 0x060
#define GPMC_A9 0x064
#define GPMC_A10 0x068
#define GPMC_A11 0x06C
#define GPMC_A12 0x070
#define GPMC_A13 0x074
#define GPMC_A14 0x078
#define GPMC_A15 0x07C
#define GPMC_A16 0x080
#define GPMC_A17 0x084
#define GPMC_A18 0x088
#define GPMC_A19 0x08C
#define GPMC_A20 0x090
#define GPMC_A21 0x094
#define GPMC_A22 0x098
#define GPMC_A23 0x09C
#define GPMC_A24 0x0A0
#define GPMC_A25 0x0A4
#define GPMC_A26 0x0A8
#define GPMC_A27 0x0AC
#define GPMC_CS1 0x0B0
#define GPMC_CS0 0x0B4
#define GPMC_CS2 0x0B8
#define GPMC_CS3 0x0BC
#define GPMC_CLK 0x0C0
#define GPMC_ADVN_ALE 0x0C4
#define GPMC_OEN_REN 0x0C8
#define GPMC_WEN 0x0CC
#define GPMC_BEN0 0x0D0
#define GPMC_BEN1 0x0D4
#define GPMC_WAIT0 0x0D8
#define VIN1A_CLK0 0x0DC
#define VIN1B_CLK1 0x0E0
#define VIN1A_DE0 0x0E4
#define VIN1A_FLD0 0x0E8
#define VIN1A_HSYNC0 0x0EC
#define VIN1A_VSYNC0 0x0F0
#define VIN1A_D0 0x0F4
#define VIN1A_D1 0x0F8
#define VIN1A_D2 0x0FC
#define VIN1A_D3 0x100
#define VIN1A_D4 0x104
#define VIN1A_D5 0x108
#define VIN1A_D6 0x10C
#define VIN1A_D7 0x110
#define VIN1A_D8 0x114
#define VIN1A_D9 0x118
#define VIN1A_D10 0x11C
#define VIN1A_D11 0x120
#define VIN1A_D12 0x124
#define VIN1A_D13 0x128
#define VIN1A_D14 0x12C
#define VIN1A_D15 0x130
#define VIN1A_D16 0x134
#define VIN1A_D17 0x138
#define VIN1A_D18 0x13C
#define VIN1A_D19 0x140
#define VIN1A_D20 0x144
#define VIN1A_D21 0x148
#define VIN1A_D22 0x14C
#define VIN1A_D23 0x150
#define VIN2A_CLK0 0x154
#define VIN2A_DE0 0x158
#define VIN2A_FLD0 0x15C
#define VIN2A_HSYNC0 0x160
#define VIN2A_VSYNC0 0x164
#define VIN2A_D0 0x168
#define VIN2A_D1 0x16C
#define VIN2A_D2 0x170
#define VIN2A_D3 0x174
#define VIN2A_D4 0x178
#define VIN2A_D5 0x17C
#define VIN2A_D6 0x180
#define VIN2A_D7 0x184
#define VIN2A_D8 0x188
#define VIN2A_D9 0x18C
#define VIN2A_D10 0x190
#define VIN2A_D11 0x194
#define VIN2A_D12 0x198
#define VIN2A_D13 0x19C
#define VIN2A_D14 0x1A0
#define VIN2A_D15 0x1A4
#define VIN2A_D16 0x1A8
#define VIN2A_D17 0x1AC
#define VIN2A_D18 0x1B0
#define VIN2A_D19 0x1B4
#define VIN2A_D20 0x1B8
#define VIN2A_D21 0x1BC
#define VIN2A_D22 0x1C0
#define VIN2A_D23 0x1C4
#define VOUT1_CLK 0x1C8
#define VOUT1_DE 0x1CC
#define VOUT1_FLD 0x1D0
#define VOUT1_HSYNC 0x1D4
#define VOUT1_VSYNC 0x1D8
#define VOUT1_D0 0x1DC
#define VOUT1_D1 0x1E0
#define VOUT1_D2 0x1E4
#define VOUT1_D3 0x1E8
#define VOUT1_D4 0x1EC
#define VOUT1_D5 0x1F0
#define VOUT1_D6 0x1F4
#define VOUT1_D7 0x1F8
#define VOUT1_D8 0x1FC
#define VOUT1_D9 0x200
#define VOUT1_D10 0x204
#define VOUT1_D11 0x208
#define VOUT1_D12 0x20C
#define VOUT1_D13 0x210
#define VOUT1_D14 0x214
#define VOUT1_D15 0x218
#define VOUT1_D16 0x21C
#define VOUT1_D17 0x220
#define VOUT1_D18 0x224
#define VOUT1_D19 0x228
#define VOUT1_D20 0x22C
#define VOUT1_D21 0x230
#define VOUT1_D22 0x234
#define VOUT1_D23 0x238
#define MDIO_MCLK 0x23C
#define MDIO_D 0x240
#define RMII_MHZ_50_CLK 0x244
#define UART3_RXD 0x248
#define UART3_TXD 0x24C
#define RGMII0_TXC 0x250
#define RGMII0_TXCTL 0x254
#define RGMII0_TXD3 0x258
#define RGMII0_TXD2 0x25C
#define RGMII0_TXD1 0x260
#define RGMII0_TXD0 0x264
#define RGMII0_RXC 0x268
#define RGMII0_RXCTL 0x26C
#define RGMII0_RXD3 0x270
#define RGMII0_RXD2 0x274
#define RGMII0_RXD1 0x278
#define RGMII0_RXD0 0x27C
#define USB1_DRVVBUS 0x280
#define USB2_DRVVBUS 0x284
#define GPIO6_14 0x288
#define GPIO6_15 0x28C
#define GPIO6_16 0x290
#define XREF_CLK0 0x294
#define XREF_CLK1 0x298
#define XREF_CLK2 0x29C
#define XREF_CLK3 0x2A0
#define MCASP1_ACLKX 0x2A4
#define MCASP1_FSX 0x2A8
#define MCASP1_ACLKR 0x2AC
#define MCASP1_FSR 0x2B0
#define MCASP1_AXR0 0x2B4
#define MCASP1_AXR1 0x2B8
#define MCASP1_AXR2 0x2BC
#define MCASP1_AXR3 0x2C0
#define MCASP1_AXR4 0x2C4
#define MCASP1_AXR5 0x2C8
#define MCASP1_AXR6 0x2CC
#define MCASP1_AXR7 0x2D0
#define MCASP1_AXR8 0x2D4
#define MCASP1_AXR9 0x2D8
#define MCASP1_AXR10 0x2DC
#define MCASP1_AXR11 0x2E0
#define MCASP1_AXR12 0x2E4
#define MCASP1_AXR13 0x2E8
#define MCASP1_AXR14 0x2EC
#define MCASP1_AXR15 0x2F0
#define MCASP2_ACLKX 0x2F4
#define MCASP2_FSX 0x2F8
#define MCASP2_ACLKR 0x2FC
#define MCASP2_FSR 0x300
#define MCASP2_AXR0 0x304
#define MCASP2_AXR1 0x308
#define MCASP2_AXR2 0x30C
#define MCASP2_AXR3 0x310
#define MCASP2_AXR4 0x314
#define MCASP2_AXR5 0x318
#define MCASP2_AXR6 0x31C
#define MCASP2_AXR7 0x320
#define MCASP3_ACLKX 0x324
#define MCASP3_FSX 0x328
#define MCASP3_AXR0 0x32C
#define MCASP3_AXR1 0x330
#define MCASP4_ACLKX 0x334
#define MCASP4_FSX 0x338
#define MCASP4_AXR0 0x33C
#define MCASP4_AXR1 0x340
#define MCASP5_ACLKX 0x344
#define MCASP5_FSX 0x348
#define MCASP5_AXR0 0x34C
#define MCASP5_AXR1 0x350
#define MMC1_CLK 0x354
#define MMC1_CMD 0x358
#define MMC1_DAT0 0x35C
#define MMC1_DAT1 0x360
#define MMC1_DAT2 0x364
#define MMC1_DAT3 0x368
#define MMC1_SDCD 0x36C
#define MMC1_SDWP 0x370
#define GPIO6_10 0x374
#define GPIO6_11 0x378
#define MMC3_CLK 0x37C
#define MMC3_CMD 0x380
#define MMC3_DAT0 0x384
#define MMC3_DAT1 0x388
#define MMC3_DAT2 0x38C
#define MMC3_DAT3 0x390
#define MMC3_DAT4 0x394
#define MMC3_DAT5 0x398
#define MMC3_DAT6 0x39C
#define MMC3_DAT7 0x3A0
#define SPI1_SCLK 0x3A4
#define SPI1_D1 0x3A8
#define SPI1_D0 0x3AC
#define SPI1_CS0 0x3B0
#define SPI1_CS1 0x3B4
#define SPI1_CS2 0x3B8
#define SPI1_CS3 0x3BC
#define SPI2_SCLK 0x3C0
#define SPI2_D1 0x3C4
#define SPI2_D0 0x3C8
#define SPI2_CS0 0x3CC
#define DCAN1_TX 0x3D0
#define DCAN1_RX 0x3D4
#define DCAN2_TX 0x3D8
#define DCAN2_RX 0x3DC
#define UART1_RXD 0x3E0
#define UART1_TXD 0x3E4
#define UART1_CTSN 0x3E8
#define UART1_RTSN 0x3EC
#define UART2_RXD 0x3F0
#define UART2_TXD 0x3F4
#define UART2_CTSN 0x3F8
#define UART2_RTSN 0x3FC
#define I2C1_SDA 0x400
#define I2C1_SCL 0x404
#define I2C2_SDA 0x408
#define I2C2_SCL 0x40C
#define I2C3_SDA 0x410
#define I2C3_SCL 0x414
#define WAKEUP0 0x418
#define WAKEUP1 0x41C
#define WAKEUP2 0x420
#define WAKEUP3 0x424
#define ON_OFF 0x428
#define RTC_PORZ 0x42C
#define TMS 0x430
#define TDI 0x434
#define TDO 0x438
#define TCLK 0x43C
#define TRSTN 0x440
#define RTCK 0x444
#define EMU0 0x448
#define EMU1 0x44C
#define EMU2 0x450
#define EMU3 0x454
#define EMU4 0x458
#define RESETN 0x45C
#define NMIN 0x460
#define RSTOUTN 0x464
#endif /* _MUX_DRA7XX_H_ */

8
arch/arm/include/asm/arch-omap5/mux_omap5.h
View File

@ -28,14 +28,6 @@
#include <asm/types.h>
struct pad_conf_entry {
u16 offset;
u16 val;
};
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)

125
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -57,7 +57,10 @@
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
@ -131,87 +134,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
struct omap_sys_ctrl_regs {
u32 pad0[77]; /* 0x4A002000 */
u32 control_status; /* 0x4A002134 */
u32 pad1[794]; /* 0x4A002138 */
u32 control_paconf_global; /* 0x4A002DA0 */
u32 control_paconf_mode; /* 0x4A002DA4 */
u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
u32 control_smart1io_padconf_1; /* 0x4A002DAC */
u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
u32 control_smart2io_padconf_2; /* 0x4A002DBC */
u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
u32 pad2[14];
u32 control_pbias; /* 0x4A002E00 */
u32 control_i2c_0; /* 0x4A002E04 */
u32 control_camera_rx; /* 0x4A002E08 */
u32 control_hdmi_tx_phy; /* 0x4A002E0C */
u32 control_uniportm; /* 0x4A002E10 */
u32 control_dsiphy; /* 0x4A002E14 */
u32 control_mcbsplp; /* 0x4A002E18 */
u32 control_usb2phycore; /* 0x4A002E1C */
u32 control_hdmi_1; /*0x4A002E20*/
u32 control_hsi; /*0x4A002E24*/
u32 pad3[2];
u32 control_ddr3ch1_0; /*0x4A002E30*/
u32 control_ddr3ch2_0; /*0x4A002E34*/
u32 control_ddrch1_0; /*0x4A002E38*/
u32 control_ddrch1_1; /*0x4A002E3C*/
u32 control_ddrch2_0; /*0x4A002E40*/
u32 control_ddrch2_1; /*0x4A002E44*/
u32 control_lpddr2ch1_0; /*0x4A002E48*/
u32 control_lpddr2ch1_1; /*0x4A002E4C*/
u32 control_ddrio_0; /*0x4A002E50*/
u32 control_ddrio_1; /*0x4A002E54*/
u32 control_ddrio_2; /*0x4A002E58*/
u32 control_hyst_1; /*0x4A002E5C*/
u32 control_usbb_hsic_control; /*0x4A002E60*/
u32 control_c2c; /*0x4A002E64*/
u32 control_core_control_spare_rw; /*0x4A002E68*/
u32 control_core_control_spare_r; /*0x4A002E6C*/
u32 control_core_control_spare_r_c0; /*0x4A002E70*/
u32 control_srcomp_north_side; /*0x4A002E74*/
u32 control_srcomp_south_side; /*0x4A002E78*/
u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/
u32 pad4[3679394];
u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
u32 pad5[10];
u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
u32 pad6[789];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */
u32 control_xtal_oscillator; /* 0x4AE0CDAC */
u32 control_i2c_2; /* 0x4AE0CDB0 */
u32 control_ckobuffer; /* 0x4AE0CDB4 */
u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
u32 control_efuse_1; /* 0x4AE0CDC8 */
u32 control_efuse_2; /* 0x4AE0CDCC */
u32 control_efuse_3; /* 0x4AE0CDD0 */
u32 control_efuse_4; /* 0x4AE0CDD4 */
u32 control_efuse_5; /* 0x4AE0CDD8 */
u32 control_efuse_6; /* 0x4AE0CDDC */
u32 control_efuse_7; /* 0x4AE0CDE0 */
u32 control_efuse_8; /* 0x4AE0CDE4 */
u32 control_efuse_9; /* 0x4AE0CDE8 */
u32 control_efuse_10; /* 0x4AE0CDEC */
u32 control_efuse_11; /* 0x4AE0CDF0 */
u32 control_efuse_12; /* 0x4AE0CDF4 */
u32 control_efuse_13; /* 0x4AE0CDF8 */
};
/* Output impedance control */
#define ds_120_ohm 0x0
#define ds_60_ohm 0x1
@ -247,6 +169,12 @@ struct omap_sys_ctrl_regs {
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100
@ -271,7 +199,11 @@ struct omap_sys_ctrl_regs {
#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
@ -298,7 +230,26 @@ struct omap_sys_ctrl_regs {
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
/* CONTROL_SRCOMP_XXX_SIDE */
#define OVERRIDE_XS_SHIFT 30
#define OVERRIDE_XS_MASK (1 << 30)
#define SRCODE_READ_XS_SHIFT 12
#define SRCODE_READ_XS_MASK (0xff << 12)
#define PWRDWN_XS_SHIFT 11
#define PWRDWN_XS_MASK (1 << 11)
#define DIVIDE_FACTOR_XS_SHIFT 4
#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
#define MULTIPLY_FACTOR_XS_SHIFT 1
#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
#ifndef __ASSEMBLY__
struct srcomp_params {
s8 divide_factor;
s8 multiply_factor;
};
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
@ -306,5 +257,15 @@ struct omap_boot_parameters {
unsigned char reset_reason;
unsigned char ch_flags;
};
struct ctrl_ioregs {
u32 ctrl_ddrch;
u32 ctrl_lpddr2ch;
u32 ctrl_ddr3ch;
u32 ctrl_ddrio_0;
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
};
#endif /* __ASSEMBLY__ */
#endif

2
arch/arm/include/asm/arch-omap5/spl.h
View File

@ -27,7 +27,7 @@
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
#define BOOT_DEVICE_ONE_NAND 4
#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7

10
arch/arm/include/asm/arch-omap5/sys_proto.h
View File

@ -25,9 +25,13 @@
#include <asm/io.h>
#include <asm/arch/clocks.h>
#include <asm/omap_common.h>
#include <asm/arch/mux_omap5.h>
#include <asm/arch/clocks.h>
struct pad_conf_entry {
u32 offset;
u32 val;
};
struct omap_sysinfo {
char *board_string;
};
@ -44,7 +48,7 @@ u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap5_ddr_clk(void);
@ -58,6 +62,8 @@ void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
/*
* This is used to verify if the configuration header

2
arch/arm/include/asm/arch-tegra/mmc.h
View File

@ -22,6 +22,6 @@
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
void tegra_mmc_init(void);
#endif /* _TEGRA_MMC_H_ */

6
arch/arm/include/asm/arch-tegra/tegra_i2c.h
View File

@ -105,6 +105,7 @@ struct i2c_ctlr {
u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
u32 reserved_2[4]; /* 40: */
struct i2c_control control; /* 50 ~ 68 */
u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
};
/* bit fields definitions for IO Packet Header 1 format */
@ -154,6 +155,11 @@ struct i2c_ctlr {
#define I2C_INT_ARBITRATION_LOST_SHIFT 2
#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
/* I2C_CLK_DIVISOR_REGISTER */
#define CLK_DIV_STD_FAST_MODE 0x19
#define CLK_DIV_HS_MODE 1
#define CLK_MULT_STD_FAST_MODE 8
/**
* Returns the bus number of the DVC controller
*

48
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View File

@ -22,10 +22,9 @@
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
#define TEGRA_SDMMC1_BASE 0xC8000000
#define TEGRA_SDMMC2_BASE 0xC8000200
#define TEGRA_SDMMC3_BASE 0xC8000400
#define TEGRA_SDMMC4_BASE 0xC8000600
#include <fdtdec.h>
#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
#ifndef __ASSEMBLY__
struct tegra_mmc {
@ -62,12 +61,30 @@ struct tegra_mmc {
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
unsigned int res6[47]; /* 0x124 ~ 0x1DC */
unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
};
#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
@ -117,15 +134,26 @@ struct tegra_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
/* SDMMC1/3 settings from section 24.6 of T30 TRM */
#define MEMCOMP_PADCTRL_VREF 7
#define AUTO_CAL_ENABLED (1 << 29)
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
struct mmc_host {
struct tegra_mmc *reg;
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
struct fdt_gpio_state pwr_gpio; /* Power GPIO */
struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
int pwr_gpio; /* Power GPIO */
int cd_gpio; /* Change Detect GPIO */
};
void pad_init_mmc(struct mmc_host *host);
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */

22
arch/arm/include/asm/arch-tegra20/usb.h → arch/arm/include/asm/arch-tegra/usb.h
View File

@ -243,29 +243,7 @@ struct usb_ctlr {
#define VBUS_VLD_STS (1 << 26)
/* Change the USB host port into host mode */
void usb_set_host_mode(void);
/* Setup USB on the board */
int board_usb_init(const void *blob);
/**
* Start up the given port number (ports are numbered from 0 on each board).
* This returns values for the appropriate hccr and hcor addresses to use for
* USB EHCI operations.
*
* @param portnum port number to start
* @param hccr returns start address of EHCI HCCR registers
* @param hcor returns start address of EHCI HCOR registers
* @return 0 if ok, -1 on error (generally invalid port number)
*/
int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
/**
* Stop the current port
*
* @return 0 if ok, -1 if no port was active
*/
int tegrausb_stop_port(int portnum);
#endif /* _TEGRA_USB_H_ */

34
arch/arm/include/asm/arch-tegra114/gp_padctrl.h
View File

@ -27,7 +27,7 @@ struct apb_misc_gp_ctlr {
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
@ -35,25 +35,43 @@ struct apb_misc_gp_ctlr {
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
u32 reserved1; /* 0x8C: */
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
u32 reserved2[3]; /* 0xA4 - 0xAC: */
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
u32 reserved1[7]; /* 0xD0-0xE8: */
u32 reserved3[9]; /* 0xC8-0xE8: */
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
u32 reserved4[3]; /* 0xF0-0xF8: */
u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
u32 reserved5[3]; /* 0x104-0x10C: */
u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
u32 reserved6; /* 0x128: */
u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
u32 reserved7[2]; /* 0x130 - 0x134: */
u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
u32 reserved8[22]; /* 0x13C - 0x190: */
u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
#endif /* _TEGRA114_GP_PADCTRL_H_ */

246
arch/arm/include/asm/arch-tegra114/pinmux.h
View File

@ -50,72 +50,12 @@ enum pmux_pingrp {
PINGRP_SDMMC1_DAT2,
PINGRP_SDMMC1_DAT1,
PINGRP_SDMMC1_DAT0,
PINGRP_GPIO_PV2,
PINGRP_GPIO_PV3,
PINGRP_CLK2_OUT,
PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
PINGRP_CLK2_REQ,
PINGRP_LCD_PWR1,
PINGRP_LCD_PWR2,
PINGRP_LCD_SDIN,
PINGRP_LCD_SDOUT,
PINGRP_LCD_WR_N,
PINGRP_LCD_CS0_N,
PINGRP_LCD_DC0,
PINGRP_LCD_SCK,
PINGRP_LCD_PWR0,
PINGRP_LCD_PCLK,
PINGRP_LCD_DE,
PINGRP_LCD_HSYNC,
PINGRP_LCD_VSYNC,
PINGRP_LCD_D0,
PINGRP_LCD_D1,
PINGRP_LCD_D2,
PINGRP_LCD_D3,
PINGRP_LCD_D4,
PINGRP_LCD_D5,
PINGRP_LCD_D6,
PINGRP_LCD_D7,
PINGRP_LCD_D8,
PINGRP_LCD_D9,
PINGRP_LCD_D10,
PINGRP_LCD_D11,
PINGRP_LCD_D12,
PINGRP_LCD_D13,
PINGRP_LCD_D14,
PINGRP_LCD_D15,
PINGRP_LCD_D16,
PINGRP_LCD_D17,
PINGRP_LCD_D18,
PINGRP_LCD_D19,
PINGRP_LCD_D20,
PINGRP_LCD_D21,
PINGRP_LCD_D22,
PINGRP_LCD_D23,
PINGRP_LCD_CS1_N,
PINGRP_LCD_M1,
PINGRP_LCD_DC1,
PINGRP_HDMI_INT,
PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
PINGRP_DDC_SCL,
PINGRP_DDC_SDA,
PINGRP_CRT_HSYNC,
PINGRP_CRT_VSYNC,
PINGRP_VI_D0,
PINGRP_VI_D1,
PINGRP_VI_D2,
PINGRP_VI_D3,
PINGRP_VI_D4,
PINGRP_VI_D5,
PINGRP_VI_D6,
PINGRP_VI_D7,
PINGRP_VI_D8,
PINGRP_VI_D9,
PINGRP_VI_D10,
PINGRP_VI_D11,
PINGRP_VI_PCLK,
PINGRP_VI_MCLK,
PINGRP_VI_VSYNC,
PINGRP_VI_HSYNC,
PINGRP_UART2_RXD,
PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
PINGRP_UART2_TXD,
PINGRP_UART2_RTS_N,
PINGRP_UART2_CTS_N,
@ -186,8 +126,7 @@ enum pmux_pingrp {
PINGRP_SDMMC4_DAT5,
PINGRP_SDMMC4_DAT6,
PINGRP_SDMMC4_DAT7,
PINGRP_SDMMC4_RST_N,
PINGRP_CAM_MCLK,
PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
PINGRP_GPIO_PCC1,
PINGRP_GPIO_PBB0,
PINGRP_CAM_I2C_SCL,
@ -212,12 +151,7 @@ enum pmux_pingrp {
PINGRP_KB_ROW8,
PINGRP_KB_ROW9,
PINGRP_KB_ROW10,
PINGRP_KB_ROW11,
PINGRP_KB_ROW12,
PINGRP_KB_ROW13,
PINGRP_KB_ROW14,
PINGRP_KB_ROW15,
PINGRP_KB_COL0,
PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
PINGRP_KB_COL1,
PINGRP_KB_COL2,
PINGRP_KB_COL3,
@ -244,47 +178,30 @@ enum pmux_pingrp {
PINGRP_DAP2_DIN,
PINGRP_DAP2_DOUT,
PINGRP_DAP2_SCLK,
PINGRP_SPI2_MOSI,
PINGRP_SPI2_MISO,
PINGRP_SPI2_CS0_N,
PINGRP_SPI2_SCK,
PINGRP_SPI1_MOSI,
PINGRP_SPI1_SCK,
PINGRP_SPI1_CS0_N,
PINGRP_SPI1_MISO,
PINGRP_SPI2_CS1_N,
PINGRP_SPI2_CS2_N,
PINGRP_SDMMC3_CLK,
PINGRP_DVFS_PWM,
PINGRP_GPIO_X1_AUD,
PINGRP_GPIO_X3_AUD,
PINGRP_DVFS_CLK,
PINGRP_GPIO_X4_AUD,
PINGRP_GPIO_X5_AUD,
PINGRP_GPIO_X6_AUD,
PINGRP_GPIO_X7_AUD,
PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
PINGRP_SDMMC3_CMD,
PINGRP_SDMMC3_DAT0,
PINGRP_SDMMC3_DAT1,
PINGRP_SDMMC3_DAT2,
PINGRP_SDMMC3_DAT3,
PINGRP_SDMMC3_DAT4,
PINGRP_SDMMC3_DAT5,
PINGRP_SDMMC3_DAT6,
PINGRP_SDMMC3_DAT7,
PINGRP_PEX_L0_PRSNT_N,
PINGRP_PEX_L0_RST_N,
PINGRP_PEX_L0_CLKREQ_N,
PINGRP_PEX_WAKE_N,
PINGRP_PEX_L1_PRSNT_N,
PINGRP_PEX_L1_RST_N,
PINGRP_PEX_L1_CLKREQ_N,
PINGRP_PEX_L2_PRSNT_N,
PINGRP_PEX_L2_RST_N,
PINGRP_PEX_L2_CLKREQ_N,
PINGRP_HDMI_CEC, /* offset 0x33e0 */
PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
PINGRP_SDMMC1_WP_N,
PINGRP_SDMMC3_CD_N,
PINGRP_SPI1_CS1_N,
PINGRP_SPI1_CS2_N,
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
PINGRP_GPIO_W2_AUD,
PINGRP_GPIO_W3_AUD,
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
PINGRP_USB_VBUS_EN1,
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
PINGRP_NAND_GMI_CLK_LB,
PINGRP_RESET_OUT_N,
PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
PINGRP_COUNT,
};
@ -298,41 +215,35 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_AT5,
PDRIVE_PINGROUP_CDEV1,
PDRIVE_PINGROUP_CDEV2,
PDRIVE_PINGROUP_CSUS,
PDRIVE_PINGROUP_DAP1,
PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
PDRIVE_PINGROUP_DAP2,
PDRIVE_PINGROUP_DAP3,
PDRIVE_PINGROUP_DAP4,
PDRIVE_PINGROUP_DBG,
PDRIVE_PINGROUP_LCD1,
PDRIVE_PINGROUP_LCD2,
PDRIVE_PINGROUP_SDIO2,
PDRIVE_PINGROUP_SDIO3,
PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
PDRIVE_PINGROUP_SPI,
PDRIVE_PINGROUP_UAA,
PDRIVE_PINGROUP_UAB,
PDRIVE_PINGROUP_UART2,
PDRIVE_PINGROUP_UART3,
PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
PDRIVE_PINGROUP_DDC,
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
PDRIVE_PINGROUP_GMA,
PDRIVE_PINGROUP_GMB,
PDRIVE_PINGROUP_GMC,
PDRIVE_PINGROUP_GMD,
PDRIVE_PINGROUP_GME,
PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
PDRIVE_PINGROUP_GMF,
PDRIVE_PINGROUP_GMG,
PDRIVE_PINGROUP_GMH,
PDRIVE_PINGROUP_OWR,
PDRIVE_PINGROUP_UAD,
PDRIVE_PINGROUP_GPV,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
PDRIVE_PINGROUP_AT6,
PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
PDRIVE_PINGROUP_DAP5,
PDRIVE_PINGROUP_VBUS,
PDRIVE_PINGROUP_AO3,
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
};
@ -401,6 +312,7 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
/* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK12,
@ -444,7 +356,7 @@ enum pmux_func {
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
/* End of Tegra3 MUX selectors */
PMUX_FUNC_USB,
PMUX_FUNC_SOC,
PMUX_FUNC_CPU,
@ -453,10 +365,12 @@ enum pmux_func {
PMUX_FUNC_PMI,
PMUX_FUNC_CLDVFS,
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
@ -492,6 +406,7 @@ enum pmux_tristate {
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
PMUX_PIN_NONE,
};
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
@ -525,6 +440,16 @@ enum pmux_pin_ioreset {
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_HIGH,
};
/* return 1 if a pin_rcv_sel_is in range */
#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
@ -546,10 +471,73 @@ enum pmux_vddio {
PMUX_VDDIO_NONE
};
/* T114 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
PDRIVE_PINGROUP_COUNT)
#define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE
#define PGRP_SLWR_MAX PGRP_SLWF_MAX
#define PGRP_DRVUP_NONE -1
#define PGRP_DRVUP_MAX 127
#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
#define PGRP_SCHMT_NONE -1
#define PGRP_HSM_NONE PGRP_SCHMT_NONE
/* return 1 if a padgrp is in range */
#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
/* return 1 if a slew-rate rising/falling edge value is in range */
#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
/* return 1 if a driver output pull-up/down strength code value is in range */
#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
/* return 1 if a low-power mode value is in range */
#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
/* Defines a pin group cfg's low-power mode select */
enum pgrp_lpmd {
PGRP_LPMD_X8 = 0,
PGRP_LPMD_X4,
PGRP_LPMD_X2,
PGRP_LPMD_X,
PGRP_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pgrp_schmt {
PGRP_SCHMT_DISABLE = 0,
PGRP_SCHMT_ENABLE = 1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pgrp_hsm {
PGRP_HSM_DISABLE = 0,
PGRP_HSM_ENABLE = 1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
struct padctrl_config {
enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
int slwf; /* falling edge slew */
int slwr; /* rising edge slew */
int drvup; /* pull-up drive strength */
int drvdn; /* pull-down drive strength */
enum pgrp_lpmd lpmd; /* low-power mode selection */
enum pgrp_schmt schmt; /* schmidt enable */
enum pgrp_hsm hsm; /* high-speed mode enable */
};
/* t114 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
PDRIVE_PINGROUP_COUNT)
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
@ -581,6 +569,8 @@ struct pingroup_config {
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
/* VIL/VIH receivers */
};
/* Set a pin group to tristate */
@ -615,4 +605,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
#endif /* _TEGRA114_PINMUX_H_ */
/**
* Set the GP pad configs
*
* @param config List of config items
* @param len Number of config items in list
*/
void padgrp_config_table(struct padctrl_config *config, int len);
#endif /* _TEGRA114_PINMUX_H_ */

1
arch/arm/include/asm/arch-tegra20/tegra.h
View File

@ -29,7 +29,6 @@
#include <asm/arch-tegra/tegra.h>
#define TEGRA_USB1_BASE 0xC5000000
#define TEGRA_USB3_BASE 0xC5008000
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */

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