imx: mx6sl: Set the preclk clock source to OSC 24Mhz
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
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@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void)
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writel(0, &mxc_ccm->ccdr);
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writel(0, &mxc_ccm->ccdr);
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}
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}
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#ifdef CONFIG_MX6SL
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static void set_preclk_from_osc(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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u32 reg;
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reg = readl(&mxc_ccm->cscmr1);
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reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
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writel(reg, &mxc_ccm->cscmr1);
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}
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#endif
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int arch_cpu_init(void)
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int arch_cpu_init(void)
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{
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{
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init_aips();
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init_aips();
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@ -254,6 +266,11 @@ int arch_cpu_init(void)
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if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
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if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
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set_ahb_rate(132000000);
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set_ahb_rate(132000000);
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/* Set perclk to source from OSC 24MHz */
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#if defined(CONFIG_MX6SL)
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set_preclk_from_osc();
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#endif
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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#ifdef CONFIG_APBH_DMA
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#ifdef CONFIG_APBH_DMA
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