board/p1010rdb:Add NAND boot support using new SPL format
- defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
Andy Fleming
parent
3a88179d03
commit
0fa934d235
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@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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COBJS-y += spl_minimal.o tlb.o law.o
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else
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -31,11 +31,18 @@
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long ddr_freq_mhz;
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void sdram_init(void)
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{
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 ddr_ratio;
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unsigned long ddr_freq_mhz;
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ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
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ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
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/* mask off E bit */
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u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
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@ -81,6 +88,7 @@ void sdram_init(void)
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__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
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}
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asm volatile("sync;isync");
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udelay(500);
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/* Let the controller go */
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@ -91,7 +99,7 @@ void sdram_init(void)
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, ddr_ratio;
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* initialize selected port with appropriate baud rate */
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@ -99,10 +107,6 @@ void board_init_f(ulong bootflag)
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
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ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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@ -115,8 +119,8 @@ void board_init_f(ulong bootflag)
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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@ -43,16 +43,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_8K, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_NAND_SPL
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SDCARD
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 3, BOOKE_PAGESZ_16M, 1),
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#endif
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#ifdef CONFIG_PCI
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#ifndef CONFIG_PCI
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 7, BOOKE_PAGESZ_1M, 1),
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 8, BOOKE_PAGESZ_1G, 1)
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@ -48,15 +48,25 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#ifdef CONFIG_NAND /* NAND Boot */
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#define CONFIG_RAMBOOT_NAND
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
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#else
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#endif /* CONFIG_NAND_SPL */
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#ifdef CONFIG_NAND
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#define CONFIG_SPL
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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@ -74,8 +84,10 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/* High Level Configuration Options */
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@ -242,7 +254,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* Don't relocate CCSRBAR while in NAND_SPL */
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#ifdef CONFIG_NAND_SPL
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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@ -268,6 +280,10 @@ extern unsigned long get_sdram_size(void);
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* IFC Definitions
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*/
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/* NOR Flash on IFC */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_NO_FLASH
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#endif
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#define CONFIG_SYS_FLASH_BASE 0xee000000
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
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@ -353,7 +369,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NAND_DDR_LAW 11
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/* Set up IFC registers for boot location NOR/NAND */
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
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#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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@ -385,15 +401,6 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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/* NAND boot: 8K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
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/* CPLD on IFC */
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#define CONFIG_SYS_CPLD_BASE 0xffb00000
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@ -421,8 +428,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CS3_FTIM3 0x0
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#endif /* CONFIG_SDCARD */
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#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
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defined(CONFIG_RAMBOOT_NAND)
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#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#else
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@ -457,7 +463,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_NAND_SPL
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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@ -512,7 +518,7 @@ extern unsigned long get_sdram_size(void);
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* SPI interface will not be available in case of NAND boot SPI CS0 will be
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* used for SLIC
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*/
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#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
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#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
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/* eSPI - Enhanced SPI */
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#define CONFIG_FSL_ESPI
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#define CONFIG_SPI_FLASH
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@ -607,7 +613,6 @@ extern unsigned long get_sdram_size(void);
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/*
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* Environment
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*/
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_SDCARD)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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@ -622,16 +627,15 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_NAND_U_BOOT)
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#elif defined(CONFIG_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
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#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#else
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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@ -1,142 +0,0 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# Copyright 2011 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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NAND_SPL := y
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CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
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PAD_TO := 0xff802000
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include $(TOPDIR)/config.mk
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nandobj := $(OBJTREE)/nand_spl/
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LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
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LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
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$(LDFLAGS_FINAL)
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AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o ticks.o
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COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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all: $(obj).depend $(ALL)
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map \
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-o $(nandobj)u-boot-spl
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$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
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$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \
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-ansi -D__ASSEMBLY__ -P - <$< >$@
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# create symbolic links for common files
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$(obj)cache.c:
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@rm -f $(obj)cache.c
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ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
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$(obj)cpu_init_early.c:
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@rm -f $(obj)cpu_init_early.c
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ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
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$(obj)spl_minimal.c:
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@rm -f $(obj)spl_minimal.c
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ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
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$(obj)fsl_law.c:
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@rm -f $(obj)fsl_law.c
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
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$(obj)law.c:
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@rm -f $(obj)law.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
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$(obj)nand_boot_fsl_ifc.c:
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@rm -f $(obj)nand_boot_fsl_ifc.c
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ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
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$(obj)nand_boot_fsl_ifc.c
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$(obj)ns16550.c:
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@rm -f $(obj)ns16550.c
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)resetvec.S:
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@rm -f $(obj)resetvec.S
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ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
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$(obj)fixed_ivor.S:
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@rm -f $(obj)fixed_ivor.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
|
||||
|
||||
$(obj)start.S: $(obj)fixed_ivor.S
|
||||
@rm -f $(obj)start.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
|
||||
|
||||
$(obj)ticks.S:
|
||||
@rm -f $(obj)ticks.S
|
||||
ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
|
||||
|
||||
$(obj)tlb.c:
|
||||
@rm -f $(obj)tlb.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
|
||||
|
||||
$(obj)tlb_table.c:
|
||||
@rm -f $(obj)tlb_table.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
|
||||
|
||||
ifneq ($(OBJTREE), $(SRCTREE))
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
|
||||
endif
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -1,271 +0,0 @@
|
|||
/*
|
||||
* NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
static inline int is_blank(uchar *addr, int page_size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < page_size; i++) {
|
||||
if (__raw_readb(&addr[i]) != 0xff)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* For the SPL, don't worry about uncorrectable errors
|
||||
* where the main area is all FFs but shouldn't be.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* returns nonzero if entire page is blank */
|
||||
static inline int check_read_ecc(uchar *buf, u32 *eccstat,
|
||||
unsigned int bufnum, int page_size)
|
||||
{
|
||||
u32 reg = eccstat[bufnum / 4];
|
||||
int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
|
||||
|
||||
if (errors == 15) { /* uncorrectable */
|
||||
/* Blank pages fail hw ECC checks */
|
||||
if (is_blank(buf, page_size))
|
||||
return 1;
|
||||
|
||||
puts("ecc error\n");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void nand_wait(uchar *buf, int bufnum, int page_size)
|
||||
{
|
||||
struct fsl_ifc *ifc = IFC_BASE_ADDR;
|
||||
u32 status;
|
||||
u32 eccstat[4];
|
||||
int bufperpage = page_size / 512;
|
||||
int bufnum_end, i;
|
||||
|
||||
bufnum *= bufperpage;
|
||||
bufnum_end = bufnum + bufperpage - 1;
|
||||
|
||||
do {
|
||||
status = in_be32(&ifc->ifc_nand.nand_evter_stat);
|
||||
} while (!(status & IFC_NAND_EVTER_STAT_OPC));
|
||||
|
||||
if (status & IFC_NAND_EVTER_STAT_FTOER) {
|
||||
puts("flash time out error\n");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
for (i = bufnum / 4; i <= bufnum_end / 4; i++)
|
||||
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
|
||||
|
||||
for (i = bufnum; i <= bufnum_end; i++) {
|
||||
if (check_read_ecc(buf, eccstat, i, page_size))
|
||||
break;
|
||||
}
|
||||
|
||||
out_be32(&ifc->ifc_nand.nand_evter_stat, status);
|
||||
}
|
||||
|
||||
static inline int bad_block(uchar *marker, int port_size)
|
||||
{
|
||||
if (port_size == 8)
|
||||
return __raw_readb(marker) != 0xff;
|
||||
else
|
||||
return __raw_readw((u16 *)marker) != 0xffff;
|
||||
}
|
||||
|
||||
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
|
||||
{
|
||||
struct fsl_ifc *ifc = IFC_BASE_ADDR;
|
||||
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
|
||||
int page_size;
|
||||
int port_size;
|
||||
int pages_per_blk;
|
||||
int blk_size;
|
||||
int bad_marker = 0;
|
||||
int bufnum_mask, bufnum;
|
||||
|
||||
int csor, cspr;
|
||||
int pos = 0;
|
||||
int j = 0;
|
||||
|
||||
int sram_addr;
|
||||
int pg_no;
|
||||
|
||||
/* Get NAND Flash configuration */
|
||||
csor = CONFIG_SYS_NAND_CSOR;
|
||||
cspr = CONFIG_SYS_NAND_CSPR;
|
||||
|
||||
if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
|
||||
/* soft ECC in SPL is unimplemented */
|
||||
puts("WARNING: soft ECC not checked in SPL\n");
|
||||
} else {
|
||||
u32 hwcsor;
|
||||
|
||||
/* make sure board is configured with ECC on boot */
|
||||
hwcsor = in_be32(&ifc->csor_cs[0].csor);
|
||||
if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
|
||||
puts("WARNING: ECC not checked in SPL, "
|
||||
"check board cfg\n");
|
||||
}
|
||||
|
||||
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
|
||||
|
||||
if (csor & CSOR_NAND_PGS_4K) {
|
||||
page_size = 4096;
|
||||
bufnum_mask = 1;
|
||||
} else if (csor & CSOR_NAND_PGS_2K) {
|
||||
page_size = 2048;
|
||||
bufnum_mask = 3;
|
||||
} else {
|
||||
page_size = 512;
|
||||
bufnum_mask = 15;
|
||||
|
||||
if (port_size == 8)
|
||||
bad_marker = 5;
|
||||
}
|
||||
|
||||
pages_per_blk =
|
||||
32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
|
||||
|
||||
blk_size = pages_per_blk * page_size;
|
||||
|
||||
/* Open Full SRAM mapping for spare are access */
|
||||
out_be32(&ifc->ifc_nand.ncfgr, 0x0);
|
||||
|
||||
/* Clear Boot events */
|
||||
out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
|
||||
|
||||
/* Program FIR/FCR for Large/Small page */
|
||||
if (page_size > 512) {
|
||||
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
|
||||
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
|
||||
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
|
||||
|
||||
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
|
||||
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
|
||||
} else {
|
||||
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
|
||||
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
|
||||
|
||||
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||
}
|
||||
|
||||
/* Program FBCR = 0 for full page read */
|
||||
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
||||
|
||||
/* Read and copy u-boot on SDRAM from NAND device, In parallel
|
||||
* check for Bad block if found skip it and read continue to
|
||||
* next Block
|
||||
*/
|
||||
while (pos < uboot_size) {
|
||||
int i = 0;
|
||||
do {
|
||||
pg_no = offs / page_size;
|
||||
bufnum = pg_no & bufnum_mask;
|
||||
sram_addr = bufnum * page_size * 2;
|
||||
|
||||
out_be32(&ifc->ifc_nand.row0, pg_no);
|
||||
out_be32(&ifc->ifc_nand.col0, 0);
|
||||
/* start read */
|
||||
out_be32(&ifc->ifc_nand.nandseq_strt,
|
||||
IFC_NAND_SEQ_STRT_FIR_STRT);
|
||||
|
||||
/* wait for read to complete */
|
||||
nand_wait(&buf[sram_addr], bufnum, page_size);
|
||||
|
||||
/*
|
||||
* If either of the first two pages are marked bad,
|
||||
* continue to the next block.
|
||||
*/
|
||||
if (i++ < 2 &&
|
||||
bad_block(&buf[sram_addr + page_size + bad_marker],
|
||||
port_size)) {
|
||||
puts("skipping\n");
|
||||
offs = (offs + blk_size) & ~(blk_size - 1);
|
||||
pos &= ~(blk_size - 1);
|
||||
break;
|
||||
}
|
||||
|
||||
for (j = 0; j < page_size; j++)
|
||||
dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
|
||||
|
||||
pos += page_size;
|
||||
offs += page_size;
|
||||
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
|
||||
* configured and available since this code loads the main U-boot image
|
||||
* from NAND into SDRAM and starts from there.
|
||||
*/
|
||||
void nand_boot(void)
|
||||
{
|
||||
__attribute__((noreturn)) void (*uboot)(void);
|
||||
|
||||
/*
|
||||
* Load U-Boot image from NAND into RAM
|
||||
*/
|
||||
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
|
||||
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
|
||||
|
||||
#ifdef CONFIG_NAND_ENV_DST
|
||||
nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_NAND_ENV_DST);
|
||||
|
||||
#ifdef CONFIG_ENV_OFFSET_REDUND
|
||||
nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Jump to U-Boot image
|
||||
*/
|
||||
/*
|
||||
* Clean d-cache and invalidate i-cache, to
|
||||
* make sure that no stale data is executed.
|
||||
*/
|
||||
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
|
||||
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
|
||||
uboot();
|
||||
}
|
||||
Loading…
Reference in New Issue