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patch - arm - define SYS_CACHELINE_SIZE for mx5 

mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards

Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too

Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Matthew Starr <mstarr@hedonline.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Chris Kuethe 2015-06-02 16:31:43 -07:00 committed by Stefano Babic
parent 3d0158ae18
commit 1005ccda97
1 changed files with 2 additions and 0 deletions
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2
arch/arm/include/asm/arch-mx5/imx-regs.h
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@ -9,6 +9,8 @@
#define ARCH_MXC
#define CONFIG_SYS_CACHELINE_SIZE 64
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000