board/w7o/fpga.c: make (mostly) checkpatch clean
Just reformated the code. No attempts were made to clean up warnings about "Use of volatile is usually wrong" or "externs should be avoided". Signed-off-by: Wolfgang Denk <wd@denx.de>
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fb82fd7a32
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@ -54,9 +54,7 @@ fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
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int
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int
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fpgaDownload(unsigned char *saddr,
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fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
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unsigned long size,
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unsigned short *daddr)
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{
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{
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int i; /* index, intr disable flag */
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int i; /* index, intr disable flag */
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int start; /* timer */
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int start; /* timer */
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@ -86,8 +84,8 @@ fpgaDownload(unsigned char *saddr,
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/* Setup timeout timer */
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/* Setup timeout timer */
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start = get_timer(0);
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start = get_timer(0);
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/* Wait for FPGA init line */
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/* Wait for FPGA init line to go low */
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while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
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while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
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/* Check for timeout - 100us max, so use 3ms */
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/* Check for timeout - 100us max, so use 3ms */
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if (get_timer(start) > 3) {
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if (get_timer(start) > 3) {
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printf(" failed to start init.\n");
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printf(" failed to start init.\n");
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@ -102,8 +100,8 @@ fpgaDownload(unsigned char *saddr,
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grego |= GPIO_XCV_PROG; /* PROG line high */
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grego |= GPIO_XCV_PROG; /* PROG line high */
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out32(PPC405GP_GPIO0_OR, grego);
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out32(PPC405GP_GPIO0_OR, grego);
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/* Wait for FPGA end of init period . */
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/* Wait for FPGA end of init period = init line go hi */
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while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
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while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
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/* Check for timeout */
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/* Check for timeout */
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if (get_timer(start) > 3) {
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if (get_timer(start) > 3) {
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@ -161,7 +159,8 @@ fpgaDownload(unsigned char *saddr,
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greg &= ~eirq; /* toggle irq/gpio */
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greg &= ~eirq; /* toggle irq/gpio */
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mtdcr(CPC0_CR0, greg); /* ... just do it */
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mtdcr(CPC0_CR0, greg); /* ... just do it */
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ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */
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/* XXX - Next FPGA addr */
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ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
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cnfg >>= 1; /* XXX - Next */
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cnfg >>= 1; /* XXX - Next */
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eirq >>= 1;
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eirq >>= 1;
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}
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}
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@ -179,8 +178,8 @@ fpgaDownload(unsigned char *saddr,
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/* Setup timer */
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/* Setup timer */
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start = get_timer(0);
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start = get_timer(0);
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/* Wait for FPGA end of programming period . */
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/* Wait for FPGA end of programming period = Test DONE low */
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while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
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while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
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/* Check for timeout */
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/* Check for timeout */
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if (get_timer(start) > 3) {
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if (get_timer(start) > 3) {
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@ -240,9 +239,9 @@ int init_fpga(void)
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/*
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/*
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* Get the file name pointer and length.
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* Get the file name pointer and length.
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* filename length is next short
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*/
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*/
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fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length
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fn_len = (*(unsigned short *) (buf + 12) & 0xff);
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is next short */
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fn_buf = buf + 14;
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fn_buf = buf + 14;
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/*
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/*
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@ -252,7 +251,8 @@ int init_fpga(void)
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xcv_len = len - 14 - fn_len; /* fpga image length */
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xcv_len = len - 14 - fn_len; /* fpga image length */
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/* Check for uninitialized FLASH */
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/* Check for uninitialized FLASH */
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if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
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if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
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|| (len == 0))
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goto bad_image;
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goto bad_image;
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/*
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/*
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@ -268,7 +268,8 @@ int init_fpga(void)
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printf("file name : ");
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printf("file name : ");
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for (i = 0; i < fn_len; i++) {
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for (i = 0; i < fn_len; i++) {
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bufchar = fn_buf[+i];
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bufchar = fn_buf[+i];
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if (bufchar<' ' || bufchar>'~') bufchar = '.';
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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putc(bufchar);
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}
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}
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@ -278,7 +279,8 @@ int init_fpga(void)
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ptr = 15; /* Offset to ncd filename
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ptr = 15; /* Offset to ncd filename
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length in fpga image */
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length in fpga image */
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j = xcv_buf[ptr]; /* Get len of ncd filename */
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j = xcv_buf[ptr]; /* Get len of ncd filename */
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if (j > 32) goto bad_image;
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if (j > 32)
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goto bad_image;
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ptr = ptr + j + 3; /* skip ncd filename string +
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ptr = ptr + j + 3; /* skip ncd filename string +
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3 bytes more bytes */
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3 bytes more bytes */
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@ -286,11 +288,13 @@ int init_fpga(void)
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* output target device string
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* output target device string
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*/
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*/
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j = xcv_buf[ptr++] - 1; /* len of targ str less term */
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j = xcv_buf[ptr++] - 1; /* len of targ str less term */
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if (j > 32) goto bad_image;
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if (j > 32)
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goto bad_image;
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printf("\n target : ");
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printf("\n target : ");
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for (i = 0; i < j; i++) {
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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bufchar = (xcv_buf[ptr++]);
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if (bufchar<' ' || bufchar>'~') bufchar = '.';
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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putc(bufchar);
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}
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}
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@ -300,20 +304,24 @@ int init_fpga(void)
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ptr += 3; /* skip 2 bytes */
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ptr += 3; /* skip 2 bytes */
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printf("\n synth time : ");
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printf("\n synth time : ");
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j = (xcv_buf[ptr++] - 1); /* len of date str less term */
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j = (xcv_buf[ptr++] - 1); /* len of date str less term */
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if (j > 32) goto bad_image;
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if (j > 32)
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goto bad_image;
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for (i = 0; i < j; i++) {
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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bufchar = (xcv_buf[ptr++]);
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if (bufchar<' ' || bufchar>'~') bufchar = '.';
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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putc(bufchar);
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}
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}
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ptr += 3; /* Skip 2 bytes */
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ptr += 3; /* Skip 2 bytes */
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printf(" - ");
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printf(" - ");
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j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
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j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
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if (j > 32) goto bad_image;
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if (j > 32)
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goto bad_image;
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for (i = 0; i < j; i++) {
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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bufchar = (xcv_buf[ptr++]);
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if (bufchar<' ' || bufchar>'~') bufchar = '.';
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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putc(bufchar);
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}
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}
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@ -330,7 +338,8 @@ int init_fpga(void)
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return retval;
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return retval;
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bad_image:
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bad_image:
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printf("\n BAD FPGA image format @ %lx\n", flash_info[1].start[0]);
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printf("\n BAD FPGA image format @ %lx\n",
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flash_info[1].start[0]);
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log_warn(ERR_XIMAGE);
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log_warn(ERR_XIMAGE);
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done:
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done:
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return retval;
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return retval;
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@ -361,12 +370,10 @@ void test_fpga(unsigned short *daddr)
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ndest[0x4801] = 0xaa55;
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ndest[0x4801] = 0xaa55;
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ndest[0x4802] = 0xc318;
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ndest[0x4802] = 0xc318;
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if ((ndest[0x800] != 0x55aa) ||
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if ((ndest[0x800] != 0x55aa) ||
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(ndest[0x801] != 0xaa55) ||
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(ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
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(ndest[0x802] != 0xc318))
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log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
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log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
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if ((ndest[0x4800] != 0x55aa) ||
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if ((ndest[0x4800] != 0x55aa) ||
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(ndest[0x4801] != 0xaa55) ||
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(ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
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(ndest[0x4802] != 0xc318))
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log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
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log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
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#else
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#else
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