clk: uniphier: move U_BOOT_DRIVER entry to core code
Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c) to the core support file (clk-uniphier-core.c) because I do not want to repeat the driver boilerplate when I add more clock data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -14,6 +14,35 @@
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#include "clk-uniphier.h"
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#include "clk-uniphier.h"
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/**
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* struct uniphier_clk_priv - private data for UniPhier clock driver
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*
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* @base: base address of the clock provider
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* @socdata: SoC specific data
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*/
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struct uniphier_clk_priv {
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void __iomem *base;
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const struct uniphier_clk_soc_data *socdata;
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};
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int uniphier_clk_probe(struct udevice *dev)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = dev_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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if (!priv->base)
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return -ENOMEM;
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priv->socdata = (void *)dev_get_driver_data(dev);
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return 0;
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}
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static int uniphier_clk_enable(struct clk *clk)
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static int uniphier_clk_enable(struct clk *clk)
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{
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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@ -128,20 +157,47 @@ const struct clk_ops uniphier_clk_ops = {
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.set_rate = uniphier_clk_set_rate,
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.set_rate = uniphier_clk_set_rate,
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};
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};
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int uniphier_clk_probe(struct udevice *dev)
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static const struct udevice_id uniphier_clk_match[] = {
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{
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{
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struct uniphier_clk_priv *priv = dev_get_priv(dev);
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.compatible = "socionext,ph1-sld3-mioctrl",
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fdt_addr_t addr;
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-sld8-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro5-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,proxstream2-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld11-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld20-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{ /* sentinel */ }
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};
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addr = dev_get_addr(dev);
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U_BOOT_DRIVER(uniphier_clk) = {
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if (addr == FDT_ADDR_T_NONE)
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.name = "uniphier-clk",
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return -EINVAL;
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.id = UCLASS_CLK,
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.of_match = uniphier_clk_match,
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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.probe = uniphier_clk_probe,
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if (!priv->base)
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.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
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return -ENOMEM;
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.ops = &uniphier_clk_ops,
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};
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priv->socdata = (void *)dev_get_driver_data(dev);
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return 0;
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}
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@ -132,54 +132,9 @@ static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
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UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
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UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
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};
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};
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static const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
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const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
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.gate = uniphier_mio_clk_gate,
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.gate = uniphier_mio_clk_gate,
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.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
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.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
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.rate = uniphier_mio_clk_rate,
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.rate = uniphier_mio_clk_rate,
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.nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
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.nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
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};
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};
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static const struct udevice_id uniphier_mio_clk_match[] = {
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{
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.compatible = "socionext,ph1-sld3-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-sld8-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro5-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,proxstream2-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld11-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld20-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_mio_clk) = {
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.name = "uniphier-mio-clk",
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.id = UCLASS_CLK,
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.of_match = uniphier_mio_clk_match,
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.probe = uniphier_clk_probe,
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.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
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.ops = &uniphier_clk_ops,
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};
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@ -40,18 +40,6 @@ struct uniphier_clk_soc_data {
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.rate = f, \
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.rate = f, \
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}
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}
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/**
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extern const struct uniphier_clk_soc_data uniphier_mio_clk_data;
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* struct uniphier_clk_priv - private data for UniPhier clock driver
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*
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* @base: base address of the clock provider
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* @socdata: SoC specific data
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*/
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struct uniphier_clk_priv {
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void __iomem *base;
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const struct uniphier_clk_soc_data *socdata;
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};
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extern const struct clk_ops uniphier_clk_ops;
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int uniphier_clk_probe(struct udevice *dev);
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#endif /* __CLK_UNIPHIER_H__ */
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#endif /* __CLK_UNIPHIER_H__ */
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