Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
1199c377cf
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@ -112,6 +112,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
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return exynos_get_pll_clk(pllreg, r, k);
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}
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/* exynos4x12: return pll clock frequency */
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static unsigned long exynos4x12_get_pll_clk(int pllreg)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long r, k = 0;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con0);
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break;
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case MPLL:
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r = readl(&clk->mpll_con0);
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break;
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case EPLL:
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r = readl(&clk->epll_con0);
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k = readl(&clk->epll_con1);
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break;
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case VPLL:
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r = readl(&clk->vpll_con0);
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k = readl(&clk->vpll_con1);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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return exynos_get_pll_clk(pllreg, r, k);
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}
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/* exynos5: return pll clock frequency */
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static unsigned long exynos5_get_pll_clk(int pllreg)
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{
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@ -193,6 +223,28 @@ static unsigned long exynos4_get_arm_clk(void)
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return armclk;
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}
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/* exynos4x12: return ARM clock frequency */
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static unsigned long exynos4x12_get_arm_clk(void)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long armclk;
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unsigned int core_ratio;
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unsigned int core2_ratio;
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div = readl(&clk->div_cpu0);
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/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
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core_ratio = (div >> 0) & 0x7;
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core2_ratio = (div >> 28) & 0x7;
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armclk = get_pll_clk(APLL) / (core_ratio + 1);
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armclk /= (core2_ratio + 1);
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return armclk;
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}
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/* exynos5: return ARM clock frequency */
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static unsigned long exynos5_get_arm_clk(void)
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{
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@ -258,6 +310,20 @@ static unsigned long exynos4_get_pwm_clk(void)
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return pclk;
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}
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/* exynos4x12: return pwm clock frequency */
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static unsigned long exynos4x12_get_pwm_clk(void)
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{
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unsigned long pclk, sclk;
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unsigned int ratio;
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sclk = get_pll_clk(MPLL);
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ratio = 8;
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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/* exynos5: return pwm clock frequency */
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static unsigned long exynos5_get_pwm_clk(void)
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{
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@ -326,6 +392,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
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return uclk;
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}
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/* exynos4x12: return uart clock frequency */
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static unsigned long exynos4x12_get_uart_clk(int dev_index)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_PERIL0
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* UART0_SEL [3:0]
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* UART1_SEL [7:4]
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* UART2_SEL [8:11]
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* UART3_SEL [12:15]
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* UART4_SEL [16:19]
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*/
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sel = readl(&clk->src_peril0);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIL0
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* UART0_RATIO [3:0]
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* UART1_RATIO [7:4]
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* UART2_RATIO [8:11]
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* UART3_RATIO [12:15]
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* UART4_RATIO [16:19]
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*/
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ratio = readl(&clk->div_peril0);
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ratio = (ratio >> (dev_index << 2)) & 0xf;
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uclk = sclk / (ratio + 1);
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return uclk;
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}
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/* exynos5: return uart clock frequency */
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static unsigned long exynos5_get_uart_clk(int dev_index)
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{
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@ -373,6 +484,100 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
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return uclk;
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}
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static unsigned long exynos4_get_mmc_clk(int dev_index)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel, ratio, pre_ratio;
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int shift;
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sel = readl(&clk->src_fsys);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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switch (dev_index) {
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case 0:
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case 1:
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ratio = readl(&clk->div_fsys1);
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pre_ratio = readl(&clk->div_fsys1);
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break;
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case 2:
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case 3:
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ratio = readl(&clk->div_fsys2);
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pre_ratio = readl(&clk->div_fsys2);
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break;
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case 4:
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ratio = readl(&clk->div_fsys3);
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pre_ratio = readl(&clk->div_fsys3);
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break;
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default:
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return 0;
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}
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if (dev_index == 1 || dev_index == 3)
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shift = 16;
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ratio = (ratio >> shift) & 0xf;
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pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
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uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
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return uclk;
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}
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static unsigned long exynos5_get_mmc_clk(int dev_index)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel, ratio, pre_ratio;
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int shift;
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sel = readl(&clk->src_fsys);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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switch (dev_index) {
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case 0:
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case 1:
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ratio = readl(&clk->div_fsys1);
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pre_ratio = readl(&clk->div_fsys1);
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break;
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case 2:
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case 3:
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ratio = readl(&clk->div_fsys2);
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pre_ratio = readl(&clk->div_fsys2);
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break;
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default:
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return 0;
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}
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if (dev_index == 1 || dev_index == 3)
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shift = 16;
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ratio = (ratio >> shift) & 0xf;
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pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
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uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
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return uclk;
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}
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/* exynos4: set the mmc clock */
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static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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{
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@ -381,6 +586,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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* CLK_DIV_FSYS2
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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* CLK_DIV_FSYS3
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* MMC4_PRE_RATIO [15:8]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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} else if (dev_index == 4) {
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addr = (unsigned int)&clk->div_fsys3;
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dev_index -= 4;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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}
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/* exynos4x12: set the mmc clock */
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static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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@ -603,7 +840,7 @@ void exynos5_set_lcd_clk(void)
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*/
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cfg = readl(&clk->src_disp1_0);
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cfg &= ~(0xf);
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cfg |= 0x8;
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cfg |= 0x6;
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writel(cfg, &clk->src_disp1_0);
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/*
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@ -940,16 +1177,22 @@ unsigned long get_pll_clk(int pllreg)
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{
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if (cpu_is_exynos5())
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return exynos5_get_pll_clk(pllreg);
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_pll_clk(pllreg);
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return exynos4_get_pll_clk(pllreg);
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}
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}
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unsigned long get_arm_clk(void)
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{
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if (cpu_is_exynos5())
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return exynos5_get_arm_clk();
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_arm_clk();
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return exynos4_get_arm_clk();
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}
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}
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unsigned long get_i2c_clk(void)
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@ -968,24 +1211,41 @@ unsigned long get_pwm_clk(void)
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{
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if (cpu_is_exynos5())
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return exynos5_get_pwm_clk();
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_pwm_clk();
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return exynos4_get_pwm_clk();
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}
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}
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unsigned long get_uart_clk(int dev_index)
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{
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if (cpu_is_exynos5())
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return exynos5_get_uart_clk(dev_index);
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else
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else {
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if (proid_is_exynos4412())
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return exynos4x12_get_uart_clk(dev_index);
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return exynos4_get_uart_clk(dev_index);
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}
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}
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unsigned long get_mmc_clk(int dev_index)
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{
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if (cpu_is_exynos5())
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return exynos5_get_mmc_clk(dev_index);
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else
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return exynos4_get_mmc_clk(dev_index);
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}
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void set_mmc_clk(int dev_index, unsigned int div)
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{
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if (cpu_is_exynos5())
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exynos5_set_mmc_clk(dev_index, div);
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else
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else {
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if (proid_is_exynos4412())
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exynos4x12_set_mmc_clk(dev_index, div);
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exynos4_set_mmc_clk(dev_index, div);
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}
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}
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unsigned long get_lcd_clk(void)
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|
|
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@ -22,6 +22,7 @@
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/sromc.h>
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|
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@ -370,6 +371,43 @@ static void exynos4_i2c_config(int peripheral, int flags)
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}
|
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}
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static int exynos4_mmc_config(int peripheral, int flags)
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{
|
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struct exynos4_gpio_part2 *gpio2 =
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(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
|
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struct s5p_gpio_bank *bank, *bank_ext;
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int i;
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|
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switch (peripheral) {
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case PERIPH_ID_SDMMC0:
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bank = &gpio2->k0;
|
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bank_ext = &gpio2->k1;
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break;
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case PERIPH_ID_SDMMC2:
|
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bank = &gpio2->k2;
|
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bank_ext = &gpio2->k3;
|
||||
break;
|
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default:
|
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return -1;
|
||||
}
|
||||
for (i = 0; i < 7; i++) {
|
||||
if (i == 2)
|
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continue;
|
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s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
|
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
|
||||
}
|
||||
if (flags & PINMUX_FLAG_8BIT_MODE) {
|
||||
for (i = 3; i < 7; i++) {
|
||||
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
|
||||
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_pinmux_config(int peripheral, int flags)
|
||||
{
|
||||
switch (peripheral) {
|
||||
|
|
@ -383,6 +421,14 @@ static int exynos4_pinmux_config(int peripheral, int flags)
|
|||
case PERIPH_ID_I2C7:
|
||||
exynos4_i2c_config(peripheral, flags);
|
||||
break;
|
||||
case PERIPH_ID_SDMMC0:
|
||||
case PERIPH_ID_SDMMC2:
|
||||
return exynos4_mmc_config(peripheral, flags);
|
||||
case PERIPH_ID_SDMMC1:
|
||||
case PERIPH_ID_SDMMC3:
|
||||
case PERIPH_ID_SDMMC4:
|
||||
printf("SDMMC device %d not implemented\n", peripheral);
|
||||
return -1;
|
||||
default:
|
||||
debug("%s: invalid peripheral %d", __func__, peripheral);
|
||||
return -1;
|
||||
|
|
@ -402,3 +448,31 @@ int exynos_pinmux_config(int peripheral, int flags)
|
|||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
|
||||
{
|
||||
int err;
|
||||
u32 cell[3];
|
||||
|
||||
err = fdtdec_get_int_array(blob, node, "interrupts", cell,
|
||||
ARRAY_SIZE(cell));
|
||||
if (err)
|
||||
return PERIPH_ID_NONE;
|
||||
|
||||
/* check for invalid peripheral id */
|
||||
if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
|
||||
return cell[1];
|
||||
|
||||
debug(" invalid peripheral id\n");
|
||||
return PERIPH_ID_NONE;
|
||||
}
|
||||
|
||||
int pinmux_decode_periph_id(const void *blob, int node)
|
||||
{
|
||||
if (cpu_is_exynos5())
|
||||
return exynos5_pinmux_decode_periph_id(blob, node);
|
||||
else
|
||||
return PERIPH_ID_NONE;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* SAMSUNG EXYNOS5250 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
|
||||
* EXYNOS5250 based board files can include this file and provide
|
||||
* values for board specfic bindings.
|
||||
*
|
||||
* Note: This file does not include device nodes for all the controllers in
|
||||
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
|
||||
* additional nodes can be added to this file.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos5250";
|
||||
|
||||
sromc@12250000 {
|
||||
compatible = "samsung,exynos-sromc";
|
||||
reg = <0x12250000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@12c60000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C60000 0x100>;
|
||||
interrupts = <0 56 0>;
|
||||
};
|
||||
|
||||
i2c@12c70000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C70000 0x100>;
|
||||
interrupts = <0 57 0>;
|
||||
};
|
||||
|
||||
i2c@12c80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C80000 0x100>;
|
||||
interrupts = <0 58 0>;
|
||||
};
|
||||
|
||||
i2c@12c90000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12C90000 0x100>;
|
||||
interrupts = <0 59 0>;
|
||||
};
|
||||
|
||||
i2c@12ca0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CA0000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
};
|
||||
|
||||
i2c@12cb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CB0000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
};
|
||||
|
||||
i2c@12cc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CC0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
i2c@12cd0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-i2c";
|
||||
reg = <0x12CD0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
|
||||
sound@12d60000 {
|
||||
compatible = "samsung,exynos-sound";
|
||||
reg = <0x12d60000 0x20>;
|
||||
};
|
||||
|
||||
spi@12d20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x12d20000 0x30>;
|
||||
interrupts = <0 68 0>;
|
||||
};
|
||||
|
||||
spi@12d30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x12d30000 0x30>;
|
||||
interrupts = <0 69 0>;
|
||||
};
|
||||
|
||||
spi@12d40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x12d40000 0x30>;
|
||||
clock-frequency = <50000000>;
|
||||
interrupts = <0 70 0>;
|
||||
};
|
||||
|
||||
spi@131a0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x131a0000 0x30>;
|
||||
interrupts = <0 129 0>;
|
||||
};
|
||||
|
||||
spi@131b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x131b0000 0x30>;
|
||||
interrupts = <0 130 0>;
|
||||
};
|
||||
|
||||
ehci@12110000 {
|
||||
compatible = "samsung,exynos-ehci";
|
||||
reg = <0x12110000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
phy {
|
||||
compatible = "samsung,exynos-usb-phy";
|
||||
reg = <0x12130000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -34,6 +34,7 @@ unsigned long get_arm_clk(void);
|
|||
unsigned long get_i2c_clk(void);
|
||||
unsigned long get_pwm_clk(void);
|
||||
unsigned long get_uart_clk(int dev_index);
|
||||
unsigned long get_mmc_clk(int dev_index);
|
||||
void set_mmc_clk(int dev_index, unsigned int div);
|
||||
unsigned long get_lcd_clk(void);
|
||||
void set_lcd_clk(void);
|
||||
|
|
|
|||
|
|
@ -251,6 +251,282 @@ struct exynos4_clock {
|
|||
unsigned int div_iem_l1;
|
||||
};
|
||||
|
||||
struct exynos4x12_clock {
|
||||
unsigned char res1[0x4200];
|
||||
unsigned int src_leftbus;
|
||||
unsigned char res2[0x1fc];
|
||||
unsigned int mux_stat_leftbus;
|
||||
unsigned char res3[0xfc];
|
||||
unsigned int div_leftbus;
|
||||
unsigned char res4[0xfc];
|
||||
unsigned int div_stat_leftbus;
|
||||
unsigned char res5[0x1fc];
|
||||
unsigned int gate_ip_leftbus;
|
||||
unsigned char res6[0x12c];
|
||||
unsigned int gate_ip_image;
|
||||
unsigned char res7[0xcc];
|
||||
unsigned int clkout_leftbus;
|
||||
unsigned int clkout_leftbus_div_stat;
|
||||
unsigned char res8[0x37f8];
|
||||
unsigned int src_rightbus;
|
||||
unsigned char res9[0x1fc];
|
||||
unsigned int mux_stat_rightbus;
|
||||
unsigned char res10[0xfc];
|
||||
unsigned int div_rightbus;
|
||||
unsigned char res11[0xfc];
|
||||
unsigned int div_stat_rightbus;
|
||||
unsigned char res12[0x1fc];
|
||||
unsigned int gate_ip_rightbus;
|
||||
unsigned char res13[0x15c];
|
||||
unsigned int gate_ip_perir;
|
||||
unsigned char res14[0x9c];
|
||||
unsigned int clkout_rightbus;
|
||||
unsigned int clkout_rightbus_div_stat;
|
||||
unsigned char res15[0x3608];
|
||||
unsigned int epll_lock;
|
||||
unsigned char res16[0xc];
|
||||
unsigned int vpll_lock;
|
||||
unsigned char res17[0xec];
|
||||
unsigned int epll_con0;
|
||||
unsigned int epll_con1;
|
||||
unsigned int epll_con2;
|
||||
unsigned char res18[0x4];
|
||||
unsigned int vpll_con0;
|
||||
unsigned int vpll_con1;
|
||||
unsigned int vpll_con2;
|
||||
unsigned char res19[0xe4];
|
||||
unsigned int src_top0;
|
||||
unsigned int src_top1;
|
||||
unsigned char res20[0x8];
|
||||
unsigned int src_cam;
|
||||
unsigned int src_tv;
|
||||
unsigned int src_mfc;
|
||||
unsigned int src_g3d;
|
||||
unsigned char res21[0x4];
|
||||
unsigned int src_lcd;
|
||||
unsigned int src_isp;
|
||||
unsigned int src_maudio;
|
||||
unsigned int src_fsys;
|
||||
unsigned char res22[0xc];
|
||||
unsigned int src_peril0;
|
||||
unsigned int src_peril1;
|
||||
unsigned int src_cam1;
|
||||
unsigned char res23[0xb4];
|
||||
unsigned int src_mask_top;
|
||||
unsigned char res24[0xc];
|
||||
unsigned int src_mask_cam;
|
||||
unsigned int src_mask_tv;
|
||||
unsigned char res25[0xc];
|
||||
unsigned int src_mask_lcd;
|
||||
unsigned int src_mask_isp;
|
||||
unsigned int src_mask_maudio;
|
||||
unsigned int src_mask_fsys;
|
||||
unsigned char res26[0xc];
|
||||
unsigned int src_mask_peril0;
|
||||
unsigned int src_mask_peril1;
|
||||
unsigned char res27[0xb8];
|
||||
unsigned int mux_stat_top0;
|
||||
unsigned int mux_stat_top1;
|
||||
unsigned char res28[0x10];
|
||||
unsigned int mux_stat_mfc;
|
||||
unsigned int mux_stat_g3d;
|
||||
unsigned char res29[0x28];
|
||||
unsigned int mux_stat_cam1;
|
||||
unsigned char res30[0xb4];
|
||||
unsigned int div_top;
|
||||
unsigned char res31[0xc];
|
||||
unsigned int div_cam;
|
||||
unsigned int div_tv;
|
||||
unsigned int div_mfc;
|
||||
unsigned int div_g3d;
|
||||
unsigned char res32[0x4];
|
||||
unsigned int div_lcd;
|
||||
unsigned int div_isp;
|
||||
unsigned int div_maudio;
|
||||
unsigned int div_fsys0;
|
||||
unsigned int div_fsys1;
|
||||
unsigned int div_fsys2;
|
||||
unsigned int div_fsys3;
|
||||
unsigned int div_peril0;
|
||||
unsigned int div_peril1;
|
||||
unsigned int div_peril2;
|
||||
unsigned int div_peril3;
|
||||
unsigned int div_peril4;
|
||||
unsigned int div_peril5;
|
||||
unsigned int div_cam1;
|
||||
unsigned char res33[0x14];
|
||||
unsigned int div2_ratio;
|
||||
unsigned char res34[0x8c];
|
||||
unsigned int div_stat_top;
|
||||
unsigned char res35[0xc];
|
||||
unsigned int div_stat_cam;
|
||||
unsigned int div_stat_tv;
|
||||
unsigned int div_stat_mfc;
|
||||
unsigned int div_stat_g3d;
|
||||
unsigned char res36[0x4];
|
||||
unsigned int div_stat_lcd;
|
||||
unsigned int div_stat_isp;
|
||||
unsigned int div_stat_maudio;
|
||||
unsigned int div_stat_fsys0;
|
||||
unsigned int div_stat_fsys1;
|
||||
unsigned int div_stat_fsys2;
|
||||
unsigned int div_stat_fsys3;
|
||||
unsigned int div_stat_peril0;
|
||||
unsigned int div_stat_peril1;
|
||||
unsigned int div_stat_peril2;
|
||||
unsigned int div_stat_peril3;
|
||||
unsigned int div_stat_peril4;
|
||||
unsigned int div_stat_peril5;
|
||||
unsigned int div_stat_cam1;
|
||||
unsigned char res37[0x14];
|
||||
unsigned int div2_stat;
|
||||
unsigned char res38[0x29c];
|
||||
unsigned int gate_ip_cam;
|
||||
unsigned int gate_ip_tv;
|
||||
unsigned int gate_ip_mfc;
|
||||
unsigned int gate_ip_g3d;
|
||||
unsigned char res39[0x4];
|
||||
unsigned int gate_ip_lcd;
|
||||
unsigned int gate_ip_isp;
|
||||
unsigned char res40[0x4];
|
||||
unsigned int gate_ip_fsys;
|
||||
unsigned char res41[0x8];
|
||||
unsigned int gate_ip_gps;
|
||||
unsigned int gate_ip_peril;
|
||||
unsigned char res42[0xc];
|
||||
unsigned char res43[0x4];
|
||||
unsigned char res44[0xc];
|
||||
unsigned int gate_block;
|
||||
unsigned char res45[0x8c];
|
||||
unsigned int clkout_cmu_top;
|
||||
unsigned int clkout_cmu_top_div_stat;
|
||||
unsigned char res46[0x3600];
|
||||
unsigned int mpll_lock;
|
||||
unsigned char res47[0xfc];
|
||||
unsigned int mpll_con0;
|
||||
unsigned int mpll_con1;
|
||||
unsigned char res48[0xf0];
|
||||
unsigned int src_dmc;
|
||||
unsigned char res49[0xfc];
|
||||
unsigned int src_mask_dmc;
|
||||
unsigned char res50[0xfc];
|
||||
unsigned int mux_stat_dmc;
|
||||
unsigned char res51[0xfc];
|
||||
unsigned int div_dmc0;
|
||||
unsigned int div_dmc1;
|
||||
unsigned char res52[0xf8];
|
||||
unsigned int div_stat_dmc0;
|
||||
unsigned int div_stat_dmc1;
|
||||
unsigned char res53[0xf8];
|
||||
unsigned int gate_bus_dmc0;
|
||||
unsigned int gate_bus_dmc1;
|
||||
unsigned char res54[0x1f8];
|
||||
unsigned int gate_ip_dmc0;
|
||||
unsigned int gate_ip_dmc1;
|
||||
unsigned char res55[0xf8];
|
||||
unsigned int clkout_cmu_dmc;
|
||||
unsigned int clkout_cmu_dmc_div_stat;
|
||||
unsigned char res56[0x5f8];
|
||||
unsigned int dcgidx_map0;
|
||||
unsigned int dcgidx_map1;
|
||||
unsigned int dcgidx_map2;
|
||||
unsigned char res57[0x14];
|
||||
unsigned int dcgperf_map0;
|
||||
unsigned int dcgperf_map1;
|
||||
unsigned char res58[0x18];
|
||||
unsigned int dvcidx_map;
|
||||
unsigned char res59[0x1c];
|
||||
unsigned int freq_cpu;
|
||||
unsigned int freq_dpm;
|
||||
unsigned char res60[0x18];
|
||||
unsigned int dvsemclk_en;
|
||||
unsigned int maxperf;
|
||||
unsigned char res61[0x8];
|
||||
unsigned int dmc_freq_ctrl;
|
||||
unsigned int dmc_pause_ctrl;
|
||||
unsigned int dddrphy_lock_ctrl;
|
||||
unsigned int c2c_state;
|
||||
unsigned char res62[0x2f60];
|
||||
unsigned int apll_lock;
|
||||
unsigned char res63[0x8];
|
||||
unsigned char res64[0xf4];
|
||||
unsigned int apll_con0;
|
||||
unsigned int apll_con1;
|
||||
unsigned char res65[0xf8];
|
||||
unsigned int src_cpu;
|
||||
unsigned char res66[0x1fc];
|
||||
unsigned int mux_stat_cpu;
|
||||
unsigned char res67[0xfc];
|
||||
unsigned int div_cpu0;
|
||||
unsigned int div_cpu1;
|
||||
unsigned char res68[0xf8];
|
||||
unsigned int div_stat_cpu0;
|
||||
unsigned int div_stat_cpu1;
|
||||
unsigned char res69[0x2f8];
|
||||
unsigned int clk_gate_ip_cpu;
|
||||
unsigned char res70[0xfc];
|
||||
unsigned int clkout_cmu_cpu;
|
||||
unsigned int clkout_cmu_cpu_div_stat;
|
||||
unsigned char res71[0x5f8];
|
||||
unsigned int armclk_stopctrl;
|
||||
unsigned int atclk_stopctrl;
|
||||
unsigned char res72[0x10];
|
||||
unsigned char res73[0x8];
|
||||
unsigned int pwr_ctrl;
|
||||
unsigned int pwr_ctrl2;
|
||||
unsigned char res74[0xd8];
|
||||
unsigned int apll_con0_l8;
|
||||
unsigned int apll_con0_l7;
|
||||
unsigned int apll_con0_l6;
|
||||
unsigned int apll_con0_l5;
|
||||
unsigned int apll_con0_l4;
|
||||
unsigned int apll_con0_l3;
|
||||
unsigned int apll_con0_l2;
|
||||
unsigned int apll_con0_l1;
|
||||
unsigned int iem_control;
|
||||
unsigned char res75[0xdc];
|
||||
unsigned int apll_con1_l8;
|
||||
unsigned int apll_con1_l7;
|
||||
unsigned int apll_con1_l6;
|
||||
unsigned int apll_con1_l5;
|
||||
unsigned int apll_con1_l4;
|
||||
unsigned int apll_con1_l3;
|
||||
unsigned int apll_con1_l2;
|
||||
unsigned int apll_con1_l1;
|
||||
unsigned char res76[0xe0];
|
||||
unsigned int div_iem_l8;
|
||||
unsigned int div_iem_l7;
|
||||
unsigned int div_iem_l6;
|
||||
unsigned int div_iem_l5;
|
||||
unsigned int div_iem_l4;
|
||||
unsigned int div_iem_l3;
|
||||
unsigned int div_iem_l2;
|
||||
unsigned int div_iem_l1;
|
||||
unsigned char res77[0xe0];
|
||||
unsigned int l2_status;
|
||||
unsigned char res78[0xc];
|
||||
unsigned int cpu_status;
|
||||
unsigned char res79[0xc];
|
||||
unsigned int ptm_status;
|
||||
unsigned char res80[0x2edc];
|
||||
unsigned int div_isp0;
|
||||
unsigned int div_isp1;
|
||||
unsigned char res81[0xf8];
|
||||
unsigned int div_stat_isp0;
|
||||
unsigned int div_stat_isp1;
|
||||
unsigned char res82[0x3f8];
|
||||
unsigned int gate_ip_isp0;
|
||||
unsigned int gate_ip_isp1;
|
||||
unsigned char res83[0x1f8];
|
||||
unsigned int clkout_cmu_isp;
|
||||
unsigned int clkout_cmu_ispd_div_stat;
|
||||
unsigned char res84[0xf8];
|
||||
unsigned int cmu_isp_spar0;
|
||||
unsigned int cmu_isp_spar1;
|
||||
unsigned int cmu_isp_spar2;
|
||||
unsigned int cmu_isp_spar3;
|
||||
};
|
||||
|
||||
struct exynos5_clock {
|
||||
unsigned int apll_lock;
|
||||
unsigned char res1[0xfc];
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#define EXYNOS_CPU_NAME "Exynos"
|
||||
#define EXYNOS4_ADDR_BASE 0x10000000
|
||||
|
||||
/* EXYNOS4 */
|
||||
/* EXYNOS4 Common*/
|
||||
#define EXYNOS4_I2C_SPACING 0x10000
|
||||
|
||||
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
|
||||
|
|
@ -63,7 +63,40 @@
|
|||
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS5 */
|
||||
/* EXYNOS4X12 */
|
||||
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
|
||||
#define EXYNOS4X12_PRO_ID 0x10000000
|
||||
#define EXYNOS4X12_SYSREG_BASE 0x10010000
|
||||
#define EXYNOS4X12_POWER_BASE 0x10020000
|
||||
#define EXYNOS4X12_SWRESET 0x10020400
|
||||
#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
|
||||
#define EXYNOS4X12_CLOCK_BASE 0x10030000
|
||||
#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
|
||||
#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
|
||||
#define EXYNOS4X12_DMC0_BASE 0x10600000
|
||||
#define EXYNOS4X12_DMC1_BASE 0x10610000
|
||||
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
|
||||
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
|
||||
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
|
||||
#define EXYNOS4X12_FIMD_BASE 0x11C00000
|
||||
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
|
||||
#define EXYNOS4X12_USBOTG_BASE 0x12480000
|
||||
#define EXYNOS4X12_MMC_BASE 0x12510000
|
||||
#define EXYNOS4X12_SROMC_BASE 0x12570000
|
||||
#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
|
||||
#define EXYNOS4X12_USBPHY_BASE 0x125B0000
|
||||
#define EXYNOS4X12_UART_BASE 0x13800000
|
||||
#define EXYNOS4X12_I2C_BASE 0x13860000
|
||||
#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
|
||||
|
||||
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS5 Common*/
|
||||
#define EXYNOS5_I2C_SPACING 0x10000
|
||||
|
||||
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
|
||||
|
|
@ -154,17 +187,20 @@ static inline int proid_is_##type(void) \
|
|||
}
|
||||
|
||||
IS_EXYNOS_TYPE(exynos4210, 0x4210)
|
||||
IS_EXYNOS_TYPE(exynos4412, 0x4412)
|
||||
IS_EXYNOS_TYPE(exynos5250, 0x5250)
|
||||
|
||||
#define SAMSUNG_BASE(device, base) \
|
||||
static inline unsigned int samsung_get_base_##device(void) \
|
||||
{ \
|
||||
if (cpu_is_exynos4()) \
|
||||
if (cpu_is_exynos4()) { \
|
||||
if (proid_is_exynos4412()) \
|
||||
return EXYNOS4X12_##base; \
|
||||
return EXYNOS4_##base; \
|
||||
else if (cpu_is_exynos5()) \
|
||||
} else if (cpu_is_exynos5()) { \
|
||||
return EXYNOS5_##base; \
|
||||
else \
|
||||
return 0; \
|
||||
} \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
SAMSUNG_BASE(adc, ADC_BASE)
|
||||
|
|
|
|||
|
|
@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
|
||||
|
||||
#endif /* _DP_INFO_H */
|
||||
|
|
|
|||
|
|
@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
|
|||
struct s5p_gpio_bank z;
|
||||
};
|
||||
|
||||
struct exynos4x12_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
struct s5p_gpio_bank b;
|
||||
struct s5p_gpio_bank c0;
|
||||
struct s5p_gpio_bank c1;
|
||||
struct s5p_gpio_bank d0;
|
||||
struct s5p_gpio_bank d1;
|
||||
struct s5p_gpio_bank res1[0x5];
|
||||
struct s5p_gpio_bank f0;
|
||||
struct s5p_gpio_bank f1;
|
||||
struct s5p_gpio_bank f2;
|
||||
struct s5p_gpio_bank f3;
|
||||
struct s5p_gpio_bank res2[0x2];
|
||||
struct s5p_gpio_bank j0;
|
||||
struct s5p_gpio_bank j1;
|
||||
};
|
||||
|
||||
struct exynos4x12_gpio_part2 {
|
||||
struct s5p_gpio_bank res1[0x2];
|
||||
struct s5p_gpio_bank k0;
|
||||
struct s5p_gpio_bank k1;
|
||||
struct s5p_gpio_bank k2;
|
||||
struct s5p_gpio_bank k3;
|
||||
struct s5p_gpio_bank l0;
|
||||
struct s5p_gpio_bank l1;
|
||||
struct s5p_gpio_bank l2;
|
||||
struct s5p_gpio_bank y0;
|
||||
struct s5p_gpio_bank y1;
|
||||
struct s5p_gpio_bank y2;
|
||||
struct s5p_gpio_bank y3;
|
||||
struct s5p_gpio_bank y4;
|
||||
struct s5p_gpio_bank y5;
|
||||
struct s5p_gpio_bank y6;
|
||||
struct s5p_gpio_bank res2[0x3];
|
||||
struct s5p_gpio_bank m0;
|
||||
struct s5p_gpio_bank m1;
|
||||
struct s5p_gpio_bank m2;
|
||||
struct s5p_gpio_bank m3;
|
||||
struct s5p_gpio_bank m4;
|
||||
struct s5p_gpio_bank res3[0x48];
|
||||
struct s5p_gpio_bank x0;
|
||||
struct s5p_gpio_bank x1;
|
||||
struct s5p_gpio_bank x2;
|
||||
struct s5p_gpio_bank x3;
|
||||
};
|
||||
|
||||
struct exynos4x12_gpio_part3 {
|
||||
struct s5p_gpio_bank z;
|
||||
};
|
||||
|
||||
struct exynos4x12_gpio_part4 {
|
||||
struct s5p_gpio_bank v0;
|
||||
struct s5p_gpio_bank v1;
|
||||
struct s5p_gpio_bank res1[0x1];
|
||||
struct s5p_gpio_bank v2;
|
||||
struct s5p_gpio_bank v3;
|
||||
struct s5p_gpio_bank res2[0x1];
|
||||
struct s5p_gpio_bank v4;
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
|
|
@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
|
|||
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
|
||||
|
||||
#define exynos4x12_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
|
||||
EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
|
||||
- EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin)
|
||||
|
||||
#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos4x12_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
|
||||
EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
|
||||
- EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
|
||||
|
||||
#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos4x12_gpio_part3_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
|
||||
EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
|
||||
- EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
|
||||
|
||||
#define exynos5_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
|
||||
EXYNOS5_GPIO_PART1_BASE)->bank)) \
|
||||
|
|
|
|||
|
|
@ -358,7 +358,14 @@ struct mipi_dsim_lcd_driver {
|
|||
void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
|
||||
};
|
||||
|
||||
#ifdef CONFIG_EXYNOS_MIPI_DSIM
|
||||
int exynos_mipi_dsi_init(void);
|
||||
#else
|
||||
static inline int exynos_mipi_dsi_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* register mipi_dsim_lcd_driver object defined by lcd panel driver
|
||||
|
|
|
|||
|
|
@ -25,12 +25,17 @@
|
|||
#define __ASM_ARM_ARCH_PERIPH_H
|
||||
|
||||
/*
|
||||
* Peripherals requiring clock/pinmux configuration. List will
|
||||
* Peripherals required for pinmux configuration. List will
|
||||
* grow with support for more devices getting added.
|
||||
* Numbering based on interrupt table.
|
||||
*
|
||||
*/
|
||||
enum periph_id {
|
||||
PERIPH_ID_I2C0,
|
||||
PERIPH_ID_UART0 = 51,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
PERIPH_ID_UART3,
|
||||
PERIPH_ID_I2C0 = 56,
|
||||
PERIPH_ID_I2C1,
|
||||
PERIPH_ID_I2C2,
|
||||
PERIPH_ID_I2C3,
|
||||
|
|
@ -38,22 +43,24 @@ enum periph_id {
|
|||
PERIPH_ID_I2C5,
|
||||
PERIPH_ID_I2C6,
|
||||
PERIPH_ID_I2C7,
|
||||
PERIPH_ID_I2S1,
|
||||
PERIPH_ID_SDMMC0,
|
||||
PERIPH_ID_SPI0 = 68,
|
||||
PERIPH_ID_SPI1,
|
||||
PERIPH_ID_SPI2,
|
||||
PERIPH_ID_SDMMC0 = 75,
|
||||
PERIPH_ID_SDMMC1,
|
||||
PERIPH_ID_SDMMC2,
|
||||
PERIPH_ID_SDMMC3,
|
||||
PERIPH_ID_SDMMC4,
|
||||
PERIPH_ID_SROMC,
|
||||
PERIPH_ID_SPI0,
|
||||
PERIPH_ID_SPI1,
|
||||
PERIPH_ID_SPI2,
|
||||
PERIPH_ID_I2S1 = 99,
|
||||
|
||||
/* Since following peripherals do
|
||||
* not have shared peripheral interrupts (SPIs)
|
||||
* they are numbered arbitiraly after the maximum
|
||||
* SPIs Exynos has (128)
|
||||
*/
|
||||
PERIPH_ID_SROMC = 128,
|
||||
PERIPH_ID_SPI3,
|
||||
PERIPH_ID_SPI4,
|
||||
PERIPH_ID_UART0,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
PERIPH_ID_UART3,
|
||||
PERIPH_ID_SDMMC4,
|
||||
|
||||
PERIPH_ID_COUNT,
|
||||
PERIPH_ID_NONE = -1,
|
||||
|
|
|
|||
|
|
@ -55,4 +55,12 @@ enum {
|
|||
*/
|
||||
int exynos_pinmux_config(int peripheral, int flags);
|
||||
|
||||
/**
|
||||
* Decode the peripheral id using the interrpt numbers.
|
||||
*
|
||||
* @param blob Device tree blob
|
||||
* @param node FDT I2C node to find
|
||||
* @return peripheral id if ok, PERIPH_ID_NONE on error
|
||||
*/
|
||||
int pinmux_decode_periph_id(const void *blob, int node);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -48,4 +48,22 @@ struct s5p_sromc {
|
|||
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
|
||||
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
|
||||
|
||||
enum {
|
||||
FDT_SROM_PMC,
|
||||
FDT_SROM_TACP,
|
||||
FDT_SROM_TAH,
|
||||
FDT_SROM_TCOH,
|
||||
FDT_SROM_TACC,
|
||||
FDT_SROM_TCOS,
|
||||
FDT_SROM_TACS,
|
||||
|
||||
FDT_SROM_TIMING_COUNT,
|
||||
};
|
||||
|
||||
struct fdt_sromc {
|
||||
u8 bank; /* srom bank number */
|
||||
u8 width; /* bus width in bytes */
|
||||
unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARCH_SROMC_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* SAMSUNG SMDK5250 board device tree source
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ ARCH_CPU_DTS
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
|
||||
compatible = "samsung,smdk5250", "samsung,exynos5250";
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@12c60000";
|
||||
i2c1 = "/i2c@12c70000";
|
||||
i2c2 = "/i2c@12c80000";
|
||||
i2c3 = "/i2c@12c90000";
|
||||
i2c4 = "/i2c@12ca0000";
|
||||
i2c5 = "/i2c@12cb0000";
|
||||
i2c6 = "/i2c@12cc0000";
|
||||
i2c7 = "/i2c@12cd0000";
|
||||
spi0 = "/spi@12d20000";
|
||||
spi1 = "/spi@12d30000";
|
||||
spi2 = "/spi@12d40000";
|
||||
spi3 = "/spi@131a0000";
|
||||
spi4 = "/spi@131b0000";
|
||||
};
|
||||
|
||||
sromc@12250000 {
|
||||
bank = <1>;
|
||||
srom-timing = <1 9 12 1 6 1 1>;
|
||||
width = <2>;
|
||||
lan@5000000 {
|
||||
compatible = "smsc,lan9215", "smsc,lan";
|
||||
reg = <0x5000000 0x100>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
};
|
||||
|
||||
sound@12d60000 {
|
||||
samsung,i2s-epll-clock-frequency = <192000000>;
|
||||
samsung,i2s-sampling-rate = <48000>;
|
||||
samsung,i2s-bits-per-sample = <16>;
|
||||
samsung,i2s-channels = <2>;
|
||||
samsung,i2s-lr-clk-framesize = <256>;
|
||||
samsung,i2s-bit-clk-framesize = <32>;
|
||||
samsung,codec-type = "wm8994";
|
||||
};
|
||||
|
||||
i2c@12c70000 {
|
||||
soundcodec@1a {
|
||||
reg = <0x1a>;
|
||||
compatible = "wolfson,wm8994-codec";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12c60000 {
|
||||
pmic@9 {
|
||||
reg = <0x9>;
|
||||
compatible = "maxim,max77686_pmic";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -21,43 +21,35 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include <lcd.h>
|
||||
#include <netdev.h>
|
||||
#include <spi.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/power.h>
|
||||
#include <asm/arch/sromc.h>
|
||||
#include <asm/arch/dp_info.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SMC911X
|
||||
static int smc9115_pre_init(void)
|
||||
#ifdef CONFIG_USB_EHCI_EXYNOS
|
||||
int board_usb_vbus_init(void)
|
||||
{
|
||||
u32 smc_bw_conf, smc_bc_conf;
|
||||
int err;
|
||||
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
|
||||
samsung_get_base_gpio_part1();
|
||||
|
||||
/* Ethernet needs data bus width of 16 bits */
|
||||
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
|
||||
| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
|
||||
/* Enable VBUS power switch */
|
||||
s5p_gpio_direction_output(&gpio1->x2, 6, 1);
|
||||
|
||||
smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
|
||||
| SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
|
||||
| SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
|
||||
| SROMC_BC_PMC(0x01);
|
||||
/* VBUS turn ON time */
|
||||
mdelay(3);
|
||||
|
||||
/* Select and configure the SROMC bank */
|
||||
err = exynos_pinmux_config(PERIPH_ID_SROMC,
|
||||
CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
|
||||
if (err) {
|
||||
debug("SROMC not configured\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -67,6 +59,9 @@ int board_init(void)
|
|||
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
|
||||
#ifdef CONFIG_EXYNOS_SPI
|
||||
spi_init();
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI_EXYNOS
|
||||
board_usb_vbus_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -122,12 +117,94 @@ void dram_init_banksize(void)
|
|||
PHYS_SDRAM_8_SIZE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
static int decode_sromc(const void *blob, struct fdt_sromc *config)
|
||||
{
|
||||
int err;
|
||||
int node;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
|
||||
if (node < 0) {
|
||||
debug("Could not find SROMC node\n");
|
||||
return node;
|
||||
}
|
||||
|
||||
config->bank = fdtdec_get_int(blob, node, "bank", 0);
|
||||
config->width = fdtdec_get_int(blob, node, "width", 2);
|
||||
|
||||
err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
|
||||
FDT_SROM_TIMING_COUNT);
|
||||
if (err < 0) {
|
||||
debug("Could not decode SROMC configuration\n");
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_SMC911X
|
||||
if (smc9115_pre_init())
|
||||
u32 smc_bw_conf, smc_bc_conf;
|
||||
struct fdt_sromc config;
|
||||
fdt_addr_t base_addr;
|
||||
int node;
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
node = decode_sromc(gd->fdt_blob, &config);
|
||||
if (node < 0) {
|
||||
debug("%s: Could not find sromc configuration\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
|
||||
if (node < 0) {
|
||||
debug("%s: Could not find lan9215 configuration\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We now have a node, so any problems from now on are errors */
|
||||
base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
|
||||
if (base_addr == FDT_ADDR_T_NONE) {
|
||||
debug("%s: Could not find lan9215 address\n", __func__);
|
||||
return -1;
|
||||
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
}
|
||||
#else
|
||||
/* Non-FDT configuration - bank number and timing parameters*/
|
||||
config.bank = CONFIG_ENV_SROM_BANK;
|
||||
config.width = 2;
|
||||
|
||||
config.timing[FDT_SROM_TACS] = 0x01;
|
||||
config.timing[FDT_SROM_TCOS] = 0x01;
|
||||
config.timing[FDT_SROM_TACC] = 0x06;
|
||||
config.timing[FDT_SROM_TCOH] = 0x01;
|
||||
config.timing[FDT_SROM_TAH] = 0x0C;
|
||||
config.timing[FDT_SROM_TACP] = 0x09;
|
||||
config.timing[FDT_SROM_PMC] = 0x01;
|
||||
base_addr = CONFIG_SMC911X_BASE;
|
||||
#endif
|
||||
|
||||
/* Ethernet needs data bus width of 16 bits */
|
||||
if (config.width != 2) {
|
||||
debug("%s: Unsupported bus width %d\n", __func__,
|
||||
config.width);
|
||||
return -1;
|
||||
}
|
||||
smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
|
||||
| SROMC_BYTE_ENABLE(config.bank);
|
||||
|
||||
smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
|
||||
SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
|
||||
SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
|
||||
SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
|
||||
SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
|
||||
SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
|
||||
SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
|
||||
|
||||
/* Select and configure the SROMC bank */
|
||||
exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
|
||||
s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
|
||||
return smc911x_initialize(0, base_addr);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -188,24 +265,6 @@ static int board_uart_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
||||
static int board_i2c_init(void)
|
||||
{
|
||||
int i, err;
|
||||
|
||||
for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
|
||||
err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
|
||||
PINMUX_FLAG_NONE);
|
||||
if (err) {
|
||||
debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
|
|
@ -216,8 +275,104 @@ int board_early_init_f(void)
|
|||
return err;
|
||||
}
|
||||
#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
||||
err = board_i2c_init();
|
||||
board_i2c_init(gd->fdt_blob);
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
void cfg_lcd_gpio(void)
|
||||
{
|
||||
struct exynos5_gpio_part1 *gpio1 =
|
||||
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
|
||||
|
||||
/* For Backlight */
|
||||
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
|
||||
s5p_gpio_set_value(&gpio1->b2, 0, 1);
|
||||
|
||||
/* LCD power on */
|
||||
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
|
||||
s5p_gpio_set_value(&gpio1->x1, 5, 1);
|
||||
|
||||
/* Set Hotplug detect for DP */
|
||||
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
|
||||
}
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_freq = 60,
|
||||
.vl_col = 2560,
|
||||
.vl_row = 1600,
|
||||
.vl_width = 2560,
|
||||
.vl_height = 1600,
|
||||
.vl_clkp = CONFIG_SYS_LOW,
|
||||
.vl_hsp = CONFIG_SYS_LOW,
|
||||
.vl_vsp = CONFIG_SYS_LOW,
|
||||
.vl_dp = CONFIG_SYS_LOW,
|
||||
.vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
|
||||
|
||||
/* wDP panel timing infomation */
|
||||
.vl_hspw = 32,
|
||||
.vl_hbpd = 80,
|
||||
.vl_hfpd = 48,
|
||||
|
||||
.vl_vspw = 6,
|
||||
.vl_vbpd = 37,
|
||||
.vl_vfpd = 3,
|
||||
.vl_cmd_allow_len = 0xf,
|
||||
|
||||
.win_id = 3,
|
||||
.cfg_gpio = cfg_lcd_gpio,
|
||||
.backlight_on = NULL,
|
||||
.lcd_power_on = NULL,
|
||||
.reset_lcd = NULL,
|
||||
.dual_lcd_enabled = 0,
|
||||
|
||||
.init_delay = 0,
|
||||
.power_on_delay = 0,
|
||||
.reset_delay = 0,
|
||||
.interface_mode = FIMD_RGB_INTERFACE,
|
||||
.dp_enabled = 1,
|
||||
};
|
||||
|
||||
static struct edp_device_info edp_info = {
|
||||
.disp_info = {
|
||||
.h_res = 2560,
|
||||
.h_sync_width = 32,
|
||||
.h_back_porch = 80,
|
||||
.h_front_porch = 48,
|
||||
.v_res = 1600,
|
||||
.v_sync_width = 6,
|
||||
.v_back_porch = 37,
|
||||
.v_front_porch = 3,
|
||||
.v_sync_rate = 60,
|
||||
},
|
||||
.lt_info = {
|
||||
.lt_status = DP_LT_NONE,
|
||||
},
|
||||
.video_info = {
|
||||
.master_mode = 0,
|
||||
.bist_mode = DP_DISABLE,
|
||||
.bist_pattern = NO_PATTERN,
|
||||
.h_sync_polarity = 0,
|
||||
.v_sync_polarity = 0,
|
||||
.interlaced = 0,
|
||||
.color_space = COLOR_RGB,
|
||||
.dynamic_range = VESA,
|
||||
.ycbcr_coeff = COLOR_YCBCR601,
|
||||
.color_depth = COLOR_8,
|
||||
},
|
||||
};
|
||||
|
||||
static struct exynos_dp_platform_data dp_platform_data = {
|
||||
.phy_enable = set_dp_phy_ctrl,
|
||||
.edp_dev_info = &edp_info,
|
||||
};
|
||||
|
||||
void init_panel_info(vidinfo_t *vid)
|
||||
{
|
||||
vid->rgb_mode = MODE_RGB_P,
|
||||
|
||||
exynos_set_dp_platform_data(&dp_platform_data);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ struct s3c_plat_otg_data s5pc210_otg_data;
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
|
||||
|
||||
check_hw_revision();
|
||||
printf("HW Revision:\t0x%x\n", board_rev);
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
|||
{
|
||||
int ret;
|
||||
|
||||
ret = sound_init();
|
||||
ret = sound_init(gd->fdt_blob);
|
||||
if (ret) {
|
||||
printf("Initialise Audio driver failed\n");
|
||||
return CMD_RET_FAILURE;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
Exynos ISP SPI Subsystem
|
||||
|
||||
The device node for ISP SPI subsytem.
|
||||
Since Peripheral id in EXYNOS is decoded based on Interrupts, currently
|
||||
ISP SPI have no individual interrupts hence we add ad dummy interrupt node
|
||||
which will have a value beyond the maximum number of interrupts exynos5 can
|
||||
support.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "samsung,exynos-spi" for spi.
|
||||
- reg : Base adrress of the the subsystem.
|
||||
- interrupts : A value which is beyond the maximum number of interrupts
|
||||
exynos5 can support.
|
||||
|
||||
Example:
|
||||
spi@131a0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos-spi";
|
||||
reg = <0x131a0000 0x30>;
|
||||
interrupts = <0 129 0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
Exynos Sound Subsystem
|
||||
|
||||
The device node for sound subsytem which contains codec and i2s block
|
||||
that is a part of Exynos5250
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "samsung,exynos-sound" for sound
|
||||
- samsung,i2s-epll-clock-frequency : epll clock output frequency in Hz
|
||||
- samsung,i2s-sampling-rate : sampling rate, default is 48000
|
||||
- samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
|
||||
- samsung,i2s-channels : nummber of channels, default is 2
|
||||
- samsung,i2s-lr-clk-framesize : lr clock frame size
|
||||
- samsung,i2s-bit-clk-framesize : bit clock frame size
|
||||
- samsung,codec-type : sound codec type
|
||||
|
||||
Example:
|
||||
|
||||
sound@12d60000 {
|
||||
compatible = "samsung,exynos-sound"
|
||||
samsung,i2s-epll-clock-frequency = <192000000>;
|
||||
samsung,i2s-sampling-rate = <48000>;
|
||||
samsung,i2s-bits-per-sample = <16>;
|
||||
samsung,i2s-channels = <2>;
|
||||
samsung,i2s-lr-clk-framesize = <256>;
|
||||
samsung,i2s-bit-clk-framesize = <32>;
|
||||
samsung,codec-type = "wm8994";
|
||||
};
|
||||
|
|
@ -27,9 +27,11 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#else
|
||||
#include <asm/arch/s3c24x0_cpu.h>
|
||||
#endif
|
||||
|
|
@ -60,7 +62,16 @@
|
|||
#define I2C_TIMEOUT 1 /* 1 second */
|
||||
|
||||
|
||||
static unsigned int g_current_bus; /* Stores Current I2C Bus */
|
||||
/*
|
||||
* For SPL boot some boards need i2c before SDRAM is initialised so force
|
||||
* variables to live in SRAM
|
||||
*/
|
||||
static unsigned int g_current_bus __attribute__((section(".data")));
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
static int i2c_busses __attribute__((section(".data")));
|
||||
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
|
||||
__attribute__((section(".data")));
|
||||
#endif
|
||||
|
||||
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
|
||||
static int GetI2CSDA(void)
|
||||
|
|
@ -512,4 +523,76 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
|
||||
len) != 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
void board_i2c_init(const void *blob)
|
||||
{
|
||||
int node_list[CONFIG_MAX_I2C_NUM];
|
||||
int count, i;
|
||||
|
||||
count = fdtdec_find_aliases_for_id(blob, "i2c",
|
||||
COMPAT_SAMSUNG_S3C2440_I2C, node_list,
|
||||
CONFIG_MAX_I2C_NUM);
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct s3c24x0_i2c_bus *bus;
|
||||
int node = node_list[i];
|
||||
|
||||
if (node <= 0)
|
||||
continue;
|
||||
bus = &i2c_bus[i];
|
||||
bus->regs = (struct s3c24x0_i2c *)
|
||||
fdtdec_get_addr(blob, node, "reg");
|
||||
bus->id = pinmux_decode_periph_id(blob, node);
|
||||
bus->node = node;
|
||||
bus->bus_num = i2c_busses++;
|
||||
exynos_pinmux_config(bus->id, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
|
||||
{
|
||||
if (bus_idx < i2c_busses)
|
||||
return &i2c_bus[bus_idx];
|
||||
|
||||
debug("Undefined bus: %d\n", bus_idx);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int i2c_get_bus_num_fdt(int node)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < i2c_busses; i++) {
|
||||
if (node == i2c_bus[i].node)
|
||||
return i;
|
||||
}
|
||||
|
||||
debug("%s: Can't find any matched I2C bus\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int i2c_reset_port_fdt(const void *blob, int node)
|
||||
{
|
||||
struct s3c24x0_i2c_bus *i2c;
|
||||
int bus;
|
||||
|
||||
bus = i2c_get_bus_num_fdt(node);
|
||||
if (bus < 0) {
|
||||
debug("could not get bus for node %d\n", node);
|
||||
return -1;
|
||||
}
|
||||
|
||||
i2c = get_bus(bus);
|
||||
if (!i2c) {
|
||||
debug("get_bus() failed for node node %d\n", node);
|
||||
return -1;
|
||||
}
|
||||
|
||||
i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
|
|
|||
|
|
@ -30,4 +30,11 @@ struct s3c24x0_i2c {
|
|||
u32 iicds;
|
||||
u32 iiclc;
|
||||
};
|
||||
|
||||
struct s3c24x0_i2c_bus {
|
||||
int node; /* device tree node */
|
||||
int bus_num; /* i2c bus number */
|
||||
struct s3c24x0_i2c *regs;
|
||||
int id;
|
||||
};
|
||||
#endif /* _S3C24X0_I2C_H */
|
||||
|
|
|
|||
|
|
@ -22,10 +22,14 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/max77686_pmic.h>
|
||||
#include <errno.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int pmic_init(unsigned char bus)
|
||||
{
|
||||
static const char name[] = "MAX77686_PMIC";
|
||||
|
|
@ -36,13 +40,40 @@ int pmic_init(unsigned char bus)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
puts("Board PMIC init\n");
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node, parent;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC);
|
||||
if (node < 0) {
|
||||
debug("PMIC: No node for PMIC Chip in device tree\n");
|
||||
debug("node = %d\n", node);
|
||||
return -1;
|
||||
}
|
||||
|
||||
parent = fdt_parent_offset(blob, node);
|
||||
if (parent < 0) {
|
||||
debug("%s: Cannot find node parent\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
p->bus = i2c_get_bus_num_fdt(parent);
|
||||
if (p->bus < 0) {
|
||||
debug("%s: Cannot find I2C bus\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9);
|
||||
#else
|
||||
p->bus = bus;
|
||||
p->hw.i2c.addr = MAX77686_I2C_ADDR;
|
||||
#endif
|
||||
|
||||
p->name = name;
|
||||
p->interface = PMIC_I2C;
|
||||
p->number_of_regs = PMIC_NUM_OF_REGS;
|
||||
p->hw.i2c.addr = MAX77686_I2C_ADDR;
|
||||
p->hw.i2c.tx_num = 1;
|
||||
p->bus = bus;
|
||||
|
||||
puts("Board PMIC init\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,27 +24,82 @@
|
|||
#include <malloc.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <i2s.h>
|
||||
#include <sound.h>
|
||||
#include "wm8994.h"
|
||||
#include <asm/arch/sound.h>
|
||||
#include "wm8994.h"
|
||||
|
||||
/* defines */
|
||||
#define SOUND_400_HZ 400
|
||||
#define SOUND_BITS_IN_BYTE 8
|
||||
|
||||
static struct i2stx_info g_i2stx_pri;
|
||||
static struct sound_codec_info g_codec_info;
|
||||
|
||||
/*
|
||||
* get_sound_fdt_values gets fdt values for i2s parameters
|
||||
* get_sound_i2s_values gets values for i2s parameters
|
||||
*
|
||||
* @param i2stx_info i2s transmitter transfer param structure
|
||||
* @param blob FDT blob
|
||||
* @param blob FDT blob if enabled else NULL
|
||||
*/
|
||||
static void get_sound_i2s_values(struct i2stx_info *i2s)
|
||||
static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
|
||||
{
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
int node;
|
||||
int error = 0;
|
||||
int base;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0,
|
||||
COMPAT_SAMSUNG_EXYNOS5_SOUND);
|
||||
if (node <= 0) {
|
||||
debug("EXYNOS_SOUND: No node for sound in device tree\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the pre-defined sound specific values from FDT.
|
||||
* All of these are expected to be correct otherwise
|
||||
* wrong register values in i2s setup parameters
|
||||
* may result in no sound play.
|
||||
*/
|
||||
base = fdtdec_get_addr(blob, node, "reg");
|
||||
if (base == FDT_ADDR_T_NONE) {
|
||||
debug("%s: Missing i2s base\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
i2s->base_address = base;
|
||||
|
||||
i2s->audio_pll_clk = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-epll-clock-frequency", -1);
|
||||
error |= i2s->audio_pll_clk;
|
||||
debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
|
||||
i2s->samplingrate = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-sampling-rate", -1);
|
||||
error |= i2s->samplingrate;
|
||||
debug("samplingrate = %d\n", i2s->samplingrate);
|
||||
i2s->bitspersample = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-bits-per-sample", -1);
|
||||
error |= i2s->bitspersample;
|
||||
debug("bitspersample = %d\n", i2s->bitspersample);
|
||||
i2s->channels = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-channels", -1);
|
||||
error |= i2s->channels;
|
||||
debug("channels = %d\n", i2s->channels);
|
||||
i2s->rfs = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-lr-clk-framesize", -1);
|
||||
error |= i2s->rfs;
|
||||
debug("rfs = %d\n", i2s->rfs);
|
||||
i2s->bfs = fdtdec_get_int(blob,
|
||||
node, "samsung,i2s-bit-clk-framesize", -1);
|
||||
error |= i2s->bfs;
|
||||
debug("bfs = %d\n", i2s->bfs);
|
||||
if (error == -1) {
|
||||
debug("fail to get sound i2s node properties\n");
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
i2s->base_address = samsung_get_base_i2s();
|
||||
i2s->audio_pll_clk = I2S_PLL_CLK;
|
||||
i2s->samplingrate = I2S_SAMPLING_RATE;
|
||||
|
|
@ -52,83 +107,76 @@ static void get_sound_i2s_values(struct i2stx_info *i2s)
|
|||
i2s->channels = I2S_CHANNELS;
|
||||
i2s->rfs = I2S_RFS;
|
||||
i2s->bfs = I2S_BFS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Gets fdt values for wm8994 config parameters
|
||||
*
|
||||
* @param pcodec_info codec information structure
|
||||
* @param blob FDT blob
|
||||
* @return int value, 0 for success
|
||||
*/
|
||||
static int get_sound_wm8994_values(struct sound_codec_info *pcodec_info)
|
||||
{
|
||||
int error = 0;
|
||||
|
||||
switch (AUDIO_COMPAT) {
|
||||
case AUDIO_COMPAT_SPI:
|
||||
debug("%s: Support not added for SPI interface\n", __func__);
|
||||
return -1;
|
||||
break;
|
||||
case AUDIO_COMPAT_I2C:
|
||||
pcodec_info->i2c_bus = AUDIO_I2C_BUS;
|
||||
pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
|
||||
debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
|
||||
break;
|
||||
default:
|
||||
debug("%s: Unknown compat id %d\n", __func__, AUDIO_COMPAT);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (error == -1) {
|
||||
debug("fail to get wm8994 codec node properties\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Gets fdt values for codec config parameters
|
||||
* Init codec
|
||||
*
|
||||
* @param pcodec_info codec information structure
|
||||
* @param blob FDT blob
|
||||
* @return int value, 0 for success
|
||||
* @param blob FDT blob
|
||||
* @param pi2s_tx i2s parameters required by codec
|
||||
* @return int value, 0 for success
|
||||
*/
|
||||
static int get_sound_codec_values(struct sound_codec_info *pcodec_info)
|
||||
static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
|
||||
{
|
||||
int error = 0;
|
||||
int ret;
|
||||
const char *codectype;
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
int node;
|
||||
|
||||
codectype = AUDIO_CODEC;
|
||||
|
||||
if (!strcmp(codectype, "wm8994")) {
|
||||
pcodec_info->codec_type = CODEC_WM_8994;
|
||||
error = get_sound_wm8994_values(pcodec_info);
|
||||
} else {
|
||||
error = -1;
|
||||
/* Get the node from FDT for sound */
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SOUND);
|
||||
if (node <= 0) {
|
||||
debug("EXYNOS_SOUND: No node for sound in device tree\n");
|
||||
debug("node = %d\n", node);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (error == -1) {
|
||||
debug("fail to get sound codec node properties\n");
|
||||
/*
|
||||
* Get the pre-defined sound codec specific values from FDT.
|
||||
* All of these are expected to be correct otherwise sound
|
||||
* can not be played
|
||||
*/
|
||||
codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
|
||||
debug("device = %s\n", codectype);
|
||||
#else
|
||||
codectype = AUDIO_CODEC;
|
||||
#endif
|
||||
if (!strcmp(codectype, "wm8994")) {
|
||||
/* Check the codec type and initialise the same */
|
||||
ret = wm8994_init(blob, WM8994_AIF2,
|
||||
pi2s_tx->samplingrate,
|
||||
(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
|
||||
pi2s_tx->bitspersample, pi2s_tx->channels);
|
||||
} else {
|
||||
debug("%s: Unknown code type %s\n", __func__,
|
||||
codectype);
|
||||
return -1;
|
||||
}
|
||||
if (ret) {
|
||||
debug("%s: Codec init failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sound_init(void)
|
||||
int sound_init(const void *blob)
|
||||
{
|
||||
int ret;
|
||||
struct i2stx_info *pi2s_tx = &g_i2stx_pri;
|
||||
struct sound_codec_info *pcodec_info = &g_codec_info;
|
||||
|
||||
/* Get the I2S Values */
|
||||
get_sound_i2s_values(pi2s_tx);
|
||||
|
||||
/* Get the codec Values */
|
||||
if (get_sound_codec_values(pcodec_info) < 0)
|
||||
if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
|
||||
debug(" FDT I2S values failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (codec_init(blob, pi2s_tx) < 0) {
|
||||
debug(" Codec init failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret = i2s_tx_init(pi2s_tx);
|
||||
if (ret) {
|
||||
|
|
@ -137,21 +185,6 @@ int sound_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Check the codec type and initialise the same */
|
||||
if (pcodec_info->codec_type == CODEC_WM_8994) {
|
||||
ret = wm8994_init(pcodec_info, WM8994_AIF2,
|
||||
pi2s_tx->samplingrate,
|
||||
(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
|
||||
pi2s_tx->bitspersample, pi2s_tx->channels);
|
||||
} else {
|
||||
debug("%s: Unknown code type %d\n", __func__,
|
||||
pcodec_info->codec_type);
|
||||
return -1;
|
||||
}
|
||||
if (ret) {
|
||||
debug("%s: Codec init failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,9 +26,11 @@
|
|||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <div64.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <i2s.h>
|
||||
#include <sound.h>
|
||||
#include <asm/arch/sound.h>
|
||||
#include "wm8994.h"
|
||||
#include "wm8994_registers.h"
|
||||
|
||||
|
|
@ -77,6 +79,7 @@ static int bclk_divs[] = {
|
|||
|
||||
static struct wm8994_priv g_wm8994_info;
|
||||
static unsigned char g_wm8994_i2c_dev_addr;
|
||||
static struct sound_codec_info g_codec_info;
|
||||
|
||||
/*
|
||||
* Initialise I2C for wm 8994
|
||||
|
|
@ -747,13 +750,80 @@ err:
|
|||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Gets fdt values for wm8994 config parameters
|
||||
*
|
||||
* @param pcodec_info codec information structure
|
||||
* @param blob FDT blob
|
||||
* @return int value, 0 for success
|
||||
*/
|
||||
static int get_codec_values(struct sound_codec_info *pcodec_info,
|
||||
const void *blob)
|
||||
{
|
||||
int error = 0;
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
enum fdt_compat_id compat;
|
||||
int node;
|
||||
int parent;
|
||||
|
||||
/* Get the node from FDT for codec */
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
|
||||
if (node <= 0) {
|
||||
debug("EXYNOS_SOUND: No node for codec in device tree\n");
|
||||
debug("node = %d\n", node);
|
||||
return -1;
|
||||
}
|
||||
|
||||
parent = fdt_parent_offset(blob, node);
|
||||
if (parent < 0) {
|
||||
debug("%s: Cannot find node parent\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
compat = fdtdec_lookup(blob, parent);
|
||||
switch (compat) {
|
||||
case COMPAT_SAMSUNG_S3C2440_I2C:
|
||||
pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
|
||||
error |= pcodec_info->i2c_bus;
|
||||
debug("i2c bus = %d\n", pcodec_info->i2c_bus);
|
||||
pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
|
||||
"reg", 0);
|
||||
error |= pcodec_info->i2c_dev_addr;
|
||||
debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
|
||||
break;
|
||||
default:
|
||||
debug("%s: Unknown compat id %d\n", __func__, compat);
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
pcodec_info->i2c_bus = AUDIO_I2C_BUS;
|
||||
pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
|
||||
debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
|
||||
#endif
|
||||
|
||||
pcodec_info->codec_type = CODEC_WM_8994;
|
||||
|
||||
if (error == -1) {
|
||||
debug("fail to get wm8994 codec node properties\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*wm8994 Device Initialisation */
|
||||
int wm8994_init(struct sound_codec_info *pcodec_info,
|
||||
enum en_audio_interface aif_id,
|
||||
int wm8994_init(const void *blob, enum en_audio_interface aif_id,
|
||||
int sampling_rate, int mclk_freq,
|
||||
int bits_per_sample, unsigned int channels)
|
||||
{
|
||||
int ret = 0;
|
||||
struct sound_codec_info *pcodec_info = &g_codec_info;
|
||||
|
||||
/* Get the codec Values */
|
||||
if (get_codec_values(pcodec_info, blob) < 0) {
|
||||
debug("FDT Codec values failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* shift the device address by 1 for 7 bit addressing */
|
||||
g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
|
||||
|
|
|
|||
|
|
@ -69,8 +69,7 @@ enum wm8994_type {
|
|||
/*
|
||||
* intialise wm8994 sound codec device for the given configuration
|
||||
*
|
||||
* @param pcodec_info pointer value of the sound codec info structure
|
||||
* parsed from device tree
|
||||
* @param blob FDT node for codec values
|
||||
* @param aif_id enum value of codec interface port in which
|
||||
* soc i2s is connected
|
||||
* @param sampling_rate Sampling rate ranges between from 8khz to 96khz
|
||||
|
|
@ -80,8 +79,7 @@ enum wm8994_type {
|
|||
*
|
||||
* @returns -1 for error and 0 Success.
|
||||
*/
|
||||
int wm8994_init(struct sound_codec_info *pcodec_info,
|
||||
enum en_audio_interface aif_id,
|
||||
int wm8994_init(const void *blob, enum en_audio_interface aif_id,
|
||||
int sampling_rate, int mclk_freq,
|
||||
int bits_per_sample, unsigned int channels);
|
||||
#endif /*__WM8994_H__ */
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <spi.h>
|
||||
#include <fdtdec.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
|
@ -28,16 +29,20 @@
|
|||
#include <asm/arch-exynos/spi.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Information about each SPI controller */
|
||||
struct spi_bus {
|
||||
enum periph_id periph_id;
|
||||
s32 frequency; /* Default clock frequency, -1 for none */
|
||||
struct exynos_spi *regs;
|
||||
int inited; /* 1 if this bus is ready for use */
|
||||
int node;
|
||||
};
|
||||
|
||||
/* A list of spi buses that we know about */
|
||||
static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
|
||||
static unsigned int bus_count;
|
||||
|
||||
struct exynos_spi_slave {
|
||||
struct spi_slave slave;
|
||||
|
|
@ -50,7 +55,7 @@ struct exynos_spi_slave {
|
|||
|
||||
static struct spi_bus *spi_get_bus(unsigned dev_index)
|
||||
{
|
||||
if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS)
|
||||
if (dev_index < bus_count)
|
||||
return &spi_bus[dev_index];
|
||||
debug("%s: invalid bus %d", __func__, dev_index);
|
||||
|
||||
|
|
@ -347,21 +352,100 @@ static inline struct exynos_spi *get_spi_base(int dev_index)
|
|||
(dev_index - 3);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the SPI config from the device tree node.
|
||||
*
|
||||
* @param blob FDT blob to read from
|
||||
* @param node Node offset to read from
|
||||
* @param bus SPI bus structure to fill with information
|
||||
* @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
|
||||
*/
|
||||
static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
|
||||
{
|
||||
bus->node = node;
|
||||
bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
|
||||
bus->periph_id = pinmux_decode_periph_id(blob, node);
|
||||
|
||||
if (bus->periph_id == PERIPH_ID_NONE) {
|
||||
debug("%s: Invalid peripheral ID %d\n", __func__,
|
||||
bus->periph_id);
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
|
||||
/* Use 500KHz as a suitable default */
|
||||
bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
500000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Process a list of nodes, adding them to our list of SPI ports.
|
||||
*
|
||||
* @param blob fdt blob
|
||||
* @param node_list list of nodes to process (any <=0 are ignored)
|
||||
* @param count number of nodes to process
|
||||
* @param is_dvc 1 if these are DVC ports, 0 if standard I2C
|
||||
* @return 0 if ok, -1 on error
|
||||
*/
|
||||
static int process_nodes(const void *blob, int node_list[], int count)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* build the i2c_controllers[] for each controller */
|
||||
for (i = 0; i < count; i++) {
|
||||
int node = node_list[i];
|
||||
struct spi_bus *bus;
|
||||
|
||||
if (node <= 0)
|
||||
continue;
|
||||
|
||||
bus = &spi_bus[i];
|
||||
if (spi_get_config(blob, node, bus)) {
|
||||
printf("exynos spi_init: failed to decode bus %d\n",
|
||||
i);
|
||||
return -1;
|
||||
}
|
||||
|
||||
debug("spi: controller bus %d at %p, periph_id %d\n",
|
||||
i, bus->regs, bus->periph_id);
|
||||
bus->inited = 1;
|
||||
bus_count++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sadly there is no error return from this function */
|
||||
void spi_init(void)
|
||||
{
|
||||
int i;
|
||||
int count;
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
|
||||
const void *blob = gd->fdt_blob;
|
||||
|
||||
count = fdtdec_find_aliases_for_id(blob, "spi",
|
||||
COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
|
||||
EXYNOS5_SPI_NUM_CONTROLLERS);
|
||||
if (process_nodes(blob, node_list, count))
|
||||
return;
|
||||
|
||||
#else
|
||||
struct spi_bus *bus;
|
||||
|
||||
for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) {
|
||||
bus = &spi_bus[i];
|
||||
bus->regs = get_spi_base(i);
|
||||
bus->periph_id = PERIPH_ID_SPI0 + i;
|
||||
for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
|
||||
bus = &spi_bus[count];
|
||||
bus->regs = get_spi_base(count);
|
||||
bus->periph_id = PERIPH_ID_SPI0 + count;
|
||||
|
||||
/* Although Exynos5 supports upto 50Mhz speed,
|
||||
* we are setting it to 10Mhz for safe side
|
||||
*/
|
||||
bus->frequency = 10000000;
|
||||
bus->inited = 1;
|
||||
bus->node = 0;
|
||||
bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,13 +21,71 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <libfdt.h>
|
||||
#include <malloc.h>
|
||||
#include <usb.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/ehci.h>
|
||||
#include <asm/arch/system.h>
|
||||
#include <asm/arch/power.h>
|
||||
#include <asm-generic/errno.h>
|
||||
#include <linux/compat.h>
|
||||
#include "ehci.h"
|
||||
|
||||
/* Declare global data pointer */
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/**
|
||||
* Contains pointers to register base addresses
|
||||
* for the usb controller.
|
||||
*/
|
||||
struct exynos_ehci {
|
||||
struct exynos_usb_phy *usb;
|
||||
unsigned int *hcd;
|
||||
};
|
||||
|
||||
static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
|
||||
{
|
||||
unsigned int node;
|
||||
int depth;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
|
||||
if (node <= 0) {
|
||||
debug("EHCI: Can't get device node for ehci\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the base address for EHCI controller from the device node
|
||||
*/
|
||||
exynos->hcd = (unsigned int *)fdtdec_get_addr(blob, node, "reg");
|
||||
if (exynos->hcd == NULL) {
|
||||
debug("Can't get the EHCI register address\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
depth = 0;
|
||||
node = fdtdec_next_compatible_subnode(blob, node,
|
||||
COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
|
||||
if (node <= 0) {
|
||||
debug("EHCI: Can't get device node for usb-phy controller\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the base address for usbphy from the device node
|
||||
*/
|
||||
exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
|
||||
"reg");
|
||||
if (exynos->usb == NULL) {
|
||||
debug("Can't get the usbphy register address\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Setup the EHCI host controller. */
|
||||
static void setup_usb_phy(struct exynos_usb_phy *usb)
|
||||
{
|
||||
|
|
@ -86,12 +144,20 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
|
|||
*/
|
||||
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||||
{
|
||||
struct exynos_usb_phy *usb;
|
||||
struct exynos_ehci *exynos = NULL;
|
||||
|
||||
usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
|
||||
setup_usb_phy(usb);
|
||||
exynos = (struct exynos_ehci *)
|
||||
kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
|
||||
if (!exynos) {
|
||||
debug("failed to allocate exynos ehci context\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
*hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
|
||||
exynos_usb_parse_dt(gd->fdt_blob, exynos);
|
||||
|
||||
setup_usb_phy(exynos->usb);
|
||||
|
||||
*hccr = (struct ehci_hccr *)(exynos->hcd);
|
||||
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
|
||||
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
|
||||
|
|
@ -99,6 +165,8 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
|||
(uint32_t)*hccr, (uint32_t)*hcor,
|
||||
(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
|
||||
kfree(exynos);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -108,10 +176,20 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
|||
*/
|
||||
int ehci_hcd_stop(int index)
|
||||
{
|
||||
struct exynos_usb_phy *usb;
|
||||
struct exynos_ehci *exynos = NULL;
|
||||
|
||||
usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
|
||||
reset_usb_phy(usb);
|
||||
exynos = (struct exynos_ehci *)
|
||||
kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
|
||||
if (!exynos) {
|
||||
debug("failed to allocate exynos ehci context\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
exynos_usb_parse_dt(gd->fdt_blob, exynos);
|
||||
|
||||
reset_usb_phy(exynos->usb);
|
||||
|
||||
kfree(exynos);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -857,7 +857,6 @@ unsigned int exynos_init_dp(void)
|
|||
{
|
||||
unsigned int ret;
|
||||
struct edp_device_info *edp_info;
|
||||
struct edp_disp_info disp_info;
|
||||
|
||||
edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
|
||||
if (!edp_info) {
|
||||
|
|
@ -870,7 +869,6 @@ unsigned int exynos_init_dp(void)
|
|||
debug("failed to get edp_info data.\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
disp_info = edp_info->disp_info;
|
||||
|
||||
exynos_dp_disp_info(&edp_info->disp_info);
|
||||
|
||||
|
|
|
|||
|
|
@ -63,8 +63,12 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
|
|||
static void exynos_lcd_init(vidinfo_t *vid)
|
||||
{
|
||||
exynos_fimd_lcd_init(vid);
|
||||
|
||||
/* Enable flushing after LCD writes if requested */
|
||||
lcd_set_flush_dcache(1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMP
|
||||
static void draw_logo(void)
|
||||
{
|
||||
int x, y;
|
||||
|
|
@ -87,6 +91,7 @@ static void draw_logo(void)
|
|||
addr = panel_info.logo_addr;
|
||||
bmp_display(addr, x, y);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void lcd_panel_on(vidinfo_t *vid)
|
||||
{
|
||||
|
|
@ -145,7 +150,9 @@ void lcd_enable(void)
|
|||
if (panel_info.logo_on) {
|
||||
memset(lcd_base, 0, panel_width * panel_height *
|
||||
(NBITS(panel_info.vl_bpix) >> 3));
|
||||
#ifdef CONFIG_CMD_BMP
|
||||
draw_logo();
|
||||
#endif
|
||||
}
|
||||
|
||||
lcd_panel_on(&panel_info);
|
||||
|
|
|
|||
|
|
@ -88,14 +88,18 @@ static void exynos_fimd_set_par(unsigned int win_id)
|
|||
/* DATAPATH is DMA */
|
||||
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
|
||||
|
||||
/* bpp is 32 */
|
||||
cfg |= EXYNOS_WINCON_WSWP_ENABLE;
|
||||
if (pvid->logo_on) /* To get proprietary LOGO */
|
||||
cfg |= EXYNOS_WINCON_WSWP_ENABLE;
|
||||
else /* To get output console on LCD */
|
||||
cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
|
||||
|
||||
/* dma burst is 16 */
|
||||
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
|
||||
|
||||
/* pixel format is unpacked RGB888 */
|
||||
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
|
||||
if (pvid->logo_on) /* To get proprietary LOGO */
|
||||
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
|
||||
else /* To get output console on LCD */
|
||||
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
|
||||
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
|
|
|
|||
|
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* Configuration settings for the SAMSUNG EXYNOS5250 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* S5P Family */
|
||||
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
|
||||
#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Enable fdt support for Exynos5250 */
|
||||
#define CONFIG_ARCH_DEVICE_TREE exynos5250
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* Keep L2 Cache Disabled */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x43E00000
|
||||
|
||||
/* input clock of PLL: SMDK5250 has 24MHz input clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
|
||||
#define MACH_TYPE_SMDK5250 3774
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
|
||||
|
||||
/* Power Down Modes */
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
#define S5P_CHECK_DIDLE 0xBAD00000
|
||||
#define S5P_CHECK_LPA 0xABAD0000
|
||||
|
||||
/* Offset for inform registers */
|
||||
#define INFORM0_OFFSET 0x800
|
||||
#define INFORM1_OFFSET 0x804
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL3 /* use SERIAL 3 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
|
||||
|
||||
/* Console configuration */
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define EXYNOS_DEVICE_SETTINGS \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial,lcd\0" \
|
||||
"stderr=serial,lcd\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXYNOS_DEVICE_SETTINGS
|
||||
|
||||
#define TZPC_BASE_OFFSET 0x10000
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_SDHCI
|
||||
#define CONFIG_S5P_SDHCI
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* PWM */
|
||||
#define CONFIG_PWM
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Command definition*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_EXYNOS
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/* MMC SPL */
|
||||
#define CONFIG_SPL
|
||||
#define COPY_BL2_FNPTR_ADDR 0x02020030
|
||||
|
||||
/* specific .lds file */
|
||||
#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x02023400
|
||||
#define CONFIG_SPL_MAX_SIZE (14 * 1024)
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT "SMDK5250 # "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_RD_LVL
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 8
|
||||
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
|
||||
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
|
||||
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#define CONFIG_IDENT_STRING " for SMDK5250"
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_SECURE_BL1_ONLY
|
||||
|
||||
/* Secure FW size configuration */
|
||||
#ifdef CONFIG_SECURE_BL1_ONLY
|
||||
#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
|
||||
#else
|
||||
#define CONFIG_SEC_FW_SIZE 0
|
||||
#endif
|
||||
|
||||
/* Configuration of BL1, BL2, ENV Blocks on mmc */
|
||||
#define CONFIG_RES_BLOCK_SIZE (512)
|
||||
#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
|
||||
#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
|
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
|
||||
|
||||
#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
|
||||
#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
|
||||
|
||||
/* U-boot copy size from boot Media to DRAM.*/
|
||||
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
|
||||
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
|
||||
|
||||
#define OM_STAT (0x1f << 1)
|
||||
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
|
||||
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_IRAM_STACK 0x02050000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_PMIC
|
||||
#define CONFIG_PMIC_I2C
|
||||
#define CONFIG_PMIC_MAX77686
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
#define CONFIG_EXYNOS_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SPI_BUS 1
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_MAX77686
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
#define CONFIG_EXYNOS_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SPI_BUS 1
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
|
||||
/* Ethernet Controllor Driver */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE 0x5000000
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
#define CONFIG_ENV_SROM_BANK 1
|
||||
#endif /*CONFIG_CMD_NET*/
|
||||
|
||||
/* Enable PXE Support */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PXE
|
||||
#define CONFIG_MENU
|
||||
#endif
|
||||
|
||||
/* Sound */
|
||||
#define CONFIG_CMD_SOUND
|
||||
#ifdef CONFIG_CMD_SOUND
|
||||
#define CONFIG_SOUND
|
||||
#define CONFIG_I2S
|
||||
#define CONFIG_SOUND_WM8994
|
||||
#endif
|
||||
|
||||
/* Enable devicetree support */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/* SHA hashing */
|
||||
#define CONFIG_CMD_HASH
|
||||
#define CONFIG_HASH_VERIFY
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
|
||||
/* Display */
|
||||
#define CONFIG_LCD
|
||||
#ifdef CONFIG_LCD
|
||||
#define CONFIG_EXYNOS_FB
|
||||
#define CONFIG_EXYNOS_DP
|
||||
#define LCD_XRES 2560
|
||||
#define LCD_YRES 1600
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
|
||||
* Configuration settings for the SAMSUNG SMDK5250 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -22,274 +22,12 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#ifndef __CONFIG_SMDK_H
|
||||
#define __CONFIG_SMDK_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* S5P Family */
|
||||
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
|
||||
#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
|
||||
#include <configs/exynos5250-dt.h>
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#undef CONFIG_DEFAULT_DEVICE_TREE
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Keep L2 Cache Disabled */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x43E00000
|
||||
|
||||
/* input clock of PLL: SMDK5250 has 24MHz input clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
|
||||
#define MACH_TYPE_SMDK5250 3774
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
|
||||
|
||||
/* Power Down Modes */
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
#define S5P_CHECK_DIDLE 0xBAD00000
|
||||
#define S5P_CHECK_LPA 0xABAD0000
|
||||
|
||||
/* Offset for inform registers */
|
||||
#define INFORM0_OFFSET 0x800
|
||||
#define INFORM1_OFFSET 0x804
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL3 /* use SERIAL 3 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
|
||||
|
||||
#define TZPC_BASE_OFFSET 0x10000
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_SDHCI
|
||||
#define CONFIG_S5P_SDHCI
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* PWM */
|
||||
#define CONFIG_PWM
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Command definition*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_EXYNOS
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/* MMC SPL */
|
||||
#define CONFIG_SPL
|
||||
#define COPY_BL2_FNPTR_ADDR 0x02020030
|
||||
|
||||
/* specific .lds file */
|
||||
#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x02023400
|
||||
#define CONFIG_SPL_MAX_SIZE (14 * 1024)
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT "SMDK5250 # "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_RD_LVL
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 8
|
||||
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
|
||||
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
|
||||
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#define CONFIG_IDENT_STRING " for SMDK5250"
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_SECURE_BL1_ONLY
|
||||
|
||||
/* Secure FW size configuration */
|
||||
#ifdef CONFIG_SECURE_BL1_ONLY
|
||||
#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
|
||||
#else
|
||||
#define CONFIG_SEC_FW_SIZE 0
|
||||
#endif
|
||||
|
||||
/* Configuration of BL1, BL2, ENV Blocks on mmc */
|
||||
#define CONFIG_RES_BLOCK_SIZE (512)
|
||||
#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
|
||||
#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
|
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
|
||||
|
||||
#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
|
||||
#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
|
||||
|
||||
/* U-boot copy size from boot Media to DRAM.*/
|
||||
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
|
||||
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
|
||||
|
||||
#define OM_STAT (0x1f << 1)
|
||||
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
|
||||
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_IRAM_STACK 0x02050000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_PMIC
|
||||
#define CONFIG_PMIC_I2C
|
||||
#define CONFIG_PMIC_MAX77686
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
#define CONFIG_EXYNOS_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SPI_BUS 1
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_MAX77686
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
#define CONFIG_EXYNOS_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SPI_BUS 1
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 50000000
|
||||
#endif
|
||||
|
||||
/* Ethernet Controllor Driver */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE 0x5000000
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
#define CONFIG_ENV_SROM_BANK 1
|
||||
#endif /*CONFIG_CMD_NET*/
|
||||
|
||||
/* Enable PXE Support */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PXE
|
||||
#define CONFIG_MENU
|
||||
#endif
|
||||
|
||||
/* Sound */
|
||||
#define CONFIG_CMD_SOUND
|
||||
#ifdef CONFIG_CMD_SOUND
|
||||
#define CONFIG_SOUND
|
||||
#define CONFIG_I2S
|
||||
#define CONFIG_SOUND_WM8994
|
||||
#endif
|
||||
|
||||
/* Enable devicetree support */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/* SHA hashing */
|
||||
#define CONFIG_CMD_HASH
|
||||
#define CONFIG_HASH_VERIFY
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
#endif /* __CONFIG_SMDK_H */
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@
|
|||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_GPT
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
/* FAT */
|
||||
#define CONFIG_CMD_FAT
|
||||
|
|
@ -144,9 +145,8 @@
|
|||
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
|
||||
|
||||
#define CONFIG_DFU_ALT \
|
||||
"dfu_alt_info=" \
|
||||
"u-boot mmc 80 400;" \
|
||||
"uImage fat 0 2\0" \
|
||||
"uImage ext4 0 2\0" \
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
|
@ -165,20 +165,20 @@
|
|||
"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
|
||||
"lpj=lpj=3981312\0" \
|
||||
"nfsboot=" \
|
||||
"set bootargs root=/dev/nfs rw " \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${nfsroot},nolock,tcp " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
|
||||
"; run bootk\0" \
|
||||
"ramfsboot=" \
|
||||
"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
|
||||
"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
|
||||
"${console} ${meminfo} " \
|
||||
"initrd=0x43000000,8M ramdisk=8192\0" \
|
||||
"mmcboot=" \
|
||||
"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
|
||||
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
|
||||
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
|
||||
"run loaduimage; bootm 0x40007FC0\0" \
|
||||
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
|
||||
"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
|
||||
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
|
||||
"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
|
||||
"verify=n\0" \
|
||||
|
|
@ -187,13 +187,31 @@
|
|||
"meminfo=crashkernel=32M@0x50000000\0" \
|
||||
"nfsroot=/nfsroot/arm\0" \
|
||||
"bootblock=" CONFIG_BOOTBLOCK "\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
|
||||
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcbootpart=2\0" \
|
||||
"mmcrootpart=3\0" \
|
||||
"mmcrootpart=5\0" \
|
||||
"opts=always_resume=1\0" \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
CONFIG_DFU_ALT \
|
||||
"dfu_alt_info=" CONFIG_DFU_ALT \
|
||||
"spladdr=0x40000100\0" \
|
||||
"splsize=0x200\0" \
|
||||
"splfile=falcon.bin\0" \
|
||||
"spl_export=" \
|
||||
"setexpr spl_imgsize ${splsize} + 8 ;" \
|
||||
"setexpr spl_imgaddr ${spladdr} - 8 ;" \
|
||||
"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
|
||||
"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
|
||||
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
|
||||
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
|
||||
"spl export atags 0x40007FC0;" \
|
||||
"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
|
||||
"mw.l ${spl_addr_tmp} ${splsize};" \
|
||||
"ext4write mmc ${mmcdev}:${mmcbootpart}" \
|
||||
" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
|
||||
"setenv spl_imgsize;" \
|
||||
"setenv spl_imgaddr;" \
|
||||
"setenv spl_addr_tmp;\0"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
|
@ -234,6 +252,14 @@
|
|||
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
|
||||
/* EXT4 */
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
/* Falcon mode definitions */
|
||||
#define CONFIG_CMD_SPL
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
|
||||
|
||||
/* GPT */
|
||||
#define CONFIG_EFI_PARTITION
|
||||
|
|
@ -242,7 +268,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
|
||||
#define CONFIG_SOFT_I2C
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
|
|
|
|||
|
|
@ -70,6 +70,15 @@ enum fdt_compat_id {
|
|||
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
|
||||
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
|
||||
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
|
||||
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
|
||||
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
|
||||
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
|
||||
COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */
|
||||
COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */
|
||||
COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */
|
||||
COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
|
||||
COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
|
||||
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
|
||||
|
||||
COMPAT_COUNT,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -262,4 +262,30 @@ extern int get_multi_scl_pin(void);
|
|||
extern int get_multi_sda_pin(void);
|
||||
extern int multi_i2c_init(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Get FDT values for i2c bus.
|
||||
*
|
||||
* @param blob Device tree blbo
|
||||
* @return the number of I2C bus
|
||||
*/
|
||||
void board_i2c_init(const void *blob);
|
||||
|
||||
/**
|
||||
* Find the I2C bus number by given a FDT I2C node.
|
||||
*
|
||||
* @param blob Device tree blbo
|
||||
* @param node FDT I2C node to find
|
||||
* @return the number of I2C bus (zero based), or -1 on error
|
||||
*/
|
||||
int i2c_get_bus_num_fdt(int node);
|
||||
|
||||
/**
|
||||
* Reset the I2C bus represented by the given a FDT I2C node.
|
||||
*
|
||||
* @param blob Device tree blbo
|
||||
* @param node FDT I2C node to find
|
||||
* @return 0 if port was reset, -1 if not found
|
||||
*/
|
||||
int i2c_reset_port_fdt(const void *blob, int node);
|
||||
#endif /* _I2C_H_ */
|
||||
|
|
|
|||
|
|
@ -46,10 +46,10 @@ struct sound_codec_info {
|
|||
|
||||
/*
|
||||
* Initialises audio sub system
|
||||
*
|
||||
* @param blob Pointer of device tree node or NULL if none.
|
||||
* @return int value 0 for success, -1 for error
|
||||
*/
|
||||
int sound_init(void);
|
||||
int sound_init(const void *blob);
|
||||
|
||||
/*
|
||||
* plays the pcm data buffer in pcm_data.h through i2s1 to make the
|
||||
|
|
|
|||
|
|
@ -45,6 +45,15 @@ static const char * const compat_names[COMPAT_COUNT] = {
|
|||
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
|
||||
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
|
||||
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
|
||||
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
|
||||
COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
|
||||
COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
|
||||
COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),
|
||||
COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"),
|
||||
COMPAT(SAMSUNG_EXYNOS_SPI, "samsung,exynos-spi"),
|
||||
COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
|
||||
COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
|
||||
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
|
||||
};
|
||||
|
||||
const char *fdtdec_get_compatible(enum fdt_compat_id id)
|
||||
|
|
|
|||
Loading…
Reference in New Issue