mpc5200: Add a3m071 board support
This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
083f2e08d2
commit
13b4f63949
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@ -388,6 +388,8 @@ Ricardo Ribalda <ricardo.ribalda@uam.es>
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Stefan Roese <sr@denx.de>
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a3m071 MPC5200
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P3M7448 MPC7448
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uc100 MPC857
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@ -0,0 +1,36 @@
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,80 @@
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------------------------------------------------------------------------
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A3M071 board support
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------------------------------------------------------------------------
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SPL NOR flash support:
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----------------------
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To boot fast into the OS (Linux), this board port integrates the SPL
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framework. This means, that a special, stripped-down version of
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U-Boot runs in the beginning. In the case of the A3M071 board, this
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SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
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boot the OS (Linux) or a "real", full-blown U-Boot. This detection
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on whether to boot Linux or U-Boot is done by using the "boot_os"
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environment variable. If "boot_os" is set to "yes", Linux will be
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loaded and booted from the SPL U-Boot version. Otherwise, the
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full-blown U-Boot version will be loaded and run.
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Enabling Linux booting:
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-----------------------
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From U-Boot:
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=> setenv boot_os yes
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=> saveenv
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From Linux:
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$ fw_setenv boot_os yes
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Enabling U-Boot booting:
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------------------------
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From U-Boot:
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=> setenv boot_os no
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=> saveenv
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From Linux:
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$ fw_setenv boot_os no
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Preparing Linux image(s) for booting from SPL U-Boot:
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-----------------------------------------------------
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To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
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prepard/patched first. U-Boot usually inserts some dynamic values into
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the DT binary (blob), e.g. autodetected memory size, MAC addresses,
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clocks speeds etc. To generate this patched DT blob, you can use
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the following command:
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1. Load fdt blob to SDRAM:
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=> tftp 1800000 a3m071/a3m071.dtb
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2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
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=> run mtdargs addip2 addtty
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3. Use "fdt" commands to patch the DT blob:
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=> fdt addr 1800000
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=> fdt boardsetup
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=> fdt chosen
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4. Display patched DT blob (optional):
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=> fdt print
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5. Save fdt to NOR flash:
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=> erase fc060000 fc07ffff
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=> cp.b 1800000 fc060000 10000
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All this can be integrated into an environment command:
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=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \
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fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \
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cp.b 1800000 fc060000 10000'
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=> saveenv
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After this, only "run upd_fdt" needs to get called to load, patch
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and save the DT blob into NOR flash.
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Additionally, the Linux kernel image has to be saved uncompressed in
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its uImage file (and not gzip compressed). This can be done with this
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command:
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$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
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-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
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------------------------------------------------------------------------
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Stefan Roese, 2012-08-23
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@ -0,0 +1,335 @@
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/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2006
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* MicroSys GmbH
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*
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* Copyright 2012 Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <miiphy.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "mt46v16m16-75.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_SYS_RAMBOOT) && \
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(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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long control = SDRAM_CONTROL | hi_addr_bit;
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/* unlock mode register */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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#ifdef SDRAM_DDR
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/* set mode register: extended mode */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
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/* set mode register: reset DLL */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
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#endif
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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/* auto refresh */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
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/* set mode register */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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/* normal operation */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#if !defined(CONFIG_SYS_RAMBOOT) && \
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(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
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/* setup config registers */
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out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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#ifdef SDRAM_DDR
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/* set tap delay */
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out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
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0x13 + __builtin_ffs(dramsize >> 20) - 1);
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} else {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
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out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
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return dramsize + dramsize2;
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}
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static void get_revisions(int *failsavelevel, int *digiboardversion,
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int *fpgaversion)
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{
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struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
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u8 val;
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/*
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* Figure out failsavelevel
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* see ticket dsvk#59
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*/
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*failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
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/* read digitalboard-version from TMR[2..4] */
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val = 0;
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val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
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val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
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val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
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*digiboardversion = val;
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if (*digiboardversion == 0) {
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*failsavelevel = 1; /* digiboard-version ok */
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/* read fpga-version from TMR[5..7] */
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val = 0;
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val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
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val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
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val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
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*fpgaversion = val;
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if (*fpgaversion == 1)
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*failsavelevel = 2; /* fpga-version ok */
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}
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}
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/*
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* This function is called from the SPL U-Boot version for
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* early init stuff, that needs to be done for OS (e.g. Linux)
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* booting. Doing it later in the real U-Boot would not work
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* in case that the SPL U-Boot boots Linux directly.
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*/
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void spl_board_init(void)
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{
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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int digiboardversion;
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int failsavelevel;
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int fpgaversion;
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u32 val;
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get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
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val = in_be32(&mm->ipbi_ws_ctrl);
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/* first clear bits 19..21 (CS3...5) */
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val &= ~((1 << 19) | (1 << 20) | (1 << 21));
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if (failsavelevel == 2) {
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/* FPGA ok */
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val |= (1 << 19) | (1 << 21);
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}
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if (failsavelevel >= 1) {
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/* at least digiboard-version ok */
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val |= (1 << 20);
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}
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/* And write new value back to register */
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out_be32(&mm->ipbi_ws_ctrl, val);
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/*
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* No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
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* as all 3 config versions (failsave level) have the same setup.
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*/
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/*
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* Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
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* ticket #60
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*
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* MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
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* set bit 0(msb) to 1
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*/
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
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/* setup GPIOs for status-leds if needed - see ticket #57 */
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if (failsavelevel > 0) {
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/* digiboard-version is OK */
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/* LED is LOW ACTIVE - so deactivate by set output to 1 */
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gpio->simple_dvo |= 1 << (31 - 12);
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gpio->simple_dvo |= 1 << (31 - 13);
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/* set GPIO direction to output */
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gpio->simple_ddr |= 1 << (31 - 12);
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gpio->simple_ddr |= 1 << (31 - 13);
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/* open drain config is set to "normal output" at reset */
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/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
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/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
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/* enable as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 12);
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gpio->simple_gpioe |= 1 << (31 - 13);
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}
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/* setup fpga irq - see ticket #65 */
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if (failsavelevel > 1) {
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/*
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* The main irq initialisation is done in interrupts.c
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* mpc5xxx_init_irq
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*/
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struct mpc5xxx_intr *intr =
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(struct mpc5xxx_intr *)(MPC5XXX_ICTL);
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setbits_be32(&intr->ctrl, 0x08C01801);
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/*
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* The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
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* already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
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*/
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}
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}
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int checkboard(void)
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{
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int digiboardversion;
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int failsavelevel;
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int fpgaversion;
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get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
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puts("Board: A3M071\n");
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printf("Rev: failsave level %u\n", failsavelevel);
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printf(" digiboard IO version %u\n", digiboardversion);
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if (failsavelevel > 0) /* only if fpga-version red */
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printf(" fpga IO version %u\n", fpgaversion);
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return 0;
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}
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/* miscellaneous platform dependent initialisations */
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int misc_init_r(void)
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{
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/* adjust flash start and offset to detected values */
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gd->bd->bi_flashstart = flash_info[0].start[0];
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gd->bd->bi_flashoffset = 0;
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/* adjust mapping */
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out_be32((void *)MPC5XXX_BOOTCS_START,
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START_REG(gd->bd->bi_flashstart));
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out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
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out_be32((void *)MPC5XXX_BOOTCS_STOP,
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STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
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out_be32((void *)MPC5XXX_CS0_STOP,
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STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t * bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* A3M071 specific implementation of spl_start_uboot()
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*
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* RETURN
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* 0 if booting into OS is selected (default)
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* 1 if booting into U-Boot is selected
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*/
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int spl_start_uboot(void)
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{
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char s[8];
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|
||||
env_init();
|
||||
getenv_f("boot_os", s, sizeof(s));
|
||||
if ((s != NULL) && (strcmp(s, "yes") == 0))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define SDRAM_DDR /* is DDR */
|
||||
|
||||
#if defined(CONFIG_MPC5200)
|
||||
/* Settings for XLB = 132 MHz */
|
||||
#define SDRAM_MODE 0x018D0000
|
||||
#define SDRAM_EMODE 0x40090000
|
||||
#define SDRAM_CONTROL 0x704f0f00
|
||||
#define SDRAM_CONFIG1 0x73722930
|
||||
#define SDRAM_CONFIG2 0x47770000
|
||||
#define SDRAM_TAPDELAY 0x10000000
|
||||
|
||||
#else
|
||||
#error CONFIG_MPC5200 not defined
|
||||
#endif
|
||||
|
|
@ -473,6 +473,7 @@ mpc5121ads powerpc mpc512x mpc5121ads freesca
|
|||
mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
|
||||
cmi_mpc5xx powerpc mpc5xx cmi
|
||||
PATI powerpc mpc5xx pati mpl
|
||||
a3m071 powerpc mpc5xxx a3m071
|
||||
a4m072 powerpc mpc5xxx a4m072
|
||||
BC3450 powerpc mpc5xxx bc3450
|
||||
canmb powerpc mpc5xxx
|
||||
|
|
|
|||
|
|
@ -0,0 +1,380 @@
|
|||
/*
|
||||
* Copyright 2012 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5200
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_A3M071 /* ... on A3M071 board */
|
||||
#define CONFIG_MPC5200_DDR /* ... use DDR RAM */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
|
||||
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
||||
/* define for 66MHz speed - undef for 33MHz PCI clock speed */
|
||||
#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
#define OF_FLAT_TREE_MAX_SIZE 8192
|
||||
|
||||
#define OF_CPU "PowerPC,5200@0"
|
||||
#define OF_SOC "soc5200@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
|
||||
/*
|
||||
* NOR flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfc000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x01000000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT 5
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xf0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use SRAM until RAM will be available */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPIO-config depends on failsave-level
|
||||
* failsave 0 means just MPX-config, no digiboard, no fpga
|
||||
* 1 means digiboard ok
|
||||
* 2 means fpga ok
|
||||
*/
|
||||
|
||||
/* for failsave-level 0 - full failsave */
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
|
||||
/* for failsave-level 1 - only digiboard ok */
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
|
||||
/* for failsave-level 2 - all ok */
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
|
||||
|
||||
/*
|
||||
* Configuration matrix
|
||||
* MSB LSB
|
||||
* failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave )
|
||||
* failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok )
|
||||
* failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok )
|
||||
* || ||| || | ||| | | | |
|
||||
* || ||| || | ||| | | | | bit rev name
|
||||
* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
|
||||
* +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
|
||||
* ||| || | ||| | | | | 2 29 ALTs
|
||||
* +++-++--+---+++-+---+---+---+- 3 28 ALTs
|
||||
* ++-++--+---+++-+---+---+---+- 4 27 CS7
|
||||
* +-++--+---+++-+---+---+---+- 5 26 CS6
|
||||
* || | ||| | | | | 6 25 ATA
|
||||
* ++--+---+++-+---+---+---+- 7 24 ATA
|
||||
* +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
|
||||
* | ||| | | | | 9 22 IRDA
|
||||
* | ||| | | | | 10 21 IRDA
|
||||
* +---+++-+---+---+---+- 11 20 IRDA
|
||||
* ||| | | | | 12 19 Ether
|
||||
* ||| | | | | 13 18 Ether
|
||||
* ||| | | | | 14 17 Ether
|
||||
* +++-+---+---+---+- 15 16 Ether
|
||||
* ++-+---+---+---+- 16 15 PCI_DIS
|
||||
* +-+---+---+---+- 17 14 USB_SE
|
||||
* | | | | 18 13 USB
|
||||
* +---+---+---+- 19 12 USB
|
||||
* | | | 20 11 PSC3
|
||||
* | | | 21 10 PSC3
|
||||
* | | | 22 9 PSC3
|
||||
* +---+---+- 23 8 PSC3
|
||||
* | | 24 7 -
|
||||
* | | 25 6 PSC2
|
||||
* | | 26 5 PSC2
|
||||
* +---+- 27 4 PSC2
|
||||
* | 28 3 -
|
||||
* | 29 2 PSC1
|
||||
* | 30 1 PSC1
|
||||
* +- 31 0 PSC1
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "=> "
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_LOOPW
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_CS2_START 0xe0000000
|
||||
#define CONFIG_SYS_CS2_SIZE 0x00100000
|
||||
|
||||
/* FPGA slave io (512kiB) - see ticket #66 */
|
||||
#define CONFIG_SYS_CS3_START 0xE9000000
|
||||
#define CONFIG_SYS_CS3_SIZE 0x00080000
|
||||
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
|
||||
#define CONFIG_SYS_CS3_CFG 0x0032B900
|
||||
|
||||
/* Diagnosis Interface - see ticket #63 */
|
||||
#define CONFIG_SYS_CS4_START 0xEA000000
|
||||
#define CONFIG_SYS_CS4_SIZE 0x00000001
|
||||
/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
|
||||
#define CONFIG_SYS_CS4_CFG 0x0002B900
|
||||
|
||||
/* FPGA master io (64kiB) - see ticket #66 */
|
||||
#define CONFIG_SYS_CS5_START 0xE8000000
|
||||
#define CONFIG_SYS_CS5_SIZE 0x00010000
|
||||
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
|
||||
#define CONFIG_SYS_CS5_CFG 0x0032B900
|
||||
|
||||
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
|
||||
#define CONFIG_SYS_CS1_CFG 0x0004FB00
|
||||
#define CONFIG_SYS_CS2_CFG 0x0006F90C
|
||||
#else /* for pci_clk = 33 MHz */
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
|
||||
#define CONFIG_SYS_CS1_CFG 0x0001FB00
|
||||
#define CONFIG_SYS_CS2_CFG 0x0002F90C
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
|
||||
/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
|
||||
/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
|
||||
"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_SYS_OS_BASE 0xfc080000
|
||||
#define CONFIG_SYS_FDT_BASE 0xfc060000
|
||||
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"verify=no\0" \
|
||||
"consoledev=ttyPSC0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} " \
|
||||
"console=${consoledev},${baudrate}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr} - ${fdtaddr}\0" \
|
||||
"flash_mtd=run mtdargs addip addtty;" \
|
||||
"bootm ${kernel_addr} - ${fdtaddr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
|
||||
"net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \
|
||||
"tftp c00000 ${fdtfile};" \
|
||||
"run nfsargs addip addtty;" \
|
||||
"bootm ${loadaddr} - c00000\0" \
|
||||
"load=tftp ${loadaddr} u-boot.bin\0" \
|
||||
"update=protect off fc000000 fc03ffff; " \
|
||||
"era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
|
||||
"upd=run load;run update\0" \
|
||||
"fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \
|
||||
"fdtfile=dtbFile\0" \
|
||||
"kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_mtd"
|
||||
|
||||
/*
|
||||
* SPL related defines
|
||||
*/
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_NOR_SUPPORT
|
||||
#define CONFIG_SPL_TEXT_BASE 0xfc000000
|
||||
#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
|
||||
/* Place BSS for SPL near end of SDRAM */
|
||||
#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
|
||||
|
||||
#define CONFIG_SPL_OS_BOOT
|
||||
/* Place patched DT blob (fdt) at this address */
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
|
||||
|
||||
/* Settings for real U-Boot to be loaded from NOR flash */
|
||||
#ifndef __ASSEMBLY__
|
||||
extern char __spl_flash_end[];
|
||||
#endif
|
||||
#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
|
||||
#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
|
||||
#define CONFIG_SYS_UBOOT_START 0x1000100
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue