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cpu/mips/cpu.c: Fix flush_cache bug 

Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
This commit is contained in:
Shinya Kuribayashi 2008-04-08 16:20:35 +09:00 committed by Wolfgang Denk
parent 8f2a68a07c
commit 188e94c370
1 changed files with 2 additions and 2 deletions
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4
cpu/mips/cpu.c
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@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, start_addr);
cache_op(Hit_Invalidate_I, start_addr);
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;