sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

Merge branch 'master' of git://git.denx.de/u-boot-arm

This commit is contained in:
Tom Rini 2012-10-04 10:00:42 -07:00
parent 73c15c634d 777544085d
commit 1981668777
150 changed files with 13851 additions and 181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
MAINTAINERS
View File

@ -251,6 +251,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
Gabriel Huau <contact@huau-gabriel.fr>
mini2440 s3c2440
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
@ -777,6 +781,11 @@ Nagendra T S <nagendra@mistralsolutions.com>
am3517_crane ARM ARMV7 (AM35x SoC)
Dinh Nguyen <dinguyen@altera.com>
Chin Liang See <clsee@altera.com>
socfpga socfpga_cyclone5
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
@ -799,6 +808,7 @@ Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Luka Perkov <uboot@lukaperkov.net>
ib62x0 ARM926EJS
iconnect ARM926EJS
Dave Peverley <dpeverley@mpc-data.co.uk>
@ -852,6 +862,8 @@ John Rigby <jcrigby@gmail.com>
Stefan Roese <sr@denx.de>
x600 ARM926EJS (spear600 Soc)
pdnb3 xscale/ixp
scpu xscale/ixp
@ -890,6 +902,10 @@ Matt Sealey <matt@genesi-usa.com>
Bo Shen <voice.shen@atmel.com>
at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
Michal Simek <monstr@monstr.eu>
zynq ARM ARMV7 (Zynq SoC)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
@ -990,6 +1006,14 @@ Zhong Hongbo <bocui107@gmail.com>
SMDK6400 ARM1176 (S3C6400 SoC)
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
kzm9g SH73A0 (RMOBILE SoC)
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
armadillo-800eva R8A7740 (RMOBILE SoC)
-------------------------------------------------------------------------
Unknown / orphaned boards:

18
arch/arm/config.mk
View File

@ -87,3 +87,21 @@ endif
ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
endif
#
# FIXME: binutils versions < 2.22 have a bug in the assembler where
# branches to weak symbols can be incorrectly optimized in thumb mode
# to a short branch (b.n instruction) that won't reach when the symbol
# gets preempted
#
# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
#
ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
ifeq ($(GAS_BUG_12532),)
export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
then echo y; else echo n; fi)
endif
ifeq ($(GAS_BUG_12532),y)
PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
endif
endif

1
arch/arm/cpu/arm1136/start.S
View File

@ -190,6 +190,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/arm1176/start.S
View File

@ -252,6 +252,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/arm920t/start.S
View File

@ -210,6 +210,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/arm925t/start.S
View File

@ -204,6 +204,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

58
arch/arm/cpu/arm926ejs/kirkwood/dram.c
View File

@ -30,38 +30,84 @@
DECLARE_GLOBAL_DATA_PTR;
#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
struct kw_sdram_bank {
u32 win_bar;
u32 win_sz;
};
struct kw_sdram_addr_dec {
struct kw_sdram_bank sdram_bank[4];
};
#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
/*
* kw_sdram_bar - reads SDRAM Base Address Register
*/
u32 kw_sdram_bar(enum memory_bank bank)
{
struct kw_sdram_addr_dec *base =
(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
u32 result = 0;
u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
if ((!enable) || (bank > BANK3))
return 0;
result = readl(KW_REG_CPUCS_WIN_BAR(bank));
result = readl(&base->sdram_bank[bank].win_bar);
return result;
}
/*
* kw_sdram_bs_set - writes SDRAM Bank size
*/
static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
{
struct kw_sdram_addr_dec *base =
(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
/* Read current register value */
u32 reg = readl(&base->sdram_bank[bank].win_sz);
/* Clear window size */
reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
/* Set new window size */
reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
writel(reg, &base->sdram_bank[bank].win_sz);
}
/*
* kw_sdram_bs - reads SDRAM Bank size
*/
u32 kw_sdram_bs(enum memory_bank bank)
{
struct kw_sdram_addr_dec *base =
(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
u32 result = 0;
u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
if ((!enable) || (bank > BANK3))
return 0;
result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
result += 0x01000000;
return result;
}
void kw_sdram_size_adjust(enum memory_bank bank)
{
u32 size;
/* probe currently equipped RAM size */
size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
/* adjust SDRAM window size accordingly */
kw_sdram_bs_set(bank, size);
}
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{

1
arch/arm/cpu/arm926ejs/start.S
View File

@ -236,6 +236,7 @@ stack_setup:
adr r0, _start
sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/arm946es/start.S
View File

@ -175,6 +175,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/arm_intcm/start.S
View File

@ -171,6 +171,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/armv7/highbank/config.mk
View File

@ -1 +0,0 @@
PLATFORM_CPPFLAGS += -march=armv7-a

9
arch/arm/cpu/armv7/omap-common/config.mk
View File

@ -20,15 +20,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5
# =========================================================================
#
# Supply options according to compiler version
#
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

5
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
View File

@ -27,6 +27,7 @@
*/
#include <asm/arch/omap.h>
#include <asm/arch/spl.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
@ -59,9 +60,9 @@ ENTRY(save_boot_params)
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #2
cmp r2, #BOOT_DEVICE_XIP
blt 2f
cmp r2, #7
cmp r2, #BOOT_DEVICE_MMC2
bgt 2f
/* Store the boot mode (raw/FAT) in omap_bootmode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr

65
arch/arm/cpu/armv7/rmobile/Makefile Normal file
View File

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS = lowlevel_init.o
COBJS-y += cpu_info.o
COBJS-y += emac.o
COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
# from arch/sh/lib/ directory
$(obj)sh_timer.c:
@rm -f $(obj)sh_timer.c
ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

31
arch/arm/cpu/armv7/rmobile/board.c Normal file
View File

@ -0,0 +1,31 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
int checkboard(void)
{
printf("Board: %s\n", sysinfo.board_string);
return 0;
}

26
arch/arm/cpu/armv7/rmobile/config.mk Normal file
View File

@ -0,0 +1,26 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5

48
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c Normal file
View File

@ -0,0 +1,48 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
{
u32 id;
u32 type;
struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
id = readl(hpb->cccr);
type = (id >> 8) & 0xFF;
return type;
}
u32 rmobile_get_cpu_rev(void)
{
u32 id;
u32 rev;
struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
id = readl(hpb->cccr);
rev = (id >> 4) & 0xF;
return rev;
}

60
arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c Normal file
View File

@ -0,0 +1,60 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
{
u32 id;
u32 type;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
type = (id >> 8) & 0xFF;
return type;
}
u32 rmobile_get_cpu_rev_integer(void)
{
u32 id;
u32 rev;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
rev = ((id >> 4) & 0xF) + 1;
return rev;
}
u32 rmobile_get_cpu_rev_fraction(void)
{
u32 id;
u32 rev;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
id = readl(&hpb->cccr);
rev = id & 0xF;
return rev;
}

85
arch/arm/cpu/armv7/rmobile/cpu_info.c Normal file
View File

@ -0,0 +1,85 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
icache_enable();
return 0;
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
dcache_enable();
}
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
static u32 __rmobile_get_cpu_type(void)
{
return 0x0;
}
u32 rmobile_get_cpu_type(void)
__attribute__((weak, alias("__rmobile_get_cpu_type")));
static u32 __rmobile_get_cpu_rev_integer(void)
{
return 0;
}
u32 rmobile_get_cpu_rev_integer(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
static u32 __rmobile_get_cpu_rev_fraction(void)
{
return 0;
}
u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
int print_cpuinfo(void)
{
switch (rmobile_get_cpu_type()) {
case 0x37:
printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
case 0x40:
printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
default:
printf("CPU: Renesas Electronics CPU rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
}
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

36
arch/arm/cpu/armv7/rmobile/emac.c Normal file
View File

@ -0,0 +1,36 @@
/*
* RMOBILE EtherMAC initialization.
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <common.h>
#include <asm/errno.h>
#include <netdev.h>
int cpu_eth_init(bd_t *bis)
{
int ret = -ENODEV;
#ifdef CONFIG_SH_ETHER
ret = sh_eth_initialize(bis);
#endif
return ret;
}

98
arch/arm/cpu/armv7/rmobile/lowlevel_init.S Normal file
View File

@ -0,0 +1,98 @@
/*
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
ldr r0, =MERAM_BASE
mov r1, #0x0
str r1, [r0]
mrc p15, 0, r0, c0, c0, 5
ands r0, r0, #0xF
beq lowlevel_init__
b wait_interrupt
.pool
.align 4
wait_interrupt:
#ifdef ICCICR
ldr r1, =ICCICR
mov r2, #0x0
str r2, [r1]
mov r2, #0xF0
adds r1, r1, #4 /* ICCPMR */
str r2, [r1]
ldr r1, =ICCICR
mov r2, #0x1
str r2, [r1]
#endif
wait_loop:
.long 0xE320F003 /* wfi */
ldr r2, [r1, #0xC]
str r2, [r1, #0x10]
ldr r0, =MERAM_BASE
ldr r2, [r0]
cmp r2, #0
movne pc, r2
b wait_loop
wait_loop_end:
.pool
.align 4
lowlevel_init__:
mov r0, #0x200000
loop0:
subs r0, r0, #1
bne loop0
ldr sp, MERAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
bl s_init
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
/* back to arch calling code */
mov pc, lr
.pool
.align 4
ENDPROC(lowlevel_init)
.ltorg
MERAM_STACK:
.word LOW_LEVEL_MERAM_STACK

2612
arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c Normal file
View File

File diff suppressed because it is too large Load Diff

2807
arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c Normal file
View File

File diff suppressed because it is too large Load Diff

97
arch/arm/cpu/armv7/rmobile/timer.c Normal file
View File

@ -0,0 +1,97 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-armv7/globaltimer.h>
#include <asm/arch/rmobile.h>
static struct globaltimer *global_timer = \
(struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
#define CLK2MHZ(clk) (clk / 1000 / 1000)
static u64 get_cpu_global_timer(void)
{
u32 low, high;
u64 timer;
u32 old = readl(&global_timer->cnt_h);
while (1) {
low = readl(&global_timer->cnt_l);
high = readl(&global_timer->cnt_h);
if (old == high)
break;
else
old = high;
}
timer = high;
return (u64)((timer << 32) | low);
}
static u64 get_time_us(void)
{
u64 timer = get_cpu_global_timer();
timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
return timer;
}
static ulong get_time_ms(void)
{
return (ulong)(get_time_us() / 1000);
}
int timer_init(void)
{
writel(0x01, &global_timer->ctl);
return 0;
}
void __udelay(unsigned long usec)
{
u64 start, current;
u64 wait;
start = get_cpu_global_timer();
wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
do {
current = get_cpu_global_timer();
} while ((current - start) < wait);
}
ulong get_timer(ulong base)
{
return get_time_ms() - base;
}
unsigned long long get_ticks(void)
{
return get_cpu_global_timer();
}
ulong get_tbclk(void)
{
return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
}

51
arch/arm/cpu/armv7/socfpga/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012 Altera Corporation <www.altera.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
COBJS-y := misc.o timer.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

16
arch/arm/cpu/armv7/socfpga/config.mk Normal file
View File

@ -0,0 +1,16 @@
#
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
# kind, whether express or implied; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.img
endif

77
arch/arm/cpu/armv7/socfpga/lowlevel_init.S Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <version.h>
/* Save the parameter pass in by previous boot loader */
.global save_boot_params
save_boot_params:
/* save the parameter here */
/*
* Setup stack for exception, which is located
* at the end of on-chip RAM. We don't expect exception prior to
* relocation and if that happens, we won't worry -- it will overide
* global data region as the code will goto reset. After relocation,
* this region won't be used by other part of program.
* Hence it is safe.
*/
ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
ldr r1, =IRQ_STACK_START_IN
str r0, [r1]
bx lr
/* Set up the platform, once the cpu has been initialized */
.globl lowlevel_init
lowlevel_init:
/* Remap */
#ifdef CONFIG_SPL_BUILD
/*
* SPL : configure the remap (L3 NIC-301 GPV)
* so the on-chip RAM at lower memory instead ROM.
*/
ldr r0, =SOCFPGA_L3REGS_ADDRESS
mov r1, #0x19
str r1, [r0]
#else
/*
* U-Boot : configure the remap (L3 NIC-301 GPV)
* so the SDRAM at lower memory instead on-chip RAM.
*/
ldr r0, =SOCFPGA_L3REGS_ADDRESS
mov r1, #0x2
str r1, [r0]
/* Private components security */
/*
* U-Boot : configure private timer, global timer and cpu
* component access as non secure for kernel stage (as required
* by kernel)
*/
mrc p15,4,r0,c15,c0,0
add r1, r0, #0x54
ldr r2, [r1]
orr r2, r2, #0xff
orr r2, r2, #0xf00
str r2, [r1]
#endif /* #ifdef CONFIG_SPL_BUILD */
mov pc, lr

54
arch/arm/cpu/armv7/socfpga/misc.c Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
{
/* request a warm reset */
writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
/*
* infinite loop here as watchdog will trigger and reset
* the processor
*/
while (1)
;
}
/*
* Release peripherals from reset based on handoff
*/
void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}

48
arch/arm/cpu/armv7/socfpga/spl.c Normal file
View File

@ -0,0 +1,48 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <version.h>
#include <image.h>
#include <malloc.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
return BOOT_DEVICE_RAM;
}
/*
* Board initialization after bss clearance
*/
void spl_board_init(void)
{
/* init timer for enabling delay function */
timer_init();
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
/* enable console uart printing */
preloader_console_init();
}

104
arch/arm/cpu/armv7/socfpga/timer.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
/*
* Timer initialization
*/
int timer_init(void)
{
writel(TIMER_LOAD_VAL, &timer_base->load_val);
writel(TIMER_LOAD_VAL, &timer_base->curr_val);
writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
return 0;
}
static u32 read_timer(void)
{
return readl(&timer_base->curr_val);
}
/*
* Delay x useconds
*/
void __udelay(unsigned long usec)
{
unsigned long now, last;
/*
* get the tmo value based on timer clock speed
* tmo = delay required / period of timer clock
*/
long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
last = read_timer();
while (tmo > 0) {
now = read_timer();
if (last >= now)
/* normal mode (non roll) */
tmo -= last - now;
else
/* we have overflow of the count down timer */
tmo -= TIMER_LOAD_VAL - last + now;
last = now;
}
}
/*
* Get the timer value
*/
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* Timer : get the time difference
* Unit of tick is based on the CONFIG_SYS_HZ
*/
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
if (gd->lastinc >= now) {
/* normal mode (non roll) */
/* move stamp forward with absolute diff ticks */
gd->tbl += gd->lastinc - now;
} else {
/* we have overflow of the count down timer */
gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
}
gd->lastinc = now;
return gd->tbl;
}
/*
* Reset the timer
*/
void reset_timer(void)
{
/* capture current decrementer value time */
gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
/* start "advancing" time stamp from 0 */
gd->tbl = 0;
}

60
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds Normal file
View File

@ -0,0 +1,60 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} >.sdram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end__ = .;
} >.sdram
. = ALIGN(8);
__malloc_start = .;
. = . + CONFIG_SPL_MALLOC_SIZE;
__malloc_end = .;
. = . + CONFIG_SPL_STACK_SIZE;
. = ALIGN(8);
__stack_start = .;
}

5
arch/arm/cpu/armv7/start.S
View File

@ -360,10 +360,7 @@ ENTRY(cpu_init_crit)
* basic memory. Go here to bump up clock rate and handle
* wake up conditions.
*/
mov ip, lr @ persevere link reg across call
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif

51
arch/arm/cpu/armv7/zynq/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y := timer.o
COBJS-y += cpu.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

31
arch/arm/cpu/armv7/zynq/cpu.c Normal file
View File

@ -0,0 +1,31 @@
/*
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
inline void lowlevel_init(void) {}
void reset_cpu(ulong addr)
{
while (1)
;
}

150
arch/arm/cpu/armv7/zynq/timer.c Normal file
View File

@ -0,0 +1,150 @@
/*
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* (C) Copyright 2004
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
*
* (C) Copyright 2002-2004
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2003
* Texas Instruments <www.ti.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct scu_timer {
u32 load; /* Timer Load Register */
u32 counter; /* Timer Counter Register */
u32 control; /* Timer Control Register */
};
static struct scu_timer *timer_base =
(struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
#define TIMER_LOAD_VAL 0xFFFFFFFF
#define TIMER_PRESCALE 255
#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
int timer_init(void)
{
const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
SCUTIMER_CONTROL_ENABLE_MASK;
/* Load the timer counter register */
writel(0xFFFFFFFF, &timer_base->counter);
/*
* Start the A9Timer device
* Enable Auto reload mode, Clear prescaler control bits
* Set prescaler value, Enable the decrementer
*/
clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
emask);
/* Reset time */
gd->lastinc = readl(&timer_base->counter) /
(TIMER_TICK_HZ / CONFIG_SYS_HZ);
gd->tbl = 0;
return 0;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
ulong get_timer_masked(void)
{
ulong now;
now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
if (gd->lastinc >= now) {
/* Normal mode */
gd->tbl += gd->lastinc - now;
} else {
/* We have an overflow ... */
gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
}
gd->lastinc = now;
return gd->tbl;
}
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = usec / (1000000 / CONFIG_SYS_HZ);
tmp = get_ticks() + tmo; /* Get current timestamp */
while (get_ticks() < tmp) { /* Loop till event */
/* NOP */;
}
}
/* Timer without interrupts */
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

1
arch/arm/cpu/ixp/start.S
View File

@ -273,6 +273,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/lh7a40x/start.S
View File

@ -184,6 +184,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/pxa/start.S
View File

@ -197,6 +197,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/s3c44b0/start.S
View File

@ -156,6 +156,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

1
arch/arm/cpu/sa1100/start.S
View File

@ -160,6 +160,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs

9
arch/arm/imx-common/cpu.c
View File

@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <ipu_pixfmt.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@ -138,3 +139,11 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
#if defined(CONFIG_VIDEO_IPUV3)
void arch_preboot_os(void)
{
/* disable video before launching O/S */
ipuv3_fb_shutdown();
}
#endif

2
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -23,9 +23,11 @@
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_SPL_H_
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif

36
arch/arm/include/asm/arch-armv7/globaltimer.h Normal file
View File

@ -0,0 +1,36 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _GLOBALTIMER_H_
#define _GLOBALTIMER_H_
struct globaltimer {
u32 cnt_l; /* 0x00 */
u32 cnt_h;
u32 ctl;
u32 stat;
u32 cmp_l; /* 0x10 */
u32 cmp_h;
u32 inc;
};
#endif /* _GLOBALTIMER_H_ */

2
arch/arm/include/asm/arch-kirkwood/cpu.h
View File

@ -155,10 +155,10 @@ struct kwgpio_registers {
/*
* functions
*/
void reset_cpu(unsigned long ignored);
unsigned char get_random_hex(void);
unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
void kw_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);

2
arch/arm/include/asm/arch-kirkwood/mpp.h
View File

@ -85,7 +85,7 @@
#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )

2
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -321,6 +321,8 @@
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#define BOARD_VER_OFFSET 0x8
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

1
arch/arm/include/asm/arch-orion5x/cpu.h
View File

@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers {
/*
* functions
*/
void reset_cpu(unsigned long ignored);
u32 orion5x_device_id(void);
u32 orion5x_device_rev(void);
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);

12
arch/arm/include/asm/arch-rmobile/gpio.h Normal file
View File

@ -0,0 +1,12 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#if defined(CONFIG_SH73A0)
#include "sh73a0-gpio.h"
void sh73a0_pinmux_init(void);
#elif defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

18
arch/arm/include/asm/arch-rmobile/irqs.h Normal file
View File

@ -0,0 +1,18 @@
#ifndef __ASM_MACH_IRQS_H
#define __ASM_MACH_IRQS_H
#define NR_IRQS 1024
/* GIC */
#define gic_spi(nr) ((nr) + 32)
/* INTCA */
#define evt2irq(evt) (((evt) >> 5) - 16)
#define irq2evt(irq) (((irq) + 16) << 5)
/* INTCS */
#define INTCS_VECT_BASE 0x2200
#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
#endif /* __ASM_MACH_IRQS_H */

584
arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h Normal file
View File

@ -0,0 +1,584 @@
/*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_R8A7740_H__
#define __ASM_R8A7740_H__
/*
* MD_CKx pin
*/
#define MD_CK2 (1 << 2)
#define MD_CK1 (1 << 1)
#define MD_CK0 (1 << 0)
/*
* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* PORT */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211,
/* IRQ */
GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
GPIO_FN_IRQ1,
GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
GPIO_FN_IRQ8,
GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
GPIO_FN_IRQ10,
GPIO_FN_IRQ11,
GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
GPIO_FN_IRQ17,
GPIO_FN_IRQ18,
GPIO_FN_IRQ19,
GPIO_FN_IRQ20,
GPIO_FN_IRQ21,
GPIO_FN_IRQ22,
GPIO_FN_IRQ23,
GPIO_FN_IRQ24,
GPIO_FN_IRQ25,
GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
/* Function */
/* DBGT */
GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
GPIO_FN_DBGMD21,
/* FSI */
GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
GPIO_FN_FSIAISLD_PORT5,
GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
GPIO_FN_FSIASPDIF_PORT18,
GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
GPIO_FN_FSIAIBT,
/* FMSI */
GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
GPIO_FN_FMSISLD_PORT6,
GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
GPIO_FN_FMSOCK,
/* SCIFA0 */
GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_TXD,
/* SCIFA1 */
GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
GPIO_FN_SCIFA1_RTS,
/* SCIFA2 */
GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
GPIO_FN_SCIFA2_SCK_PORT199,
GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
/* SCIFA3 */
GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
GPIO_FN_SCIFA3_SCK_PORT116,
GPIO_FN_SCIFA3_CTS_PORT117,
GPIO_FN_SCIFA3_RXD_PORT174,
GPIO_FN_SCIFA3_TXD_PORT175,
GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
GPIO_FN_SCIFA3_SCK_PORT158,
GPIO_FN_SCIFA3_CTS_PORT162,
GPIO_FN_SCIFA3_RXD_PORT159,
GPIO_FN_SCIFA3_TXD_PORT160,
/* SCIFA4 */
GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
GPIO_FN_SCIFA4_TXD_PORT13,
GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
GPIO_FN_SCIFA4_TXD_PORT203,
GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
GPIO_FN_SCIFA4_TXD_PORT93,
GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
GPIO_FN_SCIFA4_SCK_PORT205,
/* SCIFA5 */
GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
GPIO_FN_SCIFA5_RXD_PORT10,
GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
GPIO_FN_SCIFA5_TXD_PORT208,
GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
GPIO_FN_SCIFA5_RXD_PORT92,
GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
GPIO_FN_SCIFA5_SCK_PORT206,
/* SCIFA6 */
GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
/* SCIFA7 */
GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
/* SCIFAB */
GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
GPIO_FN_SCIFB_RXD_PORT191,
GPIO_FN_SCIFB_TXD_PORT192,
GPIO_FN_SCIFB_RTS_PORT186,
GPIO_FN_SCIFB_CTS_PORT187,
GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
GPIO_FN_SCIFB_RXD_PORT3,
GPIO_FN_SCIFB_TXD_PORT4,
GPIO_FN_SCIFB_RTS_PORT172,
GPIO_FN_SCIFB_CTS_PORT173,
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
GPIO_FN_RSPI_CK_A,
/* VIO CKO */
GPIO_FN_VIO_CKO1,
GPIO_FN_VIO_CKO2,
GPIO_FN_VIO_CKO_1,
GPIO_FN_VIO_CKO,
/* VIO0 */
GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
GPIO_FN_VIO0_D14_PORT25,
GPIO_FN_VIO0_D15_PORT24,
GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
GPIO_FN_VIO0_D14_PORT95,
GPIO_FN_VIO0_D15_PORT96,
/* VIO1 */
GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
/* TPU0 */
GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
GPIO_FN_TPU0TO3,
GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
GPIO_FN_TPU0TO2_PORT202,
/* SSP1 0 */
GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
/* SSP1 1 */
GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
GPIO_FN_STP1_IPEN_PORT187,
GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
GPIO_FN_STP1_IPEN_PORT193,
/* SIM */
GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
/* SDHI0 */
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
/* SDHI1 */
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
/* SDHI2 */
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
GPIO_FN_SDHI2_WP_PORT25,
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
GPIO_FN_SDHI2_CD_PORT202,
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_MSIOF2_RSCK,
/* KEYSC */
GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
GPIO_FN_KEYIN1_PORT44,
GPIO_FN_KEYIN2_PORT45,
GPIO_FN_KEYIN3_PORT46,
GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
GPIO_FN_KEYIN1_PORT57,
GPIO_FN_KEYIN2_PORT56,
GPIO_FN_KEYIN3_PORT55,
/* VOU */
GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
GPIO_FN_DV_CLK,
GPIO_FN_DV_VSYNC,
GPIO_FN_DV_HSYNC,
/* MEMC */
GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
GPIO_FN_MEMC_ADV,
GPIO_FN_MEMC_WAIT,
GPIO_FN_MEMC_BUSCLK,
GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
GPIO_FN_MEMC_DREQ0,
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
/* MMC */
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
GPIO_FN_MMC0_CLK_PORT66,
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
GPIO_FN_MMC1_CLK_PORT103,
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
/* MSIOF1 */
GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
GPIO_FN_MSIOF1_TSYNC_PORT120,
GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
GPIO_FN_MSIOF1_RXD_PORT75,
GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
/* GPIO */
GPIO_FN_GPO0, GPIO_FN_GPI0,
GPIO_FN_GPO1, GPIO_FN_GPI1,
/* USB0 */
GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
/* USB1 */
GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
/* BBIF1 */
GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
/* BBIF2 */
GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
GPIO_FN_BBIF2_RXD2_PORT60,
GPIO_FN_BBIF2_TSYNC2_PORT6,
GPIO_FN_BBIF2_TSCK2_PORT59,
GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
GPIO_FN_BBIF2_TXD2_PORT183,
GPIO_FN_BBIF2_TSCK2_PORT89,
GPIO_FN_BBIF2_TSYNC2_PORT184,
/* BSC / FLCTL / PCMCIA */
GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
GPIO_FN_CS5B, GPIO_FN_CS6A,
GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
GPIO_FN_CS5A_PORT19,
GPIO_FN_IOIS16, /* ? */
GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
GPIO_FN_A4_FOE, /* share with FLCTL */
GPIO_FN_A5_FCDE, /* share with FLCTL */
GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
GPIO_FN_A26,
GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
GPIO_FN_WE0_FWE, /* share with FLCTL */
GPIO_FN_WE1,
GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
GPIO_FN_RD_FSC, /* share with FLCTL */
GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
GPIO_FN_WAIT_PORT90,
GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
/* IRDA */
GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
/* ATAPI */
GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
/* RMII */
GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
GPIO_FN_RMII_REF50CK, /* for RMII */
GPIO_FN_RMII_REF125CK, /* for GMII */
/* GEther */
GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
/* DMA0 */
GPIO_FN_DREQ0, GPIO_FN_DACK0,
/* DMA1 */
GPIO_FN_DREQ1, GPIO_FN_DACK1,
/* SYSC */
GPIO_FN_RESETOUTS,
GPIO_FN_RESETP_PULLUP,
GPIO_FN_RESETP_PLAIN,
/* SDENC */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
/* IRREM */
GPIO_FN_IROUT,
/* DEBUG */
GPIO_FN_EDEBGREQ_PULLDOWN,
GPIO_FN_EDEBGREQ_PULLUP,
GPIO_FN_TRACEAUD_FROM_VIO,
GPIO_FN_TRACEAUD_FROM_LCDC0,
GPIO_FN_TRACEAUD_FROM_MEMC,
};
#endif /* __ASM_R8A7740_H__ */

287
arch/arm/include/asm/arch-rmobile/r8a7740.h Normal file
View File

@ -0,0 +1,287 @@
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_R8A7740_H
#define __ASM_ARCH_R8A7740_H
/*
* R8A7740 I/O Addresses
*/
#define MERAM_BASE 0xE5580000
#define DDRP_BASE 0xC12A0000
#define HPB_BASE 0xE6000000
#define RWDT0_BASE 0xE6020000
#define RWDT1_BASE 0xE6030000
#define GPIO_BASE 0xE6050000
#define CMT1_BASE 0xE6138000
#define CPG_BASE 0xE6150000
#define SYSC_BASE 0xE6180000
#define SDHI0_BASE 0xE6850000
#define SDHI1_BASE 0xE6860000
#define MMCIF_BASE 0xE6BD0000
#define SCIF5_BASE 0xE6CB0000
#define SCIF6_BASE 0xE6CC0000
#define DBSC_BASE 0xFE400000
#define BSC_BASE 0xFEC10000
#define I2C0_BASE 0xFFF20000
#define I2C1_BASE 0xE6C20000
#define TMU_BASE 0xFFF80000
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7740_rwdt {
u16 rwtcnt0; /* 0x00 */
u16 dummy0; /* 0x02 */
u16 rwtcsra0; /* 0x04 */
u16 dummy1; /* 0x06 */
u16 rwtcsrb0; /* 0x08 */
u16 dummy2; /* 0x0A */
};
/* HPB Semaphore Control Registers */
struct r8a7740_hpb {
u32 hpbctrl0;
u32 hpbctrl1;
u32 hpbctrl2;
u32 cccr;
u32 dummy0; /* 0x20 */
u32 hpbctrl4;
u32 hpbctrl5;
};
/* CPG */
struct r8a7740_cpg {
u32 frqcra;
u32 frqcrb;
u32 vclkcr1;
u32 vclkcr2;
u32 fmsickcr;
u32 fmsockcr;
u32 fsiackcr;
u32 dummy0; /* 0x1c */
u32 rtstbcr;
u32 systbcr;
u32 pllc01cr;
u32 pllc2cr;
u32 mstpsr0;
u32 dummy1; /* 0x34 */
u32 mstpsr1;
u32 mstpsr5;
u32 mstpsr2;
u32 dummy2; /* 0x44 */
u32 mstpsr3;
u32 mstpsr4;
u32 dummy3; /* 0x50 */
u32 astat;
u32 dummy4[4]; /* 0x58 .. 0x64 */
u32 ztrckcr;
u32 dummy5[5]; /* 0x6c .. 0x7c */
u32 subckcr;
u32 spuckcr;
u32 vouckcr;
u32 usbckcr;
u32 dummy6[3]; /* 0x90 .. 0x98 */
u32 stprckcr;
u32 srcr0;
u32 dummy7; /* 0xa4 */
u32 srcr1;
u32 dummy8; /* 0xac */
u32 srcr2;
u32 dummy9; /* 0xb4 */
u32 srcr3;
u32 srcr4;
u32 dummy10; /* 0xc0 */
u32 srcr5;
u32 pllc01stpcr;
u32 dummy11[5]; /* 0xcc .. 0xdc */
u32 frqcrc;
u32 frqcrd;
u32 dummy12[10]; /* 0xe8 .. 0x10c */
u32 rmstpcr0;
u32 rmstpcr1;
u32 rmstpcr2;
u32 rmstpcr3;
u32 rmstpcr4;
u32 rmstpcr5;
u32 dummy13[2]; /* 0x128 .. 0x12c */
u32 smstpcr0;
u32 smstpcr1;
u32 smstpcr2;
u32 smstpcr3;
u32 smstpcr4;
u32 smstpcr5;
};
/* BSC */
struct r8a7740_bsc {
u32 cmncr;
u32 cs0bcr;
u32 cs2bcr;
u32 dummy0; /* 0x0c */
u32 cs4bcr;
u32 cs5abcr;
u32 cs5bbcr;
u32 cs6abcr;
u32 dummy1; /* 0x20 */
u32 cs0wcr;
u32 cs2wcr;
u32 dummy2; /* 0x2c */
u32 cs4wcr;
u32 cs5awcr;
u32 cs5bwcr;
u32 cs6awcr;
u32 dummy3[5]; /* 0x40 .. 0x50 */
u32 rbwtcnt;
u32 busycr;
u32 dummy4[5]; /* 0x5c .. 0x6c */
u32 bromtimcr;
u32 dummy5[7]; /* 0x74 .. 0x8c */
u32 bptcr00;
u32 bptcr01;
u32 bptcr02;
u32 bptcr03;
u32 bptcr04;
u32 bptcr05;
u32 bptcr06;
u32 bptcr07;
u32 bptcr08;
u32 bptcr09;
u32 bptcr10;
u32 bptcr11;
u32 bptcr12;
u32 bptcr13;
u32 bptcr14;
u32 bptcr15;
u32 bptcr16;
u32 bptcr17;
u32 bptcr18;
u32 bptcr19;
u32 bptcr20;
u32 bptcr21;
u32 bptcr22;
u32 bptcr23;
u32 bptcr24;
u32 bptcr25;
u32 bptcr26;
u32 bptcr27;
u32 bptcr28;
u32 bptcr29;
u32 bptcr30;
u32 bptcr31;
u32 bswcr;
u32 dummy6[68]; /* 0x114 .. 0x220 */
u32 cs0wcr2;
u32 cs2wcr2;
u32 dummy7; /* 0x22c */
u32 cs4wcr2;
};
#define CS0WCR2 0xFEC10224
#define CS2WCR2 0xFEC10228
#define CS4WCR2 0xFEC10230
/* DDRP */
struct r8a7740_ddrp {
u32 funcctrl;
u32 dllctrl;
u32 zqcalctrl;
u32 zqodtctrl;
u32 rdctrl;
u32 rdtmg;
u32 fifoinit;
u32 outctrl;
u32 dummy0[50]; /* 0x20 .. 0xe4 */
u32 dqcalofs1;
u32 dqcalofs2;
u32 dummy1[2]; /* 0xf0 .. 0xf4 */
u32 dqcalexp;
};
#define DDRPNCNT 0xE605803C
#define DDRVREFCNT 0xE61500EC
/* DBSC */
struct r8a7740_dbsc {
u32 dummy0;
u32 dbsvcr;
u32 dbstate0;
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2c */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3c */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4c */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xac */
u32 dbbl;
u32 dummy5[3]; /* 0xb4 .. 0xbc */
u32 dbadj0;
u32 dbadj1;
u32 dbadj2;
u32 dummy6[5]; /* 0xcc .. 0xdc */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dbrfcnf3;
u32 dummy7; /* 0xf0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy8; /* 0xfc */;
u32 dbrnk0;
u32 dummy9[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy10[7]; /* 0x184 .. 0x19C */
u32 dbmrrdr;
u32 dummy11[39]; /* 0x1A4 .. 0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[46]; /* 0x248 .. 0x2FC */
u32 dbbs0cnt0;
u32 dbbs0cnt1;
};
#endif
#endif /* __ASM_ARCH_R8A7740_H */

14
arch/arm/include/asm/arch-rmobile/rmobile.h Normal file
View File

@ -0,0 +1,14 @@
#ifndef __ASM_ARCH_RMOBILE_H
#define __ASM_ARCH_RMOBILE_H
#if defined(CONFIG_RMOBILE)
#if defined(CONFIG_SH73A0)
#include <asm/arch/sh73a0.h>
#elif defined(CONFIG_R8A7740)
#include <asm/arch/r8a7740.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_RMOBILE */
#endif /* __ASM_ARCH_RMOBILE_H */

553
arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h Normal file
View File

@ -0,0 +1,553 @@
#ifndef __ASM_SH73A0_H__
#define __ASM_SH73A0_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function and MSEL switch
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* Hardware manual Table 25-1 (GPIO) */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
GPIO_PORT288, GPIO_PORT289,
GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
GPIO_FN_VBUS_0,
GPIO_FN_GPI0,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
GPIO_FN_GPI3,
GPIO_FN_GPI4,
GPIO_FN_GPI5,
GPIO_FN_GPI6,
GPIO_FN_GPI7,
GPIO_FN_SCIFA7_RXD,
GPIO_FN_SCIFA7_CTS_,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
GPIO_FN_PORT16_VIO_CKOR,
GPIO_FN_SCIFA0_TXD,
GPIO_FN_SCIFA7_TXD,
GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
GPIO_FN_GPO1,
GPIO_FN_GPO2, GPIO_FN_STATUS0,
GPIO_FN_GPO3, GPIO_FN_STATUS1,
GPIO_FN_GPO4, GPIO_FN_STATUS2,
GPIO_FN_VINT,
GPIO_FN_TCKON,
GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
GPIO_FN_PORT28_TPU1TO1,
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
GPIO_FN_SCIFA4_TXD,
GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
GPIO_FN_SCIFA4_RTS_,
GPIO_FN_SCIFA4_CTS_,
GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
GPIO_FN_FSIBOSLD,
GPIO_FN_FSIBISLD,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
GPIO_FN_FSIAOMC,
GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
GPIO_FN_A14, GPIO_FN_KEYOUT5,
GPIO_FN_A15, GPIO_FN_KEYOUT4,
GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26, GPIO_FN_KEYIN6,
GPIO_FN_KEYIN7,
GPIO_FN_D0_NAF0,
GPIO_FN_D1_NAF1,
GPIO_FN_D2_NAF2,
GPIO_FN_D3_NAF3,
GPIO_FN_D4_NAF4,
GPIO_FN_D5_NAF5,
GPIO_FN_D6_NAF6,
GPIO_FN_D7_NAF7,
GPIO_FN_D8_NAF8,
GPIO_FN_D9_NAF9,
GPIO_FN_D10_NAF10,
GPIO_FN_D11_NAF11,
GPIO_FN_D12_NAF12,
GPIO_FN_D13_NAF13,
GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
GPIO_FN_CS4_,
GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
GPIO_FN_CS5B_, GPIO_FN_FCE1_,
GPIO_FN_CS6B_, GPIO_FN_DACK0,
GPIO_FN_FCE0_, GPIO_FN_CS6A_,
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
GPIO_FN_RD__FSC,
GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
GPIO_FN_WE1_,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT_,
GPIO_FN_NBRST_,
GPIO_FN_BBIF2_TXD,
GPIO_FN_BBIF2_RXD,
GPIO_FN_BBIF2_SYNC,
GPIO_FN_BBIF2_SCK,
GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
GPIO_FN_SCIFA3_TXD,
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
GPIO_FN_PORT115_I2C_SCL3,
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
GPIO_FN_PORT116_I2C_SDA3,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
GPIO_FN_LCD2D0,
GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
GPIO_FN_LCD2D6,
GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
GPIO_FN_LCD2D7,
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
GPIO_FN_LCD2D2,
GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
GPIO_FN_LCD2D4,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
GPIO_FN_VIO_CKO,
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
GPIO_FN_PORT149_KEYOUT9,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
GPIO_FN_TPU3TO0,
GPIO_FN_LCDD0,
GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
GPIO_FN_TPU2TO1,
GPIO_FN_LCDD6,
GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
GPIO_FN_LCDD8, GPIO_FN_D16,
GPIO_FN_LCDD9, GPIO_FN_D17,
GPIO_FN_LCDD10, GPIO_FN_D18,
GPIO_FN_LCDD11, GPIO_FN_D19,
GPIO_FN_LCDD12, GPIO_FN_D20,
GPIO_FN_LCDD13, GPIO_FN_D21,
GPIO_FN_LCDD14, GPIO_FN_D22,
GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
GPIO_FN_LCDD17, GPIO_FN_D25,
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
GPIO_FN_PORT218_VIO_CKOR,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
GPIO_FN_LCD2DCK_2,
GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
GPIO_FN_PORT221_LCD2HSYN,
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
GPIO_FN_SCIFA1_RXD,
GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
GPIO_FN_LCD2D20,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
GPIO_FN_LCD2D21,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_SDHICLK0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0,
GPIO_FN_SDHID0_1,
GPIO_FN_SDHID0_2,
GPIO_FN_SDHID0_3,
GPIO_FN_SDHICMD0,
GPIO_FN_SDHIWP0,
GPIO_FN_SDHICLK1,
GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
GPIO_FN_SDHICMD1,
GPIO_FN_SDHICLK2,
GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
GPIO_FN_SDHICMD2,
GPIO_FN_MMCCLK0,
GPIO_FN_MMCD0_0,
GPIO_FN_MMCD0_1,
GPIO_FN_MMCD0_2,
GPIO_FN_MMCD0_3,
GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
GPIO_FN_MMCCMD0,
GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
GPIO_FN_MCP_WAIT__MCP_FRB,
GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
GPIO_FN_MCP_D15_MCP_NAF15,
GPIO_FN_MCP_D14_MCP_NAF14,
GPIO_FN_MCP_D13_MCP_NAF13,
GPIO_FN_MCP_D12_MCP_NAF12,
GPIO_FN_MCP_D11_MCP_NAF11,
GPIO_FN_MCP_D10_MCP_NAF10,
GPIO_FN_MCP_D9_MCP_NAF9,
GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
GPIO_FN_MCP_NBRSTOUT_,
GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
/* MSEL2 special case */
GPIO_FN_TSIF2_TS_XX1,
GPIO_FN_TSIF2_TS_XX2,
GPIO_FN_TSIF2_TS_XX3,
GPIO_FN_TSIF2_TS_XX4,
GPIO_FN_TSIF2_TS_XX5,
GPIO_FN_TSIF1_TS_XX1,
GPIO_FN_TSIF1_TS_XX2,
GPIO_FN_TSIF1_TS_XX3,
GPIO_FN_TSIF1_TS_XX4,
GPIO_FN_TSIF1_TS_XX5,
GPIO_FN_TSIF0_TS_XX1,
GPIO_FN_TSIF0_TS_XX2,
GPIO_FN_TSIF0_TS_XX3,
GPIO_FN_TSIF0_TS_XX4,
GPIO_FN_TSIF0_TS_XX5,
GPIO_FN_MST1_TS_XX1,
GPIO_FN_MST1_TS_XX2,
GPIO_FN_MST1_TS_XX3,
GPIO_FN_MST1_TS_XX4,
GPIO_FN_MST1_TS_XX5,
GPIO_FN_MST0_TS_XX1,
GPIO_FN_MST0_TS_XX2,
GPIO_FN_MST0_TS_XX3,
GPIO_FN_MST0_TS_XX4,
GPIO_FN_MST0_TS_XX5,
/* MSEL3 special cases */
GPIO_FN_SDHI0_VCCQ_MC0_ON,
GPIO_FN_SDHI0_VCCQ_MC0_OFF,
GPIO_FN_DEBUG_MON_VIO,
GPIO_FN_DEBUG_MON_LCDD,
GPIO_FN_LCDC_LCDC0,
GPIO_FN_LCDC_LCDC1,
/* MSEL4 special cases */
GPIO_FN_IRQ9_MEM_INT,
GPIO_FN_IRQ9_MCP_INT,
GPIO_FN_A11,
GPIO_FN_KEYOUT8,
GPIO_FN_TPU4TO3,
GPIO_FN_RESETA_N_PU_ON,
GPIO_FN_RESETA_N_PU_OFF,
GPIO_FN_EDBGREQ_PD,
GPIO_FN_EDBGREQ_PU,
/* Functions with pull-ups */
GPIO_FN_KEYIN0_PU,
GPIO_FN_KEYIN1_PU,
GPIO_FN_KEYIN2_PU,
GPIO_FN_KEYIN3_PU,
GPIO_FN_KEYIN4_PU,
GPIO_FN_KEYIN5_PU,
GPIO_FN_KEYIN6_PU,
GPIO_FN_KEYIN7_PU,
GPIO_FN_SDHICD0_PU,
GPIO_FN_SDHID0_0_PU,
GPIO_FN_SDHID0_1_PU,
GPIO_FN_SDHID0_2_PU,
GPIO_FN_SDHID0_3_PU,
GPIO_FN_SDHICMD0_PU,
GPIO_FN_SDHIWP0_PU,
GPIO_FN_SDHID1_0_PU,
GPIO_FN_SDHID1_1_PU,
GPIO_FN_SDHID1_2_PU,
GPIO_FN_SDHID1_3_PU,
GPIO_FN_SDHICMD1_PU,
GPIO_FN_SDHID2_0_PU,
GPIO_FN_SDHID2_1_PU,
GPIO_FN_SDHID2_2_PU,
GPIO_FN_SDHID2_3_PU,
GPIO_FN_SDHICMD2_PU,
GPIO_FN_MMCCMD0_PU,
GPIO_FN_MMCCMD1_PU,
GPIO_FN_MMCD0_0_PU,
GPIO_FN_MMCD0_1_PU,
GPIO_FN_MMCD0_2_PU,
GPIO_FN_MMCD0_3_PU,
GPIO_FN_MMCD0_4_PU,
GPIO_FN_MMCD0_5_PU,
GPIO_FN_MMCD0_6_PU,
GPIO_FN_MMCD0_7_PU,
GPIO_FN_FSIACK_PU,
GPIO_FN_FSIAILR_PU,
GPIO_FN_FSIAIBT_PU,
GPIO_FN_FSIAISLD_PU,
/* end of GPIO */
GPIO_NR,
};
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SCIF0_TX,
SHDMA_SLAVE_SCIF0_RX,
SHDMA_SLAVE_SCIF1_TX,
SHDMA_SLAVE_SCIF1_RX,
SHDMA_SLAVE_SCIF2_TX,
SHDMA_SLAVE_SCIF2_RX,
SHDMA_SLAVE_SCIF3_TX,
SHDMA_SLAVE_SCIF3_RX,
SHDMA_SLAVE_SCIF4_TX,
SHDMA_SLAVE_SCIF4_RX,
SHDMA_SLAVE_SCIF5_TX,
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
SHDMA_SLAVE_SCIF7_TX,
SHDMA_SLAVE_SCIF7_RX,
SHDMA_SLAVE_SCIF8_TX,
SHDMA_SLAVE_SCIF8_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI2_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
};
/*
* SH73A0 IRQ LOCATION TABLE
*
* 416 -----------------------------------------
* IRQ0-IRQ15
* 431 -----------------------------------------
* ...
* 448 -----------------------------------------
* sh73a0-intcs
* sh73a0-intca-irq-pins
* 680 -----------------------------------------
* ...
* 700 -----------------------------------------
* sh73a0-pint0
* 731 -----------------------------------------
* 732 -----------------------------------------
* sh73a0-pint1
* 739 -----------------------------------------
* ...
* 800 -----------------------------------------
* IRQ16-IRQ31
* 815 -----------------------------------------
* ...
* 928 -----------------------------------------
* sh73a0-intca-irq-pins
* 943 -----------------------------------------
*/
/* PINT interrupts are located at Linux IRQ 700 and up */
#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
#endif /* __ASM_SH73A0_H__ */

289
arch/arm/include/asm/arch-rmobile/sh73a0.h Normal file
View File

@ -0,0 +1,289 @@
#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
#define __ASM_ARCH_RMOBILE_SH73A0_H
/* Global Timer */
#define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
#define MERAM_BASE (0xE5580000)
/* GIC */
#define GIC_BASE (0xF0000100)
#define ICCICR GIC_BASE
/* Secure control register */
#define LIFEC_SEC_SRC (0xE6110008)
/* RWDT */
#define RWDT_BASE (0xE6020000)
/* HPB Semaphore Control Registers */
#define HPB_BASE (0xE6001010)
/* Bus Semaphore Control Registers */
#define HPBSCR_BASE (0xE6001600)
/* SBSC1 */
#define SBSC1_BASE (0xFE400000)
#define SDMRA1A (SBSC1_BASE + 0x100000)
#define SDMRA2A (SBSC1_BASE + 0x1C0000)
#define SDMRA3A (SBSC1_BASE + 0x104000)
/* SBSC2 */
#define SBSC2_BASE (0xFB400000)
#define SDMRA1B (SBSC2_BASE + 0x100000)
#define SDMRA2B (SBSC2_BASE + 0x1C0000)
#define SDMRA3B (SBSC2_BASE + 0x104000)
/* CPG */
#define CPG_BASE (0xE6150000)
#define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
#define WUPCR (CPG_BASE + 0x1010)
#define SRESCR (CPG_BASE + 0x1018)
#define PCLKCR (CPG_BASE + 0x1020)
/* SYSC */
#define SYSC_BASE (0xE6180000)
#define RESCNT2 (SYSC_BASE + 0x8020)
/* BSC */
#define BSC_BASE (0xFEC10000)
/* SCIF */
#define SCIF0_BASE (0xE6C40000)
#define SCIF1_BASE (0xE6C50000)
#define SCIF2_BASE (0xE6C60000)
#define SCIF3_BASE (0xE6C70000)
#define SCIF4_BASE (0xE6C80000)
#define SCIF5_BASE (0xE6CB0000)
#define SCIF6_BASE (0xE6CC0000)
#define SCIF7_BASE (0xE6CD0000)
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct sh73a0_rwdt {
u16 rwtcnt0; /* 0x00 */
u16 dummy0; /* 0x02 */
u16 rwtcsra0; /* 0x04 */
u16 dummy1; /* 0x06 */
u16 rwtcsrb0; /* 0x08 */
};
/* HPB Semaphore Control Registers */
struct sh73a0_hpb {
u32 hpbctrl0;
u32 hpbctrl1;
u32 hpbctrl2;
u32 cccr;
u32 dummy0; /* 0x20 */
u32 hpbctrl4;
u32 hpbctrl5;
u32 dummy1; /* 0x2C */
u32 hpbctrl6;
};
/* Bus Semaphore Control Registers */
struct sh73a0_hpb_bscr {
u32 mpsrc; /* 0x00 */
u32 mpacctl; /* 0x04 */
u32 dummy0[6];
u32 smgpiosrc; /* 0x20 */
u32 smgpioerr;
u32 smgpiotime;
u32 smgpiocnt;
u32 dummy1[4]; /* 0x30 .. 0x3C */
u32 smcmt2src;
u32 smcmt2err;
u32 smcmt2time;
u32 smcmt2cnt;
u32 smcpgsrc;
u32 smcpgerr;
u32 smcpgtime;
u32 smcpgcnt;
u32 dummy2[4]; /* 0x60 - 0x6C */
u32 smsyscsrc;
u32 smsyscerr;
u32 smsysctime;
u32 smsysccnt;
};
/* SBSC */
struct sh73a0_sbsc {
u32 dummy0[2]; /* 0x00, 0x04 */
u32 sdcr0;
u32 sdcr1;
u32 sdpcr;
u32 dummy1; /* 0x14 */
u32 sdcr0s;
u32 sdcr1s;
u32 rtcsr;
u32 dummy2; /* 0x24 */
u32 rtcor;
u32 rtcorh;
u32 rtcors;
u32 rtcorsh;
u32 dummy3[2]; /* 0x38, 0x3C */
u32 sdwcrc0;
u32 sdwcrc1;
u32 sdwcr00;
u32 sdwcr01;
u32 sdwcr10;
u32 sdwcr11;
u32 sdpdcr0;
u32 dummy4; /* 0x5C */
u32 sdwcr2;
u32 sdwcrc2;
u32 zqccr;
u32 dummy5[6]; /* 0x6C .. 0x80 */
u32 sdmracr0;
u32 dummy6; /* 0x88 */
u32 sdmrtmpcr;
u32 dummy7; /* 0x90 */
u32 sdmrtmpmsk;
u32 dummy8; /* 0x98 */
u32 sdgencnt;
u32 dphycnt0;
u32 dphycnt1;
u32 dphycnt2;
u32 dummy9[2]; /* 0xAC .. 0xB0 */
u32 sddrvcr0;
u32 dummy10[14]; /* 0xB8 .. 0xEC */
u32 dptdivcr0;
u32 dptdivcr1;
u32 dptdivcr2;
u32 dummy11; /* 0xFC */
u32 sdptcr0;
u32 sdptcr1;
u32 sdptcr2;
u32 sdptcr3; /* 0x10C */
u32 dummy12[145]; /* 0x110 .. 0x350 */
u32 dllcnt0; /* 0x354 */
u32 sbscmon0;
};
/* CPG */
struct sh73a0_sbsc_cpg {
u32 frqcra; /* 0x00 */
u32 frqcrb;
u32 vclkcr1;
u32 vclkcr2;
u32 zbckcr;
u32 flckcr;
u32 fsiackcr;
u32 vclkcr3;
u32 rtstbcr;
u32 systbcr;
u32 pll1cr;
u32 pll2cr;
u32 mstpsr0;
u32 dummy0; /* 0x34 */
u32 mstpsr1;
u32 mstpsr5;
u32 mstpsr2;
u32 dummy1; /* 0x44 */
u32 mstpsr3;
u32 mstpsr4;
u32 dummy2; /* 0x50 */
u32 astat;
u32 dvfscr0;
u32 dvfscr1;
u32 dsitckcr;
u32 dsi0pckcr;
u32 dsi1pckcr;
u32 dsi0phycr;
u32 dsi1phycr;
u32 sd0ckcr;
u32 sd1ckcr;
u32 sd2ckcr;
u32 subckcr;
u32 spuackcr;
u32 msuckcr;
u32 hsickcr;
u32 fsibckcr;
u32 spuvckcr;
u32 mfck1cr;
u32 mfck2cr;
u32 dummy3[8]; /* 0xA0 .. 0xBC */
u32 ckscr;
u32 dummy4; /* 0xC4 */
u32 pll1stpcr;
u32 mpmode;
u32 pllecr;
u32 dummy5; /* 0xD4 */
u32 pll0cr;
u32 pll3cr;
u32 dummy6; /* 0xE0 */
u32 frqcrd;
u32 dummyi7; /* 0xE8 */
u32 vrefcr;
u32 pll0stpcr;
u32 dummy8; /* 0xF4 */
u32 pll2stpcr;
u32 pll3stpcr;
u32 dummy9[4]; /* 0x100 .. 0x10c */
u32 rmstpcr0;
u32 rmstpcr1;
u32 rmstpcr2;
u32 rmstpcr3;
u32 rmstpcr4;
u32 rmstpcr5;
u32 dummy10[2]; /* 0x128 .. 0x12c */
u32 smstpcr0;
u32 smstpcr1;
u32 smstpcr2;
u32 smstpcr3;
u32 smstpcr4;
u32 smstpcr5;
u32 dummy11[2]; /* 0x148 .. 0x14c */
u32 cpgxxcs4;
u32 dummy12[7]; /* 0x154 .. 0x16c */
u32 dvfscr2;
u32 dvfscr3;
u32 dvfscr4;
u32 dvfscr5; /* 0x17C */
};
/* CPG SRCR part OK */
struct sh73a0_sbsc_cpg_srcr {
u32 srcr0;
u32 dummy0; /* 0xA4 */
u32 srcr1;
u32 dummy1; /* 0xAC */
u32 srcr2;
u32 dummy2; /* 0xB4 */
u32 srcr3;
u32 srcr4;
u32 dummy3; /* 0xC0 */
u32 srcr5;
};
/* BSC */
struct sh73a0_bsc {
u32 cmncr;
u32 cs0bcr;
u32 cs2bcr;
u32 dummy0; /* 0x0C */
u32 cs4bcr;
u32 cs5abcr;
u32 cs5bbcr;
u32 cs6abcr;
u32 cs6bbcr;
u32 cs0wcr;
u32 cs2wcr;
u32 dummy1; /* 0x2C */
u32 cs4wcr;
u32 cs5awcr;
u32 cs5bwcr;
u32 cs6awcr;
u32 cs6bwcr;
u32 rbwtcnt;
u32 busycr;
u32 dummy2; /* 0x5c */
u32 cs7abcr;
u32 cs7awcr;
u32 dummy3[2]; /* 0x68, 0x6C */
u32 bromtimcr;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */

29
arch/arm/include/asm/arch-rmobile/sys_proto.h Normal file
View File

@ -0,0 +1,29 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
struct rmobile_sysinfo {
char *board_string;
};
extern const struct rmobile_sysinfo sysinfo;
#endif

171
arch/arm/include/asm/arch-s3c24x0/gpio.h Normal file
View File

@ -0,0 +1,171 @@
/*
* Copyright (c) 2012.
*
* Gabriel Huau <contact@huau-gabriel.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _S3C24X0_GPIO_H_
#define _S3C24X0_GPIO_H_
enum s3c2440_gpio {
GPA0,
GPA1,
GPA2,
GPA3,
GPA4,
GPA5,
GPA6,
GPA7,
GPA8,
GPA9,
GPA10,
GPA11,
GPA12,
GPA13,
GPA14,
GPA15,
GPA16,
GPA17,
GPA18,
GPA19,
GPA20,
GPA21,
GPA22,
GPA23,
GPA24,
GPB0 = 32,
GPB1,
GPB2,
GPB3,
GPB4,
GPB5,
GPB6,
GPB7,
GPB8,
GPB9,
GPB10,
GPC0 = 64,
GPC1,
GPC2,
GPC3,
GPC4,
GPC5,
GPC6,
GPC7,
GPC8,
GPC9,
GPC10,
GPC11,
GPC12,
GPC13,
GPC14,
GPC15,
GPD0 = 96,
GPD1,
GPD2,
GPD3,
GPD4,
GPD5,
GPD6,
GPD7,
GPD8,
GPD9,
GPD10,
GPD11,
GPD12,
GPD13,
GPD14,
GPD15,
GPE0 = 128,
GPE1,
GPE2,
GPE3,
GPE4,
GPE5,
GPE6,
GPE7,
GPE8,
GPE9,
GPE10,
GPE11,
GPE12,
GPE13,
GPE14,
GPE15,
GPF0 = 160,
GPF1,
GPF2,
GPF3,
GPF4,
GPF5,
GPF6,
GPF7,
GPG0 = 192,
GPG1,
GPG2,
GPG3,
GPG4,
GPG5,
GPG6,
GPG7,
GPG8,
GPG9,
GPG10,
GPG11,
GPG12,
GPG13,
GPG14,
GPG15,
GPH0 = 224,
GPH1,
GPH2,
GPH3,
GPH4,
GPH5,
GPH6,
GPH7,
GPH8,
GPH9,
GPH10,
GPJ0 = 256,
GPJ1,
GPJ2,
GPJ3,
GPJ4,
GPJ5,
GPJ6,
GPJ7,
GPJ8,
GPJ9,
GPJ10,
GPJ11,
GPJ12,
};
#endif

200
arch/arm/include/asm/arch-s3c24x0/iomux.h Normal file
View File

@ -0,0 +1,200 @@
/*
* Copyright (c) 2012
*
* Gabriel Huau <contact@huau-gabriel.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _S3C24X0_IOMUX_H_
#define _S3C24X0_IOMUX_H_
enum s3c2440_iomux_func {
/* PORT A */
IOMUXA_ADDR0 = 1,
IOMUXA_ADDR16 = (1 << 1),
IOMUXA_ADDR17 = (1 << 2),
IOMUXA_ADDR18 = (1 << 3),
IOMUXA_ADDR19 = (1 << 4),
IOMUXA_ADDR20 = (1 << 5),
IOMUXA_ADDR21 = (1 << 6),
IOMUXA_ADDR22 = (1 << 7),
IOMUXA_ADDR23 = (1 << 8),
IOMUXA_ADDR24 = (1 << 9),
IOMUXA_ADDR25 = (1 << 10),
IOMUXA_ADDR26 = (1 << 11),
IOMUXA_nGCS1 = (1 << 12),
IOMUXA_nGCS2 = (1 << 13),
IOMUXA_nGCS3 = (1 << 14),
IOMUXA_nGCS4 = (1 << 15),
IOMUXA_nGCS5 = (1 << 16),
IOMUXA_CLE = (1 << 17),
IOMUXA_ALE = (1 << 18),
IOMUXA_nFWE = (1 << 19),
IOMUXA_nFRE = (1 << 20),
IOMUXA_nRSTOUT = (1 << 21),
IOMUXA_nFCE = (1 << 22),
/* PORT B */
IOMUXB_nXDREQ0 = (2 << 20),
IOMUXB_nXDACK0 = (2 << 18),
IOMUXB_nXDREQ1 = (2 << 16),
IOMUXB_nXDACK1 = (2 << 14),
IOMUXB_nXBREQ = (2 << 12),
IOMUXB_nXBACK = (2 << 10),
IOMUXB_TCLK0 = (2 << 8),
IOMUXB_TOUT3 = (2 << 6),
IOMUXB_TOUT2 = (2 << 4),
IOMUXB_TOUT1 = (2 << 2),
IOMUXB_TOUT0 = 2,
/* PORT C */
IOMUXC_VS7 = (2 << 30),
IOMUXC_VS6 = (2 << 28),
IOMUXC_VS5 = (2 << 26),
IOMUXC_VS4 = (2 << 24),
IOMUXC_VS3 = (2 << 22),
IOMUXC_VS2 = (2 << 20),
IOMUXC_VS1 = (2 << 18),
IOMUXC_VS0 = (2 << 16),
IOMUXC_LCD_LPCREVB = (2 << 14),
IOMUXC_LCD_LPCREV = (2 << 12),
IOMUXC_LCD_LPCOE = (2 << 10),
IOMUXC_VM = (2 << 8),
IOMUXC_VFRAME = (2 << 6),
IOMUXC_VLINE = (2 << 4),
IOMUXC_VCLK = (2 << 2),
IOMUXC_LEND = 2,
IOMUXC_I2SSDI = (3 << 8),
/* PORT D */
IOMUXD_VS23 = (2 << 30),
IOMUXD_VS22 = (2 << 28),
IOMUXD_VS21 = (2 << 26),
IOMUXD_VS20 = (2 << 24),
IOMUXD_VS19 = (2 << 22),
IOMUXD_VS18 = (2 << 20),
IOMUXD_VS17 = (2 << 18),
IOMUXD_VS16 = (2 << 16),
IOMUXD_VS15 = (2 << 14),
IOMUXD_VS14 = (2 << 12),
IOMUXD_VS13 = (2 << 10),
IOMUXD_VS12 = (2 << 8),
IOMUXD_VS11 = (2 << 6),
IOMUXD_VS10 = (2 << 4),
IOMUXD_VS9 = (2 << 2),
IOMUXD_VS8 = 2,
IOMUXD_nSS0 = (3 << 30),
IOMUXD_nSS1 = (3 << 28),
IOMUXD_SPICLK1 = (3 << 20),
IOMUXD_SPIMOSI1 = (3 << 18),
IOMUXD_SPIMISO1 = (3 << 16),
/* PORT E */
IOMUXE_IICSDA = (2 << 30),
IOMUXE_IICSCL = (2 << 28),
IOMUXE_SPICLK0 = (2 << 26),
IOMUXE_SPIMOSI0 = (2 << 24),
IOMUXE_SPIMISO0 = (2 << 22),
IOMUXE_SDDAT3 = (2 << 20),
IOMUXE_SDDAT2 = (2 << 18),
IOMUXE_SDDAT1 = (2 << 16),
IOMUXE_SDDAT0 = (2 << 14),
IOMUXE_SDCMD = (2 << 12),
IOMUXE_SDCLK = (2 << 10),
IOMUXE_I2SDO = (2 << 8),
IOMUXE_I2SDI = (2 << 6),
IOMUXE_CDCLK = (2 << 4),
IOMUXE_I2SSCLK = (2 << 2),
IOMUXE_I2SLRCK = 2,
IOMUXE_AC_SDATA_OUT = (3 << 8),
IOMUXE_AC_SDATA_IN = (3 << 6),
IOMUXE_AC_nRESET = (3 << 4),
IOMUXE_AC_BIT_CLK = (3 << 2),
IOMUXE_AC_SYNC = 3,
/* PORT F */
IOMUXF_EINT7 = (2 << 14),
IOMUXF_EINT6 = (2 << 12),
IOMUXF_EINT5 = (2 << 10),
IOMUXF_EINT4 = (2 << 8),
IOMUXF_EINT3 = (2 << 6),
IOMUXF_EINT2 = (2 << 4),
IOMUXF_EINT1 = (2 << 2),
IOMUXF_EINT0 = 2,
/* PORT G */
IOMUXG_EINT23 = (2 << 30),
IOMUXG_EINT22 = (2 << 28),
IOMUXG_EINT21 = (2 << 26),
IOMUXG_EINT20 = (2 << 24),
IOMUXG_EINT19 = (2 << 22),
IOMUXG_EINT18 = (2 << 20),
IOMUXG_EINT17 = (2 << 18),
IOMUXG_EINT16 = (2 << 16),
IOMUXG_EINT15 = (2 << 14),
IOMUXG_EINT14 = (2 << 12),
IOMUXG_EINT13 = (2 << 10),
IOMUXG_EINT12 = (2 << 8),
IOMUXG_EINT11 = (2 << 6),
IOMUXG_EINT10 = (2 << 4),
IOMUXG_EINT9 = (2 << 2),
IOMUXG_EINT8 = 2,
IOMUXG_TCLK1 = (3 << 22),
IOMUXG_nCTS1 = (3 << 20),
IOMUXG_nRTS1 = (3 << 18),
IOMUXG_SPICLK1 = (3 << 14),
IOMUXG_SPIMOSI1 = (3 << 12),
IOMUXG_SPIMISO1 = (3 << 10),
IOMUXG_LCD_PWRDN = (3 << 8),
IOMUXG_nSS1 = (3 << 6),
IOMUXG_nSS0 = (3 << 4),
/* PORT H */
IOMUXH_CLKOUT1 = (2 << 20),
IOMUXH_CLKOUT0 = (2 << 18),
IOMUXH_UEXTCLK = (2 << 16),
IOMUXH_RXD2 = (2 << 14),
IOMUXH_TXD2 = (2 << 12),
IOMUXH_RXD1 = (2 << 10),
IOMUXH_TXD1 = (2 << 8),
IOMUXH_RXD0 = (2 << 6),
IOMUXH_TXD0 = (2 << 4),
IOMUXH_nRTS0 = (2 << 2),
IOMUXH_nCTS0 = 2,
IOMUXH_nCTS1 = (3 << 14),
IOMUXH_nRTS1 = (3 << 12),
/* PORT J */
IOMUXJ_CAMRESET = (2 << 24),
IOMUXJ_CAMCLKOUT = (2 << 22),
IOMUXJ_CAMHREF = (2 << 20),
IOMUXJ_CAMVSYNC = (2 << 18),
IOMUXJ_CAMPCLK = (2 << 16),
IOMUXJ_CAMDATA7 = (2 << 14),
IOMUXJ_CAMDATA6 = (2 << 12),
IOMUXJ_CAMDATA5 = (2 << 10),
IOMUXJ_CAMDATA4 = (2 << 8),
IOMUXJ_CAMDATA3 = (2 << 6),
IOMUXJ_CAMDATA2 = (2 << 4),
IOMUXJ_CAMDATA1 = (2 << 2),
IOMUXJ_CAMDATA0 = 2
};
#endif

37
arch/arm/include/asm/arch-socfpga/reset_manager.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
struct socfpga_reset_manager {
u32 padding1;
u32 ctrl;
u32 padding2;
u32 padding3;
u32 mpu_mod_reset;
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
};
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif /* _RESET_MANAGER_H_ */

27
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SOCFPGA_BASE_ADDRS_H_
#define _SOCFPGA_BASE_ADDRS_H_
#define SOCFPGA_L3REGS_ADDRESS 0xff800000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */

26
arch/arm/include/asm/arch-socfpga/spl.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2012 Pavel Machek <pavel@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SOCFPGA_SPL_H_
#define _SOCFPGA_SPL_H_
/* Symbols from linker script */
extern char __malloc_start, __malloc_end, __stack_start;
#define BOOT_DEVICE_RAM 1
#endif

29
arch/arm/include/asm/arch-socfpga/timer.h Normal file
View File

@ -0,0 +1,29 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SOCFPGA_TIMER_H_
#define _SOCFPGA_TIMER_H_
struct socfpga_timer {
u32 load_val;
u32 curr_val;
u32 ctrl;
u32 eoi;
u32 int_stat;
};
#endif

26
arch/arm/include/asm/mach-types.h
View File

@ -1105,6 +1105,8 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_UBISYS_P9D_EVP 3493
#define MACH_TYPE_ATDGP318 3494
#define MACH_TYPE_OMAP5_SEVM 3777
#define MACH_TYPE_ARMADILLO_800EVA 3863
#define MACH_TYPE_KZM9G 4140
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@ -14222,6 +14224,30 @@ extern unsigned int __machine_arch_type;
# define machine_is_omap5_sevm() (0)
#endif
#ifdef CONFIG_MACH_ARMADILLO800EVA
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_ARMADILLO800EVA
# endif
# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
#else
# define machine_is_armadillo800eva() (0)
#endif
#ifdef CONFIG_MACH_KZM9G
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_KZM9G
# endif
# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G)
#else
# define machine_is_kzm9g() (0)
#endif
/*
* These have not yet been registered
*/

7
arch/arm/lib/bootm.c
View File

@ -69,8 +69,8 @@ void arch_lmb_reserve(struct lmb *lmb)
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 1K to be safe */
sp -= 1024;
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp,
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
}
@ -258,6 +258,9 @@ static int create_fdt(bootm_headers_t *images)
fixup_memory_node(*of_flat_tree);
fdt_fixup_ethernet(*of_flat_tree);
fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
#ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(*of_flat_tree, gd->bd);
#endif
return 0;
}

36
board/LaCie/common/common.c
View File

@ -13,10 +13,11 @@
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
#define MII_MARVELL_PHY_PAGE 22
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
@ -31,15 +32,44 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr)
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
if (miiphy_reset(name, phyaddr) == 0)
printf("88E1116 Initialized on %s\n", name);
}
void mv_phy_88e1318_init(const char *name, u16 phyaddr)
{
u16 reg;
if (miiphy_set_current_dev(name))
return;
/*
* Set control mode 4 for LED[0].
*/
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
miiphy_read(name, phyaddr, 16, &reg);
reg |= 0xf;
miiphy_write(name, phyaddr, 16, reg);
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
if (miiphy_reset(name, phyaddr) == 0)
printf("88E1318 Initialized on %s\n", name);
}
#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)

1
board/LaCie/common/common.h
View File

@ -12,6 +12,7 @@
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
void mv_phy_88e1116_init(const char *name, u16 phyaddr);
void mv_phy_88e1318_init(const char *name, u16 phyaddr);
#endif
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac);

162
board/LaCie/netspace_v2/kwbimage-ns2l.cfg Normal file
View File

@ -0,0 +1,162 @@
#
# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
#
# Based on Kirkwood support:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1B1B1B9B
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000618 # DDR Configuration register
# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x0000DDDD # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 10, Cs0size=512Mb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000632 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000004 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strenght reduced
# bit2: 1, DDR ODT control lsd enabled
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, enabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 1 , D2P Latency enabled
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
# bit11-10:1, DQ_ODTSel. ODT select turned on
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

4
board/LaCie/netspace_v2/netspace_v2.c
View File

@ -107,7 +107,11 @@ int misc_init_r(void)
/* Configure and initialize PHY */
void reset_phy(void)
{
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
mv_phy_88e1318_init("egiga0", 0);
#else
mv_phy_88e1116_init("egiga0", 8);
#endif
}
#endif

50
board/altera/socfpga_cyclone5/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := socfpga_cyclone5.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

80
board/altera/socfpga_cyclone5/socfpga_cyclone5.c Normal file
View File

@ -0,0 +1,80 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
puts("CPU : Altera SOCFPGA Platform\n");
return 0;
}
/*
* Print Board information
*/
int checkboard(void)
{
puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
return 0;
}
/*
* Initialization function which happen at early stage of c code
*/
int board_early_init_f(void)
{
return 0;
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
icache_enable();
return 0;
}
int misc_init_r(void)
{
return 0;
}
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
return 0;
}
#endif
/*
* DesignWare Ethernet initialization
*/
/* We know all the init functions have been run now */
int board_eth_init(bd_t *bis)
{
return 0;
}

46
board/atmark-techno/armadillo-800eva/Makefile Normal file
View File

@ -0,0 +1,46 @@
#
# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += armadillo-800eva.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

328
board/atmark-techno/armadillo-800eva/armadillo-800eva.c Normal file
View File

@ -0,0 +1,328 @@
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#define s_init_wait(cnt) \
({ \
volatile u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define USBCR1 0xE605810A
void s_init(void)
{
struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
/* Watchdog init */
writew(0xA500, &rwdt0->rwtcsra0);
writew(0xA500, &rwdt1->rwtcsra0);
/* CPG */
writel(0xFF800080, &cpg->rmstpcr4);
writel(0xFF800080, &cpg->smstpcr4);
/* USB clock */
writel(0x00000080, &cpg->usbckcr);
s_init_wait(1);
/* USBCR1 */
writew(0x0710, USBCR1);
/* FRQCR */
writel(0x00000000, &cpg->frqcrb);
writel(0x62030533, &cpg->frqcra);
writel(0x208A354E, &cpg->frqcrc);
writel(0x80331050, &cpg->frqcrb);
s_init_wait(1);
writel(0x00000000, &cpg->frqcrd);
s_init_wait(1);
/* SUBClk */
writel(0x0000010B, &cpg->subckcr);
/* PLL */
writel(0x00004004, &cpg->pllc01cr);
s_init_wait(1);
writel(0xa0000000, &cpg->pllc2cr);
s_init_wait(2);
/* BSC */
writel(0x0000001B, &bsc->cmncr);
writel(0x20000000, &dbsc->dbcmd);
writel(0x10009C40, &dbsc->dbcmd);
s_init_wait(1);
writel(0x00000007, &dbsc->dbkind);
writel(0x0E030A02, &dbsc->dbconf0);
writel(0x00000001, &dbsc->dbphytype);
writel(0x00000000, &dbsc->dbbl);
writel(0x00000006, &dbsc->dbtr0);
writel(0x00000005, &dbsc->dbtr1);
writel(0x00000000, &dbsc->dbtr2);
writel(0x00000006, &dbsc->dbtr3);
writel(0x00080006, &dbsc->dbtr4);
writel(0x00000015, &dbsc->dbtr5);
writel(0x0000000f, &dbsc->dbtr6);
writel(0x00000004, &dbsc->dbtr7);
writel(0x00000018, &dbsc->dbtr8);
writel(0x00000006, &dbsc->dbtr9);
writel(0x00000006, &dbsc->dbtr10);
writel(0x0000000F, &dbsc->dbtr11);
writel(0x0000000D, &dbsc->dbtr12);
writel(0x000000A0, &dbsc->dbtr13);
writel(0x000A0003, &dbsc->dbtr14);
writel(0x00000003, &dbsc->dbtr15);
writel(0x40005005, &dbsc->dbtr16);
writel(0x0C0C0000, &dbsc->dbtr17);
writel(0x00000200, &dbsc->dbtr18);
writel(0x00000040, &dbsc->dbtr19);
writel(0x00000001, &dbsc->dbrnk0);
writel(0x00000110, &dbsc->dbdficnt);
writel(0x00000101, &ddrp->funcctrl);
writel(0x00000001, &ddrp->dllctrl);
writel(0x00000186, &ddrp->zqcalctrl);
writel(0xB3440051, &ddrp->zqodtctrl);
writel(0x94449443, &ddrp->rdctrl);
writel(0x000000C0, &ddrp->rdtmg);
writel(0x00000101, &ddrp->fifoinit);
writel(0x02060506, &ddrp->outctrl);
writel(0x00004646, &ddrp->dqcalofs1);
writel(0x00004646, &ddrp->dqcalofs2);
writel(0x800000aa, &ddrp->dqcalexp);
writel(0x00000000, &ddrp->dllctrl);
writel(0x00000000, DDRPNCNT);
writel(0x0000000C, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00000002, DDRPNCNT);
writel(0x0000000C, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00000187, &ddrp->zqcalctrl);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00000010, &dbsc->dbdficnt);
writel(0x02060507, &ddrp->outctrl);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x21009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x00009C40, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x11000044, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x2A000000, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x2B000000, &dbsc->dbcmd);
readl(&dbsc->dbwait);
writel(0x29000004, &dbsc->dbcmd);
readl(&dbsc->dbwait);
writel(0x28001520, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x03000200, &dbsc->dbcmd);
readl(&dbsc->dbwait);
s_init_wait(1);
writel(0x000001FF, &dbsc->dbrfcnf0);
writel(0x00010C30, &dbsc->dbrfcnf1);
writel(0x00000000, &dbsc->dbrfcnf2);
writel(0x00000001, &dbsc->dbrfen);
writel(0x00000001, &dbsc->dbacen);
/* BSC */
writel(0x00410400, &bsc->cs0bcr);
writel(0x00410400, &bsc->cs2bcr);
writel(0x00410400, &bsc->cs5bbcr);
writel(0x02CB0400, &bsc->cs6abcr);
writel(0x00000440, &bsc->cs0wcr);
writel(0x00000440, &bsc->cs2wcr);
writel(0x00000240, &bsc->cs5bwcr);
writel(0x00000240, &bsc->cs6awcr);
writel(0x00000005, &bsc->rbwtcnt);
writel(0x00000002, &bsc->cs0wcr2);
writel(0x00000002, &bsc->cs2wcr2);
writel(0x00000002, &bsc->cs4wcr2);
}
#define GPIO_ICCR (0xE60581A0)
#define ICCR_15BIT (1 << 15) /* any time 1 */
#define IIC0_CONTA (1 << 7)
#define IIC0_CONTB (1 << 6)
#define IIC1_CONTA (1 << 5)
#define IIC1_CONTB (1 << 4)
#define IIC0_PS33E (1 << 1)
#define IIC1_PS33E (1 << 0)
#define GPIO_ICCR_DATA \
(ICCR_15BIT | \
IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
#define MSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define I2C0_MSTP116 (1 << 16)
#define MSTPCR3 0xE615013C
#define I2C1_MSTP323 (1 << 23)
#define GETHER_MSTP309 (1 << 9)
#define GPIO_SCIFA1_TXD (0xE60520C4)
#define GPIO_SCIFA1_RXD (0xE60520C3)
int board_early_init_f(void)
{
/* TMU */
clrbits_le32(MSTPCR1, TMU0_MSTP125);
/* GETHER */
clrbits_le32(MSTPCR3, GETHER_MSTP309);
/* I2C 0/1 */
clrbits_le32(MSTPCR1, I2C0_MSTP116);
clrbits_le32(MSTPCR3, I2C1_MSTP323);
/* SCIFA1 */
writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
/* IICCR */
writew(GPIO_ICCR_DATA, GPIO_ICCR);
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
/* adress of boot parameters */
gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7740_pinmux_init();
/* GETHER Enable */
gpio_request(GPIO_FN_ET_CRS, NULL);
gpio_request(GPIO_FN_ET_MDC, NULL);
gpio_request(GPIO_FN_ET_MDIO, NULL);
gpio_request(GPIO_FN_ET_TX_ER, NULL);
gpio_request(GPIO_FN_ET_RX_ER, NULL);
gpio_request(GPIO_FN_ET_ERXD0, NULL);
gpio_request(GPIO_FN_ET_ERXD1, NULL);
gpio_request(GPIO_FN_ET_ERXD2, NULL);
gpio_request(GPIO_FN_ET_ERXD3, NULL);
gpio_request(GPIO_FN_ET_TX_CLK, NULL);
gpio_request(GPIO_FN_ET_TX_EN, NULL);
gpio_request(GPIO_FN_ET_ETXD0, NULL);
gpio_request(GPIO_FN_ET_ETXD1, NULL);
gpio_request(GPIO_FN_ET_ETXD2, NULL);
gpio_request(GPIO_FN_ET_ETXD3, NULL);
gpio_request(GPIO_FN_ET_PHY_INT, NULL);
gpio_request(GPIO_FN_ET_COL, NULL);
gpio_request(GPIO_FN_ET_RX_DV, NULL);
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
gpio_direction_output(GPIO_PORT18, 1);
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
int board_late_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
}

4
board/atmel/at91sam9x5ek/at91sam9x5ek.c
View File

@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void)
csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
/* NAND flash on D16 */
csa |= AT91_MATRIX_NFD0_ON_D16;
/* Configure IO drive */
csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */

6
board/buffalo/lsxl/lsxl.c
View File

@ -195,9 +195,11 @@ int board_init(void)
static void check_power_switch(void)
{
if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
/* turn off HDD and USB power */
/* turn off fan, HDD and USB power */
kw_gpio_set_value(GPIO_HDD_POWER, 0);
kw_gpio_set_value(GPIO_USB_VBUS, 0);
kw_gpio_set_value(GPIO_FAN_HIGH, 1);
kw_gpio_set_value(GPIO_FAN_LOW, 1);
set_led(LED_OFF);
/* loop until released */
@ -207,6 +209,8 @@ static void check_power_switch(void)
/* turn power on again */
kw_gpio_set_value(GPIO_HDD_POWER, 1);
kw_gpio_set_value(GPIO_USB_VBUS, 1);
kw_gpio_set_value(GPIO_FAN_HIGH, 0);
kw_gpio_set_value(GPIO_FAN_LOW, 0);
set_led(LED_POWER_BLINKING);
}
}

32
board/davinci/ea20/ea20.c
View File

@ -176,6 +176,9 @@ int board_early_init_f(void)
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* Set DISP_ON high to enable LCD output*/
gpio_direction_output(97, 1);
/* Set the RESETOUTn low */
gpio_direction_output(111, 0);
@ -188,9 +191,6 @@ int board_early_init_f(void)
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
/* Set DISP_ON low to disable LCD output*/
gpio_direction_output(97, 0);
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
@ -250,15 +250,19 @@ int board_early_init_f(void)
writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
&davinci_syscfg_regs->mstpri[2]);
/* Set LCD_B_PWR low to power up LCD Backlight*/
gpio_set_value(102, 1);
/* Set DISP_ON low to disable LCD output*/
gpio_set_value(97, 1);
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_init(void)
{
/* arch number of the board */
@ -276,6 +280,9 @@ int board_init(void)
int board_late_init(void)
{
unsigned char buf[2];
int ret;
/* PinMux for HALTEN */
if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
return 1;
@ -283,8 +290,15 @@ int board_late_init(void)
/* Set HALTEN to high */
gpio_direction_output(134, 1);
setenv("stdout", "serial");
/* Set fixed contrast settings for LCD via I2C potentiometer */
buf[0] = 0x00;
buf[1] = 0xd7;
ret = i2c_write(0x2e, 6, 1, buf, 2);
if (ret)
puts("\nContrast Settings FAILED\n");
/* Set LCD_B_PWR high to power up LCD Backlight*/
gpio_set_value(102, 1);
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */

25
board/freescale/mx28evk/mx28evk.c
View File

@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_CMD_NET
#define MII_OPMODE_STRAP_OVERRIDE 0x16
#define MII_PHY_CTRL1 0x1e
#define MII_PHY_CTRL2 0x1f
int fecmxc_mii_postcall(int phy)
{
miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
if (phy == 3)
miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
return 0;
}
int board_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis)
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC0 mii postcall\n");
return ret;
}
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
puts("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC1 mii postcall\n");
return ret;
}
return ret;
}

8
board/freescale/mx51evk/mx51evk.c
View File

@ -60,6 +60,14 @@ int dram_init(void)
return 0;
}
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
static void setup_iomux_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |

44
board/friendlyarm/mini2440/Makefile Normal file
View File

@ -0,0 +1,44 @@
#
# (C) Copyright 2012
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := mini2440.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

134
board/friendlyarm/mini2440/mini2440.c Normal file
View File

@ -0,0 +1,134 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2009
* Michel Pollet <buserror@gmail.com>
*
* (C) Copyright 2012
* Gabriel Huau <contact@huau-gabriel.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/s3c2440.h>
#include <asm/arch/iomux.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <netdev.h>
#include "mini2440.h"
DECLARE_GLOBAL_DATA_PTR;
static inline void pll_delay(unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b" : "=r" (loops) : "0" (loops));
}
int board_early_init_f(void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
clk_power->clkdivn = CLKDIVN_VAL;
/* configure UPLL */
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
pll_delay(100);
/* configure MPLL */
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
pll_delay(10000);
return 0;
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* IOMUX Port H : UART Configuration */
gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
gpio_direction_output(GPH8, 0);
gpio_direction_output(GPH9, 0);
gpio_direction_output(GPH10, 0);
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
return 0;
}
int dram_init(void)
{
struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
/*
* Configuring bus width and timing
* Initialize clocks for each bank 0..5
* Bank 3 and 4 are used for DM9000
*/
writel(BANK_CONF, &memctl->bwscon);
writel(B0_CONF, &memctl->bankcon[0]);
writel(B1_CONF, &memctl->bankcon[1]);
writel(B2_CONF, &memctl->bankcon[2]);
writel(B3_CONF, &memctl->bankcon[3]);
writel(B4_CONF, &memctl->bankcon[4]);
writel(B5_CONF, &memctl->bankcon[5]);
/* Bank 6 and 7 are used for DRAM */
writel(SDRAM_64MB, &memctl->bankcon[6]);
writel(SDRAM_64MB, &memctl->bankcon[7]);
writel(MEM_TIMING, &memctl->refresh);
writel(BANKSIZE_CONF, &memctl->banksize);
writel(B6_MRSR, &memctl->mrsrb6);
writel(B7_MRSR, &memctl->mrsrb7);
gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_SIZE);
return 0;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_DRIVER_DM9000
return dm9000_initialize(bis);
#else
return 0;
#endif
}

144
board/friendlyarm/mini2440/mini2440.h Normal file
View File

@ -0,0 +1,144 @@
#ifndef __MINI2440_BOARD_CONF_H__
#define __MINI2440_BOARD_CONF_H__
/* PLL Parameters */
#define CLKDIVN_VAL 7
#define M_MDIV 0x7f
#define M_PDIV 0x2
#define M_SDIV 0x1
#define U_M_MDIV 0x38
#define U_M_PDIV 0x2
#define U_M_SDIV 0x2
/* BWSCON */
#define DW8 0x0
#define DW16 0x1
#define DW32 0x2
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW32)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16 + WAIT + UBLB)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/*
* Bank Configuration
*/
#define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0 /* 0clk */
#define B0_PMC 0x0 /* normal */
#define B1_Tacs 0x0
#define B1_Tcos 0x0
#define B1_Tacc 0x7
#define B1_Tcoh 0x0
#define B1_Tah 0x0
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0x0
#define B3_Tcos 0x3 /* 4clk */
#define B3_Tacc 0x7
#define B3_Tcoh 0x1 /* 1clk */
#define B3_Tah 0x3 /* 4clk */
#define B3_Tacp 0x0
#define B3_PMC 0x0
#define B4_Tacs 0x0
#define B4_Tcos 0x3
#define B4_Tacc 0x7
#define B4_Tcoh 0x1
#define B4_Tah 0x3
#define B4_Tacp 0x0
#define B4_PMC 0x0
#define B5_Tacs 0x0
#define B5_Tcos 0x0
#define B5_Tacc 0x7
#define B5_Tcoh 0x0
#define B5_Tah 0x0
#define B5_Tacp 0x0
#define B5_PMC 0x0
/*
* SDRAM Configuration
*/
#define SDRAM_MT 0x3 /* SDRAM */
#define SDRAM_Trcd 0x0 /* 2clk */
#define SDRAM_SCAN_9 0x1 /* 9bit */
#define SDRAM_SCAN_10 0x2 /* 10bit */
#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
/*
* Refresh Parameter
*/
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x1 /* 3clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x0 /* unused */
#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
/*
* MRSR Parameter
*/
#define BL 0x0
#define BT 0x0
#define CL 0x3 /* 3 clocks */
#define TM 0x0
#define WBL 0x0
/*
* BankSize Parameter
*/
#define BK76MAP 0x2 /* 128MB/128MB */
#define SCLK_EN 0x1 /* SCLK active */
#define SCKE_EN 0x1 /* SDRAM power down mode enable */
#define BURST_EN 0x1 /* Burst enable */
/*
* Register values
*/
#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
(B7_BWSCON<<28)))
#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
(Trc<<18) + (Tchr<<16) + REFCNT
#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
#define B6_MRSR (CL<<4)
#define B7_MRSR (CL<<4)
#endif

43
board/iomega/iconnect/Makefile Normal file
View File

@ -0,0 +1,43 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := iconnect.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

107
board/iomega/iconnect/iconnect.c Normal file
View File

@ -0,0 +1,107 @@
/*
* Copyright (C) 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <uboot@lukaperkov.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "iconnect.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
kw_config_gpio(ICONNECT_OE_VAL_LOW,
ICONNECT_OE_VAL_HIGH,
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn, /* Reset signal */
MPP7_GPO,
MPP8_TW_SDA, /* I2C */
MPP9_TW_SCK, /* I2C */
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Reset button */
MPP13_SD_CMD,
MPP14_SD_D0,
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GPIO,
MPP29_GPIO,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GE1_14,
MPP35_GPIO, /* OTB button */
MPP36_AUDIO_SPDIFI,
MPP37_AUDIO_SPDIFO,
MPP38_GPIO,
MPP39_TDM_SPI_CS0,
MPP40_TDM_SPI_SCK,
MPP41_GPIO, /* LED brightness */
MPP42_GPIO, /* LED power (blue) */
MPP43_GPIO, /* LED power (red) */
MPP44_GPIO, /* LED USB 1 */
MPP45_GPIO, /* LED USB 2 */
MPP46_GPIO, /* LED USB 3 */
MPP47_GPIO, /* LED USB 4 */
MPP48_GPIO, /* LED OTB */
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
return 0;
}

39
board/iomega/iconnect/iconnect.h Normal file
View File

@ -0,0 +1,39 @@
/*
* Copyright (C) 2009-2012
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
* Luka Perkov <uboot@lukaperkov.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ICONNECT_H
#define __ICONNECT_H
#define ICONNECT_OE_LOW (~(1 << 7))
#define ICONNECT_OE_HIGH (~(1 << 10))
#define ICONNECT_OE_VAL_LOW (0)
#define ICONNECT_OE_VAL_HIGH (1 << 10)
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* __ICONNECT_H */

165
board/iomega/iconnect/kwbimage.cfg Normal file
View File

@ -0,0 +1,165 @@
#
# (C) Copyright 2009-2012
# Wojciech Dubowik <wojciech.dubowik@neratec.com>
# Luka Perkov <uboot@lukaperkov.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
# bit23-14: 0x0,
# bit24: 0x1, enable exit self refresh mode on DDR access
# bit25: 0x1, required
# bit29-26: 0x0,
# bit31-30: 0x1,
DATA 0xffd01404 0x37543000 # DDR Controller Control Low
# bit4: 0x0, addr/cmd in smame cycle
# bit5: 0x0, clk is driven during self refresh, we don't care for APX
# bit6: 0x0, use recommended falling edge of clk for addr/cmd
# bit14: 0x0, input buffer always powered up
# bit18: 0x1, cpu lock transaction enabled
# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 0x3, required
# bit31: 0x0, no additional STARTBURST delay
DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11-8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: 0x0, required
DATA 0xffd01410 0x000000cc # DDR Address Control
# bit1-0: 00, Cs0width (x8)
# bit3-2: 11, Cs0size (1Gb)
# bit5-4: 00, Cs1width (x8)
# bit7-6: 11, Cs1size (1Gb)
# bit9-8: 00, Cs2width (nonexistent)
# bit11-10: 00, Cs2size (nonexistent)
# bit13-12: 00, Cs3width (nonexistent)
# bit15-14: 00, Cs3size (nonexistent)
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0x0, required
DATA 0xffd01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0x0, required
DATA 0xffd01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0x0, required
DATA 0xffd0141c 0x00000c52 # DDR Mode
# bit2-0: 0x2, BurstLen=2 required
# bit3: 0x0, BurstType=0 required
# bit6-4: 0x4, CL=5
# bit7: 0x0, TestMode=0 normal
# bit8: 0x0, DLL reset=0 normal
# bit11-9: 0x6, auto-precharge write recovery ????????????
# bit12: 0x0, PD must be zero
# bit31-13: 0x0, required
DATA 0xffd01420 0x00000040 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 0x0, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 0x0, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0x0, required
DATA 0xffd01424 0x0000f17f # DDR Controller Control High
# bit2-0: 0x7, required
# bit3: 0x1, MBUS Burst Chop disabled
# bit6-4: 0x7, required
# bit7: 0x0,
# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9: 0x0, no half clock cycle addition to dataout
# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
# bit15-12: 0xf, required
# bit31-16: 0x0, required
DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
# bit0: 0x1, Window enabled
# bit1: 0x0, Write Protect disabled
# bit3-2: 0x0, CS0 hit selected
# bit23-4: 0xfffff, required
# bit31-24: 0x0f, Size (i.e. 256MB)
DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
# bit3-2: 0x1, ODT1 active NEVER!
# bit31-4: 0x0, required
DATA 0xffd0149c 0x0000e803 # CPU ODT Control
DATA 0xffd01480 0x00000001 # DDR Initialization Control
# bit0: 0x1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

8
board/karo/tx25/lowlevel_init.S
View File

@ -66,6 +66,14 @@
write32 0x53f80064, 0x45600000
write32 0x53f80008, 0x20034000
/*
* PCDR2: NFC = 33.25 MHz
* This is required for the NAND Flash of this board, which is a Samsung
* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
* the NFC driver in symmetric (i.e. one-cycle) mode.
*/
write32 0x53f80020, 0x01010103
/*
* enable all implemented clocks in all three
* clock control registers

68
board/keymile/km_arm/km_arm.c
View File

@ -250,7 +250,8 @@ int board_early_init_f(void)
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
#endif
/* adjust SDRAM size for bank 0 */
kw_sdram_size_adjust(0);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
@ -365,6 +366,71 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#elif defined(CONFIG_KM_PIGGY4_88E6352)
#include <mv88e6352.h>
#if defined(CONFIG_KM_NUSA)
struct mv88e_sw_reg extsw_conf[] = {
/*
* port 0, PIGGY4, autoneg
* first the fix for the 1000Mbits Autoneg, this is from
* a Marvell errata, the regs are undocumented
*/
{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
{ PHY(0), PHY_STATUS, AN1000FIX },
{ PHY(0), PHY_PAGE, 0 },
/* now the real port and phy configuration */
{ PORT(0), PORT_PHY, NO_SPEED_FOR },
{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
{ PHY(0), PHY_1000_CTRL, NO_ADV },
{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
/* port 1, unused */
{ PORT(1), PORT_CTRL, PORT_DIS },
{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 2, unused */
{ PORT(2), PORT_CTRL, PORT_DIS },
{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 3, unused */
{ PORT(3), PORT_CTRL, PORT_DIS },
{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 4, ICNEV, SerDes, SGMII */
{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
{ PORT(4), PORT_PHY, SPEED_1000_FOR },
{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 5, CPU_RGMII */
{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
FULL_DPX_FOR | SPEED_1000_FOR },
{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/* port 6, unused, this port has no phy */
{ PORT(6), PORT_CTRL, PORT_DIS },
};
#else
struct mv88e_sw_reg extsw_conf[] = {};
#endif
void reset_phy(void)
{
#if defined(CONFIG_KM_MVEXTSW_ADDR)
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
ARRAY_SIZE(extsw_conf));
mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
#endif
}
#else
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)

50
board/kmc/kzm9g/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
# (C) Copyright 2012 Renesas Solutions Corp.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := kzm9g.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj) .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

377
board/kmc/kzm9g/kzm9g.c Normal file
View File

@ -0,0 +1,377 @@
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <netdev.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#define CS0BCR_D (0x06C00400)
#define CS4BCR_D (0x16c90400)
#define CS0WCR_D (0x55062C42)
#define CS4WCR_D (0x1e071dc3)
#define CMNCR_BROMMD0 (1 << 21)
#define CMNCR_BROMMD1 (1 << 22)
#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
#define VCLKCR1_D (0x27)
#define SMSTPCR1_CMT0 (1 << 24)
#define SMSTPCR1_I2C0 (1 << 16)
#define SMSTPCR3_USB (1 << 22)
#define PORT32CR (0xE6051020)
#define PORT33CR (0xE6051021)
#define PORT34CR (0xE6051022)
#define PORT35CR (0xE6051023)
static int cmp_loop(u32 *addr, u32 data, u32 cmp)
{
int err = -1;
int timeout = 100;
u32 value;
while (timeout > 0) {
value = readl(addr);
if ((value & data) == cmp) {
err = 0;
break;
}
timeout--;
}
return err;
}
/* SBSC Init function */
static void sbsc_init(struct sh73a0_sbsc *sbsc)
{
writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
writel(0x5, &sbsc->sdgencnt);
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
writel(0xacc90159, &sbsc->sdcr0);
writel(0x00010059, &sbsc->sdcr1);
writel(0x50874114, &sbsc->sdwcrc0);
writel(0x33199b37, &sbsc->sdwcrc1);
writel(0x008f2313, &sbsc->sdwcrc2);
writel(0x31020707, &sbsc->sdwcr00);
writel(0x0017040a, &sbsc->sdwcr01);
writel(0x31020707, &sbsc->sdwcr10);
writel(0x0017040a, &sbsc->sdwcr11);
writel(0x05555555, &sbsc->sddrvcr0);
writel(0x30000000, &sbsc->sdwcr2);
writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
writel(0x00002710, &sbsc->sdgencnt);
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
writel(0x0000003f, &sbsc->sdmracr0);
writel(0x0, SDMRA1A);
writel(0x000001f4, &sbsc->sdgencnt);
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
writel(0x0000ff0a, &sbsc->sdmracr0);
if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
writel(0x0, SDMRA3A);
else
writel(0x0, SDMRA3B);
writel(0x00000032, &sbsc->sdgencnt);
cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
writel(0x00002201, &sbsc->sdmracr0);
writel(0x0, SDMRA1A);
writel(0x00000402, &sbsc->sdmracr0);
writel(0x0, SDMRA1A);
writel(0x00000403, &sbsc->sdmracr0);
writel(0x0, SDMRA1A);
writel(0x0, SDMRA2A);
} else {
writel(0x00002201, &sbsc->sdmracr0);
writel(0x0, SDMRA1B);
writel(0x00000402, &sbsc->sdmracr0);
writel(0x0, SDMRA1B);
writel(0x00000403, &sbsc->sdmracr0);
writel(0x0, SDMRA1B);
writel(0x0, SDMRA2B);
}
writel(0x88800004, &sbsc->sdmrtmpcr);
writel(0x00000004, &sbsc->sdmrtmpmsk);
writel(0xa55a0032, &sbsc->rtcor);
writel(0xa55a000c, &sbsc->rtcorh);
writel(0xa55a2048, &sbsc->rtcsr);
writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
writel(0xfff20000, &sbsc->zqccr);
/* SCBS2 only */
if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
writel(0xa5390000, &sbsc->dphycnt1);
writel(0x00001200, &sbsc->dphycnt0);
writel(0x07ce0000, &sbsc->dphycnt1);
writel(0x00001247, &sbsc->dphycnt0);
cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
}
}
void s_init(void)
{
struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
struct sh73a0_hpb_bscr *hpb_bscr =
(struct sh73a0_hpb_bscr *)HPBSCR_BASE;
/* Watchdog init */
writew(0xA507, &rwdt->rwtcsra0);
/* Secure control register Init */
#define LIFEC_SEC_SRC_BIT (1 << 15)
writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
clrbits_le32(&cpg->smstpcr3, (1 << 15));
clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
clrbits_le32(&cpg->smstpcr2, (1 << 18));
clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
writel(0x0, &cpg->pllecr);
cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
writel(0x2D000000, &cpg->pll0cr);
writel(0x17100000, &cpg->pll1cr);
writel(0x96235880, &cpg->frqcrb);
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
writel(0xB, &cpg->flckcr);
clrbits_le32(&cpg->smstpcr0, (1 << 1));
clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
writel(0x0514, &hpb_bscr->smgpiotime);
writel(0x0514, &hpb_bscr->smcmt2time);
writel(0x0514, &hpb_bscr->smcpgtime);
writel(0x0514, &hpb_bscr->smsysctime);
writel(0x00092000, &cpg->dvfscr4);
writel(0x000000DC, &cpg->dvfscr5);
writel(0x0, &cpg->pllecr);
cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
/* FRQCR Init */
writel(0x0012453C, &cpg->frqcra);
writel(0x80331350, &cpg->frqcrb);
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
writel(0x00000B0B, &cpg->frqcrd);
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
/* Clock Init */
writel(0x00000003, PCLKCR);
writel(0x0000012F, &cpg->vclkcr1);
writel(0x00000119, &cpg->vclkcr2);
writel(0x00000119, &cpg->vclkcr3);
writel(0x00000002, &cpg->zbckcr);
writel(0x00000005, &cpg->flckcr);
writel(0x00000080, &cpg->sd0ckcr);
writel(0x00000080, &cpg->sd1ckcr);
writel(0x00000080, &cpg->sd2ckcr);
writel(0x0000003F, &cpg->fsiackcr);
writel(0x0000003F, &cpg->fsibckcr);
writel(0x00000080, &cpg->subckcr);
writel(0x0000000B, &cpg->spuackcr);
writel(0x0000000B, &cpg->spuvckcr);
writel(0x0000013F, &cpg->msuckcr);
writel(0x00000080, &cpg->hsickcr);
writel(0x0000003F, &cpg->mfck1cr);
writel(0x0000003F, &cpg->mfck2cr);
writel(0x00000107, &cpg->dsitckcr);
writel(0x00000313, &cpg->dsi0pckcr);
writel(0x0000130D, &cpg->dsi1pckcr);
writel(0x2A800E0E, &cpg->dsi0phycr);
writel(0x1E000000, &cpg->pll0cr);
writel(0x2D000000, &cpg->pll0cr);
writel(0x17100000, &cpg->pll1cr);
writel(0x27000080, &cpg->pll2cr);
writel(0x1D000000, &cpg->pll3cr);
writel(0x00080000, &cpg->pll0stpcr);
writel(0x000120C0, &cpg->pll1stpcr);
writel(0x00012000, &cpg->pll2stpcr);
writel(0x00000030, &cpg->pll3stpcr);
writel(0x0000000B, &cpg->pllecr);
cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
writel(0x000120F0, &cpg->dvfscr3);
writel(0x00000020, &cpg->mpmode);
writel(0x0000028A, &cpg->vrefcr);
writel(0xE4628087, &cpg->rmstpcr0);
writel(0xFFFFFFFF, &cpg->rmstpcr1);
writel(0x53FFFFFF, &cpg->rmstpcr2);
writel(0xFFFFFFFF, &cpg->rmstpcr3);
writel(0x00800D3D, &cpg->rmstpcr4);
writel(0xFFFFF3FF, &cpg->rmstpcr5);
writel(0x00000000, &cpg->smstpcr2);
writel(0x00040000, &cpg_srcr->srcr2);
clrbits_le32(&cpg->pllecr, (1 << 3));
cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
writel(0x00000001, &hpb->hpbctrl6);
cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
writel(0x00001414, &cpg->frqcrd);
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
writel(0x1d000000, &cpg->pll3cr);
setbits_le32(&cpg->pllecr, (1 << 3));
cmp_loop(&cpg->pllecr, 0x800, 0x800);
/* SBSC1 Init*/
sbsc_init(sbsc1);
/* SBSC2 Init*/
sbsc_init(sbsc2);
writel(0x00000b0b, &cpg->frqcrd);
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
writel(0xfffffffc, &cpg->cpgxxcs4);
}
int board_early_init_f(void)
{
struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
writel(CS0BCR_D, &bsc->cs0bcr);
writel(CS4BCR_D, &bsc->cs4bcr);
writel(CS0WCR_D, &bsc->cs0wcr);
writel(CS4WCR_D, &bsc->cs4wcr);
clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
writel(VCLKCR1_D, &cpg->vclkcr1);
/* Setup SCIF4 / workaround */
writeb(0x12, PORT32CR);
writeb(0x22, PORT33CR);
writeb(0x12, PORT34CR);
writeb(0x22, PORT35CR);
return 0;
}
int board_init(void)
{
sh73a0_pinmux_init();
/* SCIFA 4 */
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
/* Ethernet/SMSC */
gpio_request(GPIO_PORT224, NULL);
gpio_direction_input(GPIO_PORT224);
/* SMSC/USB */
gpio_request(GPIO_FN_CS4_, NULL);
/* MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
/* SDHI */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request(GPIO_PORT15, NULL);
gpio_direction_output(GPIO_PORT15, 1);
/* I2C */
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
#ifdef CONFIG_SMC911X
ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return ret;
}
void reset_cpu(ulong addr)
{
/* Soft Power On Reset */
writel((1 << 31), RESCNT2);
}

3
board/raidsonic/ib62x0/ib62x0.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
@ -41,6 +42,8 @@ int board_early_init_f(void)
IB62x0_OE_VAL_HIGH,
IB62x0_OE_LOW, IB62x0_OE_HIGH);
/* Set SATA activity LEDs to default off */
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,

4
board/raidsonic/ib62x0/ib62x0.h
View File

@ -37,4 +37,8 @@
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
/* SATAHC related */
#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C)
#define MVSATAHC_LED_POLARITY_CTRL (1 << 3)
#endif /* __IB62x0_H */

47
board/spear/x600/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
ifndef CONFIG_SPL_BUILD
COBJS := fpga.o $(BOARD).o
endif
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

280
board/spear/x600/fpga.c Normal file
View File

@ -0,0 +1,280 @@
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spartan3.h>
#include <command.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_ssp.h>
/*
* FPGA program pin configuration on X600:
*
* Only PROG and DONE are connected to GPIOs. INIT is not connected to the
* SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
* 16bit serial writes via this SSP port to write the data bits into the
* FPGA.
*/
#define CONFIG_SYS_FPGA_PROG 2
#define CONFIG_SYS_FPGA_DONE 3
/*
* Set the active-low FPGA reset signal.
*/
static void fpga_reset(int assert)
{
/*
* On x600 we have no means to toggle the FPGA reset signal
*/
debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
}
/*
* Set the FPGA's active-low SelectMap program line to the specified level
*/
static int fpga_pgm_fn(int assert, int flush, int cookie)
{
debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
return assert;
}
/*
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
static int fpga_init_fn(int cookie)
{
static int state;
debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
/*
* On x600, the FPGA INIT signal is not connected to the SoC.
* We can't read the INIT status. Let's return the "correct"
* INIT signal state generated via a local state-machine.
*/
if (++state == 1) {
return 1;
} else {
state = 0;
return 0;
}
}
/*
* Test the state of the active-high FPGA DONE pin
*/
static int fpga_done_fn(int cookie)
{
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
/*
* Wait for Tx-FIFO to become empty before looking for DONE
*/
while (!(readl(&ssp->sspsr) & SSPSR_TFE))
;
if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
return 1;
else
return 0;
}
/*
* FPGA pre-configuration function. Just make sure that
* FPGA reset is asserted to keep the FPGA from starting up after
* configuration.
*/
static int fpga_pre_config_fn(int cookie)
{
debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
fpga_reset(TRUE);
return 0;
}
/*
* FPGA post configuration function. Blip the FPGA reset line and then see if
* the FPGA appears to be running.
*/
static int fpga_post_config_fn(int cookie)
{
int rc = 0;
debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
fpga_reset(TRUE);
udelay(100);
fpga_reset(FALSE);
udelay(100);
return rc;
}
static int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
/*
* No dedicated clock signal on x600 (data & clock generated)
* in SSP interface. So we don't have to do anything here.
*/
return assert_clk;
}
static int fpga_wr_fn(int assert_write, int flush, int cookie)
{
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
static int count;
static u16 data;
/*
* First collect 16 bits of data
*/
data = data << 1;
if (assert_write)
data |= 1;
/*
* If 16 bits are not available, return for more bits
*/
count++;
if (count != 16)
return assert_write;
count = 0;
/*
* Wait for Tx-FIFO to become ready
*/
while (!(readl(&ssp->sspsr) & SSPSR_TNF))
;
/* Send 16 bits to FPGA via SSP bus */
writel(data, &ssp->sspdr);
return assert_write;
}
static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_init_fn,
fpga_done_fn,
fpga_wr_fn,
fpga_post_config_fn,
};
static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
};
/*
* Initialize the SelectMap interface. We assume that the mode and the
* initial state of all of the port pins have already been set!
*/
static void fpga_serialslave_init(void)
{
debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
}
static int expi_setup(int freq)
{
struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
pll2_m = (freq * 2) / 1000;
pll2_n = 15;
pll2_p = 1;
expi_x = 1;
expi_y = 2;
/*
* Disable reset, Low compression, Disable retiming, Enable Expi,
* Enable soft reset, DMA, PLL2, Internal
*/
writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
&misc->expi_clk_cfg);
/*
* 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
* Enable PLL2, Disable reset
*/
writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
/*
* Disable soft reset
*/
clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
return 0;
}
/*
* Initialize the fpga
*/
int x600_init_fpga(void)
{
struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/* Enable SSP2 clock */
writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
&misc->periph1_clken);
/* Set EXPI clock to 45 MHz */
expi_setup(45000);
/* Configure GPIO directions */
gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
gpio_direction_input(CONFIG_SYS_FPGA_DONE);
writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
writel(SSPCR1_SSE, &ssp->sspcr1);
/*
* Set lowest prescale divisor value (CPSDVSR) of 2 for max download
* speed.
*
* Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
* With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
*/
writel(2, &ssp->sspcpsr);
fpga_init();
fpga_serialslave_init();
debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
fpga_add(fpga_xilinx, &fpga[0]);
return 0;
}

23
board/spear/x600/fpga.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
int x600_init_fpga(void);

124
board/spear/x600/x600.c Normal file
View File

@ -0,0 +1,124 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nand.h>
#include <netdev.h>
#include <phy.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <linux/mtd/fsmc_nand.h>
#include "fpga.h"
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
int board_init(void)
{
/*
* X600 is equipped with an M41T82 RTC. This RTC has the
* HT bit (Halt Update), which needs to be cleared upon
* power-up. Otherwise the RTC is halted.
*/
rtc_reset();
return spear_board_init(MACH_TYPE_SPEAR600);
}
int board_late_init(void)
{
/*
* Monitor and env protection on by default
*/
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
2 * CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
/* Init FPGA subsystem */
x600_init_fpga();
return 0;
}
/*
* board_nand_init - Board specific NAND initialization
* @nand: mtd private chip structure
*
* Called by nand_init_chip to initialize the board specific functions
*/
void board_nand_init(void)
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
struct nand_chip *nand = &nand_chip[0];
if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
fsmc_nand_init(nand);
}
int designware_board_phy_init(struct eth_device *dev, int phy_addr,
int (*mii_write)(struct eth_device *, u8, u8, u16),
int dw_reset_phy(struct eth_device *))
{
/* Extended PHY control 1, select GMII */
mii_write(dev, phy_addr, 23, 0x0020);
/* Software reset necessary after GMII mode selction */
dw_reset_phy(dev);
/* Enable extended page register access */
mii_write(dev, phy_addr, 31, 0x0001);
/* 17e: Enhanced LED behavior, needs to be written twice */
mii_write(dev, phy_addr, 17, 0x09ff);
mii_write(dev, phy_addr, 17, 0x09ff);
/* 16e: Enhanced LED method select */
mii_write(dev, phy_addr, 16, 0xe0ea);
/* Disable extended page register access */
mii_write(dev, phy_addr, 31, 0x0000);
/* Enable clock output pin */
mii_write(dev, phy_addr, 18, 0x0049);
return 0;
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
PHY_INTERFACE_MODE_GMII) >= 0)
ret++;
return ret;
}

4
board/st-ericsson/snowball/snowball.c
View File

@ -253,6 +253,10 @@ int board_late_init(void)
if ((raise_ab8500_gpio16() < 0))
printf("error: cant' raise GPIO16\n");
/* empty UART RX FIFO */
while (tstc())
(void) getc();
return 0;
}

2
board/ti/beagle/beagle.c
View File

@ -488,7 +488,7 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_USB_EHCI
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{

54
board/xilinx/zynq/Makefile Normal file
View File

@ -0,0 +1,54 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS-y := board.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

54
board/xilinx/zynq/board.c Normal file
View File

@ -0,0 +1,54 @@
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
icache_enable();
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
#endif
return ret;
}
#endif
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}

10
boards.cfg
View File

@ -67,6 +67,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
@ -151,6 +152,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw
calimain arm arm926ejs calimain omicron davinci
pogo_e02 arm arm926ejs - cloudengines kirkwood
dns325 arm arm926ejs - d-link kirkwood
iconnect arm arm926ejs - iomega kirkwood
lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
@ -159,9 +161,12 @@ kmnusa arm arm926ejs km_arm keymile
mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
dreamplug arm arm926ejs - Marvell kirkwood
guruplug arm arm926ejs - Marvell kirkwood
@ -213,6 +218,7 @@ spear600 arm arm926ejs spear600 spear
spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
x600 arm arm926ejs - spear spear x600
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
@ -272,6 +278,10 @@ ventana arm armv7:arm720t ventana nvidia
whistler arm armv7:arm720t whistler nvidia tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
snowball arm armv7 snowball st-ericsson u8500
kzm9g arm armv7 kzm9g kmc rmobile
armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
zynq arm armv7 zynq xilinx zynq
socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8

4
common/Makefile
View File

@ -199,6 +199,10 @@ endif
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
endif
COBJS-y += console.o
COBJS-y += dlmalloc.o

8
common/cmd_nvedit.c
View File

@ -103,6 +103,7 @@ int get_env_id(void)
return env_id;
}
#ifndef CONFIG_SPL_BUILD
/*
* Command interface: print one or all environment variables
*
@ -196,6 +197,7 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
return rcode;
}
#endif
#endif /* CONFIG_SPL_BUILD */
/*
* Perform consistency checking before setting, replacing, or deleting an
@ -437,6 +439,7 @@ int setenv_addr(const char *varname, const void *addr)
return setenv(varname, str);
}
#ifndef CONFIG_SPL_BUILD
int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
@ -536,6 +539,7 @@ int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return setenv(argv[1], buffer);
}
#endif /* CONFIG_CMD_EDITENV */
#endif /* CONFIG_SPL_BUILD */
/*
* Look up variable from environment,
@ -621,6 +625,7 @@ ulong getenv_ulong(const char *name, int base, ulong default_val)
return str ? simple_strtoul(str, NULL, base) : default_val;
}
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -635,6 +640,7 @@ U_BOOT_CMD(
""
);
#endif
#endif /* CONFIG_SPL_BUILD */
/*
@ -656,6 +662,7 @@ int envmatch(uchar *s1, int i2)
return -1;
}
#ifndef CONFIG_SPL_BUILD
static int do_env_default(cmd_tbl_t *cmdtp, int __flag,
int argc, char * const argv[])
{
@ -1114,3 +1121,4 @@ U_BOOT_CMD_COMPLETE(
var_complete
);
#endif
#endif /* CONFIG_SPL_BUILD */

Some files were not shown because too many files have changed in this diff Show More