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Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

This commit is contained in:
Tom Rini 2016-01-27 15:05:12 -05:00
parent b20c38a973 f36919a813
commit 19bde0316f
108 changed files with 1191 additions and 1290 deletions
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3
.mailmap
View File

@ -21,6 +21,9 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Markus Klotzbuecher <mk@denx.de>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Ricardo Ribalda <ricardo.ribalda@uam.es>
Ricardo Ribalda <ricardo.ribalda@gmail.com>
Sandeep Paulraj <s-paulraj@ti.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Stefan Roese <stroese>

6
arch/arm/Kconfig
View File

@ -558,15 +558,15 @@ config ARCH_ZYNQ
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
select SPL_OF_CONTROL
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select SPL_DM
select SPL_DM if SPL
select DM_MMC
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
select SPL_SEPARATE_BSS
select SPL_SEPARATE_BSS if SPL
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"

4
arch/arm/cpu/armv8/zynqmp/Kconfig
View File

@ -20,10 +20,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
config SECURE_IOU
bool "Configure ZynqMP secure IOU"
default n
config ZYNQMP_USB
bool "Configure ZynqMP USB"

20
arch/arm/cpu/armv8/zynqmp/clk.c
View File

@ -21,9 +21,27 @@ unsigned long get_uart_clk(int dev_id)
return 48000;
case ZYNQMP_CSU_VERSION_EP108:
return 25000000;
case ZYNQMP_CSU_VERSION_QEMU:
return 133000000;
}
return 133000000;
return 100000000;
}
unsigned long zynqmp_get_system_timer_freq(void)
{
u32 ver = zynqmp_get_silicon_version();
switch (ver) {
case ZYNQMP_CSU_VERSION_VELOCE:
return 10000;
case ZYNQMP_CSU_VERSION_EP108:
return 4000000;
case ZYNQMP_CSU_VERSION_QEMU:
return 50000000;
}
return 100000000;
}
#ifdef CONFIG_CLOCKS

18
arch/arm/cpu/armv8/zynqmp/cpu.c
View File

@ -15,8 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
static unsigned int zynqmp_get_silicon_version_secure(void)
{
u32 ver;
ver = readl(&csu_base->version);
ver &= ZYNQMP_SILICON_VER_MASK;
ver >>= ZYNQMP_SILICON_VER_SHIFT;
return ver;
}
unsigned int zynqmp_get_silicon_version(void)
{
if (current_el() == 3)
return zynqmp_get_silicon_version_secure();
gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) {
@ -24,9 +38,11 @@ unsigned int zynqmp_get_silicon_version(void)
return ZYNQMP_CSU_VERSION_VELOCE;
case 50000000:
return ZYNQMP_CSU_VERSION_QEMU;
case 4000000:
return ZYNQMP_CSU_VERSION_EP108;
}
return ZYNQMP_CSU_VERSION_EP108;
return ZYNQMP_CSU_VERSION_SILICON;
}
#ifndef CONFIG_SYS_DCACHE_OFF

10
arch/arm/dts/zynq-7000.dtsi
View File

@ -234,7 +234,7 @@
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
} ;
};
sdhci1: sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
@ -244,7 +244,7 @@
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
} ;
};
slcr: slcr@f8000000 {
#address-cells = <1>;
@ -326,11 +326,11 @@
scutimer: timer@f8f00600 {
interrupt-parent = <&intc>;
interrupts = < 1 13 0x301 >;
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = < 0xf8f00600 0x20 >;
reg = <0xf8f00600 0x20>;
clocks = <&clkc 4>;
} ;
};
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";

5
arch/arm/dts/zynq-zc770-xm010.dts
View File

@ -21,9 +21,8 @@
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
bootargs = "root=/dev/ram rw earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {

17
arch/arm/dts/zynq-zc770-xm011.dts
View File

@ -18,9 +18,8 @@
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
bootargs = "root=/dev/ram rw earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -34,12 +33,6 @@
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&can0 {
status = "okay";
};
@ -54,6 +47,12 @@
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";

17
arch/arm/dts/zynq-zc770-xm012.dts
View File

@ -20,9 +20,8 @@
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
bootargs = "root=/dev/ram rw earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -31,12 +30,6 @@
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&can1 {
status = "okay";
};
@ -61,6 +54,12 @@
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";

35
arch/arm/dts/zynq-zc770-xm013.dts
View File

@ -20,9 +20,8 @@
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart0;
stdout-path = &uart0;
bootargs = "root=/dev/ram rw earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -31,21 +30,6 @@
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
eeprom: at25@0 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
compatible = "atmel,at25";
reg = <2>;
spi-max-frequency = <1000000>;
};
};
&can1 {
status = "okay";
};
@ -74,6 +58,21 @@
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
eeprom: at25@0 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
compatible = "atmel,at25";
reg = <2>;
spi-max-frequency = <1000000>;
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";

2
arch/arm/dts/zynqmp-ep108.dts
View File

@ -41,7 +41,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0{
phy0: phy@0 {
reg = <0>;
max-speed = <100>;
};

6
arch/arm/dts/zynqmp.dtsi
View File

@ -520,7 +520,7 @@
};
uart0: serial@ff000000 {
compatible = "cdns,uart-r1p8";
compatible = "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
@ -529,7 +529,7 @@
};
uart1: serial@ff010000 {
compatible = "cdns,uart-r1p8";
compatible = "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
@ -559,7 +559,7 @@
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 52 1>;
interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x1000>;
timeout-sec = <10>;
};

1
arch/arm/include/asm/arch-zynqmp/clk.h
View File

@ -9,5 +9,6 @@
#define _ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_id);
unsigned long zynqmp_get_system_timer_freq(void);
#endif /* _ASM_ARCH_CLK_H_ */

30
arch/arm/include/asm/arch-zynqmp/hardware.h
View File

@ -41,11 +41,8 @@ struct crlapb_regs {
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
#if defined(CONFIG_SECURE_IOU)
#define ZYNQMP_IOU_SCNTR 0xFF260000
#else
#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
#define ZYNQMP_IOU_SCNTR 0xFF250000
#endif
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@ -57,9 +54,21 @@ struct iou_scntr {
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
struct iou_scntr_secure {
u32 counter_control_register;
u32 reserved0[7];
u32 base_frequency_id_register;
};
#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
#define SD_MODE 0x00000003
#define QSPI_MODE_24BIT 0x00000001
#define QSPI_MODE_32BIT 0x00000002
#define SD_MODE 0x00000003 /* sd 0 */
#define SD_MODE1 0x00000005 /* sd 1 */
#define NAND_MODE 0x00000004
#define EMMC_MODE 0x00000006
#define JTAG_MODE 0x00000000
@ -106,9 +115,20 @@ struct apu_regs {
#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
/* Board version value */
#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
#define ZYNQMP_CSU_VERSION_SILICON 0x0
#define ZYNQMP_CSU_VERSION_EP108 0x1
#define ZYNQMP_CSU_VERSION_VELOCE 0x2
#define ZYNQMP_CSU_VERSION_QEMU 0x3
#define ZYNQMP_SILICON_VER_MASK 0xF000
#define ZYNQMP_SILICON_VER_SHIFT 12
struct csu_regs {
u32 reserved0[17];
u32 version;
};
#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
#endif /* _ASM_ARCH_HARDWARE_H */

2
arch/arm/mach-zynq/ddrc.c
View File

@ -42,8 +42,6 @@ void zynq_ddrc_init(void)
*/
/* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
gd->ram_size /= 2;
} else {
puts("ECC disabled ");
}

1
arch/microblaze/Kconfig
View File

@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
select SUPPORT_SPL
select OF_CONTROL
select DM
select DM_SERIAL
endchoice

2
arch/microblaze/cpu/Makefile
View File

@ -7,5 +7,5 @@
extra-y = start.o
obj-y = irq.o
obj-y += cpu.o interrupts.o cache.o exception.o timer.o
obj-y += interrupts.o cache.o exception.o timer.o
obj-$(CONFIG_SPL_BUILD) += spl.o

9
arch/microblaze/cpu/cpu.c
View File

@ -1,9 +0,0 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* EMPTY FILE */

4
arch/microblaze/cpu/start.S
View File

@ -155,6 +155,10 @@ clear_bss:
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
#ifdef CONFIG_DEBUG_UART
bralid r15, debug_uart_init
nop
#endif
#ifndef CONFIG_SPL_BUILD
or r5, r0, r0 /* flags - empty */
addi r31, r0, _gd

20
arch/powerpc/cpu/ppc4xx/Kconfig
View File

@ -55,12 +55,6 @@ config TARGET_YOSEMITE
config TARGET_YUCCA
bool "Support yucca"
config TARGET_FX12MM
bool "Support fx12mm"
config TARGET_V5FX30TEVAL
bool "Support v5fx30teval"
config TARGET_CPCI2DP
bool "Support CPCI2DP"
@ -115,14 +109,19 @@ config TARGET_PIP405
config TARGET_XPEDITE1000
bool "Support xpedite1000"
config TARGET_ML507
bool "Support ml507"
config TARGET_XILINX_PPC405_GENERIC
bool "Support xilinx-ppc405-generic"
select SUPPORT_SPL
select OF_CONTROL
select DM
select DM_SERIAL
config TARGET_XILINX_PPC440_GENERIC
bool "Support xilinx-ppc440-generic"
select SUPPORT_SPL
select OF_CONTROL
select DM
select DM_SERIAL
endchoice
@ -139,8 +138,6 @@ source "board/amcc/sequoia/Kconfig"
source "board/amcc/walnut/Kconfig"
source "board/amcc/yosemite/Kconfig"
source "board/amcc/yucca/Kconfig"
source "board/avnet/fx12mm/Kconfig"
source "board/avnet/v5fx30teval/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
@ -158,7 +155,6 @@ source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"
source "board/xilinx/ml507/Kconfig"
source "board/xilinx/ppc405-generic/Kconfig"
source "board/xilinx/ppc440-generic/Kconfig"

2
arch/powerpc/cpu/ppc4xx/interrupts.c
View File

@ -9,7 +9,7 @@
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* Work supported by Qtechnology (htpp://qtec.com)
*
* SPDX-License-Identifier: GPL-2.0+

2
arch/powerpc/cpu/ppc4xx/uic.c
View File

@ -9,7 +9,7 @@
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
* (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* Work supported by Qtechnology (htpp://qtec.com)
*
* SPDX-License-Identifier: GPL-2.0+

2
arch/powerpc/cpu/ppc4xx/xilinx_irq.c
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
* SPDX-License-Identifier: GPL-2.0+

2
arch/powerpc/dts/Makefile
View File

@ -3,6 +3,8 @@
#
dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
dtb-$(CONFIG_TARGET_XILINX_PPC440_GENERIC) += xilinx-ppc440-generic.dtb
dtb-$(CONFIG_TARGET_XILINX_PPC405_GENERIC) += xilinx-ppc405-generic.dtb
targets += $(dtb-y)

15
arch/powerpc/dts/xilinx-ppc405-generic.dts Normal file
View File

@ -0,0 +1,15 @@
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
};
uart0: serial@84000000 {
compatible = "xlnx,xps-uartlite-1.00.a";
interrupts = <0 0>;
reg = <0x84000000 0x10000>;
};
} ;

15
arch/powerpc/dts/xilinx-ppc440-generic.dts Normal file
View File

@ -0,0 +1,15 @@
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
};
uart0: serial@8b000000 {
compatible = "xlnx,xps-uartlite-1.00.a";
interrupts = <0 0>;
reg = <0x8b000000 0x10000>;
};
} ;

2
arch/powerpc/include/asm/interrupt.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
*

2
arch/powerpc/include/asm/xilinx_irq.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
* SPDX-License-Identifier: GPL-2.0+

12
board/avnet/fx12mm/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_FX12MM
config SYS_BOARD
default "fx12mm"
config SYS_VENDOR
default "avnet"
config SYS_CONFIG_NAME
default "fx12mm"
endif

7
board/avnet/fx12mm/MAINTAINERS
View File

@ -1,7 +0,0 @@
FX12MM BOARD
M: Georg Schardt <schardt@team-ctech.de>
S: Maintained
F: board/avnet/fx12mm/
F: include/configs/fx12mm.h
F: configs/fx12mm_defconfig
F: configs/fx12mm_flash_defconfig

11
board/avnet/fx12mm/Makefile
View File

@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += fx12mm.o
include $(srctree)/board/xilinx/ppc405-generic/Makefile

34
board/avnet/fx12mm/fx12mm.c
View File

@ -1,34 +0,0 @@
/*
* (C) Copyright 2008
*
* Author: Xilinx Inc.
*
* Modified by:
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
char buf[64];
int i;
int l = getenv_f("serial#", buf, sizeof(buf));
if (l < 0) {
printf("Avnet Virtex4 FX12 with no serial #");
} else {
printf("Avnet Virtex4 FX12 Minimodul # ");
for (i = 0; i < l; ++i) {
if (buf[i] == ' ')
break;
putc(buf[i]);
}
}
putc('\n');
return 0;
}

35
board/avnet/fx12mm/xparameters.h
View File

@ -1,35 +0,0 @@
/*
* (C) Copyright 2008
*
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* CAUTION: This file is based on the xparameters.h automatically
* generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
*/
#ifndef __XPARAMETER_H__
#define __XPARAMETER_H__
/* RS232 */
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
/* INT_C */
#define XPAR_XPS_INTC_0_DEVICE_ID 0
#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
/* CPU core clock */
#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
/* RAM */
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
/* FLASH */
#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
#endif

12
board/avnet/v5fx30teval/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_V5FX30TEVAL
config SYS_BOARD
default "v5fx30teval"
config SYS_VENDOR
default "avnet"
config SYS_CONFIG_NAME
default "v5fx30teval"
endif

7
board/avnet/v5fx30teval/MAINTAINERS
View File

@ -1,7 +0,0 @@
V5FX30TEVAL BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
S: Maintained
F: board/avnet/v5fx30teval/
F: include/configs/v5fx30teval.h
F: configs/v5fx30teval_defconfig
F: configs/v5fx30teval_flash_defconfig

11
board/avnet/v5fx30teval/Makefile
View File

@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += v5fx30teval.o
include $(srctree)/board/xilinx/ppc440-generic/Makefile

17
board/avnet/v5fx30teval/v5fx30teval.c
View File

@ -1,17 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Avnet Virtex 5 FX30 Evaluation Board\n");
return 0;
}

22
board/avnet/v5fx30teval/xparameters.h
View File

@ -1,22 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters.h by Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

41
board/xilinx/microblaze-generic/microblaze-generic.c
View File

@ -12,7 +12,6 @@
#include <common.h>
#include <config.h>
#include <fdtdec.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
static int reset_pin = -1;
#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
ulong ram_base;
void dram_init_banksize(void)
@ -58,14 +56,6 @@ int dram_init(void)
return 0;
};
#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
int gpio_init (void)
static int gpio_init(void)
{
#ifdef CONFIG_XILINX_GPIO
reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
@ -96,32 +86,9 @@ int gpio_init (void)
return 0;
}
void board_init(void)
int board_late_init(void)
{
gpio_init();
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR)
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
return ret;
return 0;
}

21
board/xilinx/microblaze-generic/xparameters.h
View File

@ -28,15 +28,6 @@
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is RS232_Uart */
#define XILINX_UARTLITE_BASEADDR 0x40600000
#define XILINX_UARTLITE_BAUDRATE 115200
/* IIC pheriphery is IIC_EEPROM */
#define XILINX_IIC_0_BASEADDR 0x40800000
#define XILINX_IIC_0_FREQ 100000
#define XILINX_IIC_0_BIT 0
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
@ -44,18 +35,6 @@
#define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is DDR_SDRAM_64Mx32 */
#define XILINX_RAM_START 0x28000000
#define XILINX_RAM_SIZE 0x04000000
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XILINX_EMACLITE_BASEADDR 0x40C00000
/* Watchdog IP is wxi_timebase_wdt_0 */
#define XILINX_WATCHDOG_BASEADDR 0x50000000
#define XILINX_WATCHDOG_IRQ 1

12
board/xilinx/ml507/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_ML507
config SYS_BOARD
default "ml507"
config SYS_VENDOR
default "xilinx"
config SYS_CONFIG_NAME
default "ml507"
endif

7
board/xilinx/ml507/MAINTAINERS
View File

@ -1,7 +0,0 @@
ML507 BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
S: Maintained
F: board/xilinx/ml507/
F: include/configs/ml507.h
F: configs/ml507_defconfig
F: configs/ml507_flash_defconfig

11
board/xilinx/ml507/Makefile
View File

@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ml507.o
include $(srctree)/board/xilinx/ppc440-generic/Makefile

17
board/xilinx/ml507/ml507.c
View File

@ -1,17 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Xilinx ML507 Board\n");
return 0;
}

23
board/xilinx/ml507/xparameters.h
View File

@ -1,23 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

2
board/xilinx/ppc405-generic/MAINTAINERS
View File

@ -1,5 +1,5 @@
PPC405-GENERIC BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc405-generic/
F: include/configs/xilinx-ppc405-generic.h

4
board/xilinx/ppc405-generic/Makefile
View File

@ -3,10 +3,10 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
obj-y += xilinx_ppc405_generic.o

31
board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
@ -10,39 +10,32 @@
#include <common.h>
#include <asm/processor.h>
ulong __get_PCI_freq(void)
ulong get_PCI_freq(void)
{
return 0;
}
ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
int checkboard(void)
{
puts("Xilinx PPC405 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
void get_sys_info(sys_info_t *sys_info)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sys_info->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

7
board/xilinx/ppc405-generic/xparameters.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
@ -14,12 +14,11 @@
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_SPI_0_BASEADDR 0x83400000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif

2
board/xilinx/ppc440-generic/MAINTAINERS
View File

@ -1,5 +1,5 @@
PPC440-GENERIC BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc440-generic/
F: include/configs/xilinx-ppc440-generic.h

6
board/xilinx/ppc440-generic/Makefile
View File

@ -3,11 +3,11 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
extra-y += ../../xilinx/ppc440-generic/init.o
obj-y += xilinx_ppc440_generic.o
extra-y += init.o

2
board/xilinx/ppc440-generic/init.S
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+

49
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
@ -8,34 +8,51 @@
#include <config.h>
#include <common.h>
#include <netdev.h>
#include <asm/processor.h>
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
int checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
void get_sys_info(sys_info_t *sys_info)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sys_info->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
puts("Init xilinx temac\n");
#ifdef XPAR_LLTEMAC_0_BASEADDR
ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
#endif
#ifdef XPAR_LLTEMAC_1_BASEADDR
ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
#endif
return ret;
}

15
board/xilinx/ppc440-generic/xparameters.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
@ -12,12 +12,15 @@
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_INTC_0_BASEADDR 0x87000000
#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
#define XPAR_LLTEMAC_0_BASEADDR 0x83000000
#define XPAR_LLTEMAC_1_BASEADDR 0x83000040
#endif

26
board/xilinx/zynq/board.c
View File

@ -8,7 +8,6 @@
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@ -94,34 +93,11 @@ int board_late_init(void)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tXilinx Zynq\n");
puts("Board: Xilinx Zynq\n");
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
return ret;
}
int dram_init(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)

49
board/xilinx/zynqmp/zynqmp.c
View File

@ -9,6 +9,7 @@
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
@ -28,10 +29,18 @@ int board_early_init_r(void)
{
u32 val;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
if (current_el() == 3) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
/* Program freq register in System counter and enable system counter */
writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
@ -48,11 +57,6 @@ int dram_init(void)
return 0;
}
int timer_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
}
@ -73,11 +77,36 @@ int board_late_init(void)
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
puts("Bootmode: ");
switch (bootmode) {
case SD_MODE:
case JTAG_MODE:
puts("JTAG_MODE\n");
setenv("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
setenv("modeboot", "qspiboot");
puts("QSPI_MODE\n");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE:
puts("SD_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE1:
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
setenv("sdbootdev", "1");
#endif
setenv("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
setenv("modeboot", "nandboot");
break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
@ -88,7 +117,7 @@ int board_late_init(void)
int checkboard(void)
{
puts("Board:\tXilinx ZynqMP\n");
puts("Board: Xilinx ZynqMP\n");
return 0;
}

2
cmd/bdinfo.c
View File

@ -205,7 +205,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_num("sram start ", (ulong)bd->bi_sramstart);
print_num("sram size ", (ulong)bd->bi_sramsize);
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
print_eths();
#endif
printf("baudrate = %u bps\n", gd->baudrate);

8
cmd/fpga.c
View File

@ -86,7 +86,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
case 3: /* fpga <op> <dev | data addr> */
dev = (int)simple_strtoul(argv[2], NULL, 16);
@ -107,13 +107,13 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
} else
#endif
{
fpga_data = (void *)dev;
fpga_data = (void *)(uintptr_t)dev;
debug("* fpga: cmdline image addr = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%x\n",
__func__, (uint)fpga_data);
debug("%s: fpga_data = 0x%lx\n",
__func__, (ulong)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}

10
configs/fx12mm_defconfig
View File

@ -1,10 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_FX12MM=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o"
CONFIG_SYS_PROMPT="FX12MM:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y

9
configs/fx12mm_flash_defconfig
View File

@ -1,9 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_FX12MM=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_NS16550=y

14
configs/microblaze-generic_defconfig
View File

@ -1,10 +1,24 @@
CONFIG_MICROBLAZE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_DM=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_SYS_TEXT_BASE=0x29000000
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
CONFIG_DM_ETH=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_EMACLITE=y
CONFIG_SYS_NS16550=y
CONFIG_XILINX_UARTLITE=y

9
configs/ml507_defconfig
View File

@ -1,9 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ML507=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
CONFIG_SYS_PROMPT="ml507:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

8
configs/ml507_flash_defconfig
View File

@ -1,8 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ML507=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

9
configs/v5fx30teval_defconfig
View File

@ -1,9 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_V5FX30TEVAL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
CONFIG_SYS_PROMPT="v5fx30t:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

8
configs/v5fx30teval_flash_defconfig
View File

@ -1,8 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_V5FX30TEVAL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

8
configs/xilinx-ppc405-generic_defconfig
View File

@ -7,3 +7,11 @@ CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_MALLOC_SIMPLE=y
CONFIG_XILINX_UARTLITE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_EMBED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"

8
configs/xilinx-ppc405-generic_flash_defconfig
View File

@ -1,8 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

16
configs/xilinx-ppc440-generic_defconfig
View File

@ -3,7 +3,15 @@ CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
CONFIG_SYS_PROMPT="board:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_MALLOC_SIMPLE=y
CONFIG_XILINX_UARTLITE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_EMBED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NETCONSOLE=y

8
configs/xilinx-ppc440-generic_flash_defconfig
View File

@ -1,8 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set

1
configs/zynq_microzed_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y

1
configs/zynq_picozed_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_PICOZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SPL=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y

2
configs/zynq_zc702_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@ -12,6 +13,7 @@ CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y

2
configs/zynq_zc706_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@ -13,6 +14,7 @@ CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y

2
configs/zynq_zc770_xm010_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@ -14,6 +15,7 @@ CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y

1
configs/zynq_zc770_xm011_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y

1
configs/zynq_zc770_xm012_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y

3
configs/zynq_zc770_xm013_defconfig
View File

@ -7,10 +7,13 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_ZYNQ_GEM=y

2
configs/zynq_zed_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@ -13,6 +14,7 @@ CONFIG_CMD_GPIO=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y

5
configs/zynq_zybo_defconfig
View File

@ -6,17 +6,18 @@ CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_QSPI=y

13
doc/device-tree-bindings/serial/xilinx_uartlite.txt Normal file
View File

@ -0,0 +1,13 @@
Binding for Xilinx Uartlite Controller
Required properties:
- compatible : should be "xlnx,xps-uartlite-1.00.a", or "xlnx,opb-uartlite-1.00.b"
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
Example:
serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a";
interrupts = <1 0>;
reg = <0x40600000 0x10000>;
};

1
doc/driver-model/serial-howto.txt
View File

@ -15,7 +15,6 @@ is time for maintainers to start converting over the remaining serial drivers:
serial_pxa.c
serial_s3c24x0.c
serial_sa1100.c
serial_xuartlite.c
usbtty.c
You should complete this by the end of January 2016.

4
drivers/fpga/xilinx.c
View File

@ -75,8 +75,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
buffer[i] = *dataptr++;
if (xdesc->name) {
i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
if (i) {
i = (ulong)strstr(buffer, xdesc->name);
if (!i) {
printf("%s: Wrong bitstream ID for this device\n",
__func__);
printf("%s: Bitstream ID %s, current device ID %d/%s\n",

2
drivers/hwmon/adt7460.c
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/

4
drivers/mmc/sdhci.c
View File

@ -530,6 +530,10 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
if (caps & SDHCI_CAN_DO_8BIT)
host->cfg.host_caps |= MMC_MODE_8BIT;
}
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
if (host->host_caps)
host->cfg.host_caps |= host->host_caps;

12
drivers/mmc/zynq_sdhci.c
View File

@ -13,6 +13,10 @@
#include <malloc.h>
#include <sdhci.h>
#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
#endif
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@ -20,9 +24,15 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
upriv->mmc = host->mmc;

16
drivers/net/Kconfig
View File

@ -102,6 +102,22 @@ config PCH_GBE
This MAC is present in Intel Platform Controller Hub EG20T. It
supports 10/100/1000 Mbps operation.
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
select MII
bool "Xilinx AXI Ethernet"
help
This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
config XILINX_EMACLITE
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB
select MII
bool "Xilinx Ethernetlite"
help
This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
config ZYNQ_GEM
depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
select PHYLIB

3
drivers/net/phy/ti.c
View File

@ -41,6 +41,8 @@
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
#define DP83867_MDI_CROSSOVER 5
#define DP83867_MDI_CROSSOVER_AUTO 2
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
@ -149,6 +151,7 @@ static int dp83867_config(struct phy_device *phydev)
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
return ret;

314
drivers/net/xilinx_axi_emac.c
View File

@ -8,15 +8,14 @@
#include <config.h>
#include <common.h>
#include <dm.h>
#include <net.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#if !defined(CONFIG_PHYLIB)
# error AXI_ETHERNET requires PHYLIB
#endif
DECLARE_GLOBAL_DATA_PTR;
/* Link setup */
#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
@ -86,7 +85,8 @@ struct axidma_priv {
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
int phyaddr;
struct axi_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
struct mii_dev *bus;
};
@ -147,9 +147,8 @@ struct axi_regs {
*/
#define PHY_DETECT_MASK 0x1808
static inline int mdio_wait(struct eth_device *dev)
static inline int mdio_wait(struct axi_regs *regs)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 timeout = 200;
/* Wait till MDIO interface is ready to accept a new transaction. */
@ -165,13 +164,13 @@ static inline int mdio_wait(struct eth_device *dev)
return 0;
}
static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
u16 *val)
static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
u16 *val)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct axi_regs *regs = priv->iobase;
u32 mdioctrlreg = 0;
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
@ -183,7 +182,7 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
out_be32(&regs->mdio_mcr, mdioctrlreg);
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
/* Read data */
@ -191,13 +190,13 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
return 0;
}
static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
u32 data)
static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
u32 data)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct axi_regs *regs = priv->iobase;
u32 mdioctrlreg = 0;
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
@ -212,19 +211,18 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
out_be32(&regs->mdio_mcr, mdioctrlreg);
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
return 0;
}
/* Setting axi emac and phy to proper setting */
static int setup_phy(struct eth_device *dev)
static int axiemac_phy_init(struct udevice *dev)
{
u16 phyreg;
u32 i, speed, emmc_reg, ret;
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 i, ret;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev;
u32 supported = SUPPORTED_10baseT_Half |
@ -234,16 +232,19 @@ static int setup_phy(struct eth_device *dev)
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
/* Set default MDIO divisor */
out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
if (priv->phyaddr == -1) {
/* Detect the PHY address */
for (i = 31; i >= 0; i--) {
ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
if (!ret && (phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
priv->phyaddr = i;
debug("axiemac: Found valid phy address, %x\n",
phyreg);
i);
break;
}
}
@ -256,6 +257,18 @@ static int setup_phy(struct eth_device *dev)
phydev->advertising = phydev->supported;
priv->phydev = phydev;
phy_config(phydev);
return 0;
}
/* Setting axi emac and phy to proper setting */
static int setup_phy(struct udevice *dev)
{
u32 speed, emmc_reg;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev = priv->phydev;
if (phy_startup(phydev)) {
printf("axiemac: could not initialize PHY %s\n",
phydev->dev->name);
@ -299,9 +312,9 @@ static int setup_phy(struct eth_device *dev)
}
/* STOP DMA transfers */
static void axiemac_halt(struct eth_device *dev)
static void axiemac_stop(struct udevice *dev)
{
struct axidma_priv *priv = dev->priv;
struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Stop the hardware */
@ -316,9 +329,9 @@ static void axiemac_halt(struct eth_device *dev)
debug("axiemac: Halted\n");
}
static int axi_ethernet_init(struct eth_device *dev)
static int axi_ethernet_init(struct axidma_priv *priv)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct axi_regs *regs = priv->iobase;
u32 timeout = 200;
/*
@ -359,25 +372,26 @@ static int axi_ethernet_init(struct eth_device *dev)
return 0;
}
static int axiemac_setup_mac(struct eth_device *dev)
static int axiemac_write_hwaddr(struct udevice *dev)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
/* Set the MAC address */
int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
out_be32(&regs->uaw0, val);
val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
out_be32(&regs->uaw1, val);
return 0;
}
/* Reset DMA engine */
static void axi_dma_init(struct eth_device *dev)
static void axi_dma_init(struct axidma_priv *priv)
{
struct axidma_priv *priv = dev->priv;
u32 timeout = 500;
/* Reset the engine so the hardware starts from a known state */
@ -388,9 +402,9 @@ static void axi_dma_init(struct eth_device *dev)
while (timeout--) {
/* Check transmit/receive channel */
/* Reset is done when the reset bit is low */
if (!(in_be32(&priv->dmatx->control) |
if (!((in_be32(&priv->dmatx->control) |
in_be32(&priv->dmarx->control))
& XAXIDMA_CR_RESET_MASK) {
& XAXIDMA_CR_RESET_MASK)) {
break;
}
}
@ -398,10 +412,10 @@ static void axi_dma_init(struct eth_device *dev)
printf("%s: Timeout\n", __func__);
}
static int axiemac_init(struct eth_device *dev, bd_t * bis)
static int axiemac_start(struct udevice *dev)
{
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
u32 temp;
debug("axiemac: Init started\n");
@ -411,10 +425,10 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis)
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
axi_dma_init(dev);
axi_dma_init(priv);
/* Initialize AxiEthernet hardware. */
if (axi_ethernet_init(dev))
if (axi_ethernet_init(priv))
return -1;
/* Disable all RX interrupts before RxBD space setup */
@ -452,7 +466,7 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis)
/* PHY setup */
if (!setup_phy(dev)) {
axiemac_halt(dev);
axiemac_stop(dev);
return -1;
}
@ -460,9 +474,9 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis)
return 0;
}
static int axiemac_send(struct eth_device *dev, void *ptr, int len)
static int axiemac_send(struct udevice *dev, void *ptr, int len)
{
struct axidma_priv *priv = dev->priv;
struct axidma_priv *priv = dev_get_priv(dev);
u32 timeout;
if (len > PKTSIZE_ALIGN)
@ -498,8 +512,8 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len)
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
timeout = 200;
while (timeout && (!in_be32(&priv->dmatx->status) &
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
while (timeout && (!(in_be32(&priv->dmatx->status) &
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
timeout--;
udelay(1);
}
@ -512,10 +526,9 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len)
return 0;
}
static int isrxready(struct eth_device *dev)
static int isrxready(struct axidma_priv *priv)
{
u32 status;
struct axidma_priv *priv = dev->priv;
/* Read pending interrupts */
status = in_be32(&priv->dmarx->status);
@ -533,15 +546,15 @@ static int isrxready(struct eth_device *dev)
return 0;
}
static int axiemac_recv(struct eth_device *dev)
static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
{
u32 length;
struct axidma_priv *priv = dev->priv;
struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Wait for an incoming packet */
if (!isrxready(dev))
return 0;
if (!isrxready(priv))
return -1;
debug("axiemac: RX data ready\n");
@ -554,9 +567,14 @@ static int axiemac_recv(struct eth_device *dev)
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
/* Pass the received frame up for processing */
if (length)
net_process_received_packet(rxframe, length);
*packetp = rxframe;
return length;
}
static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct axidma_priv *priv = dev_get_priv(dev);
#ifdef DEBUG
/* It is useful to clear buffer to be sure that it is consistent */
@ -581,76 +599,128 @@ static int axiemac_recv(struct eth_device *dev)
debug("axiemac: RX completed, framelength = %d\n", length);
return length;
}
static int axiemac_miiphy_read(const char *devname, uchar addr,
uchar reg, ushort *val)
{
struct eth_device *dev = eth_get_dev();
u32 ret;
ret = phyread(dev, addr, reg, val);
debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
return ret;
}
static int axiemac_miiphy_write(const char *devname, uchar addr,
uchar reg, ushort val)
{
struct eth_device *dev = eth_get_dev();
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
return phywrite(dev, addr, reg, val);
}
static int axiemac_bus_reset(struct mii_dev *bus)
{
debug("axiemac: Bus reset\n");
return 0;
}
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr)
static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
int devad, int reg)
{
struct eth_device *dev;
struct axidma_priv *priv;
int ret;
u16 value;
dev = calloc(1, sizeof(struct eth_device));
if (dev == NULL)
return -1;
dev->priv = calloc(1, sizeof(struct axidma_priv));
if (dev->priv == NULL) {
free(dev);
return -1;
}
priv = dev->priv;
sprintf(dev->name, "aximac.%lx", base_addr);
dev->iobase = base_addr;
priv->dmatx = (struct axidma_reg *)dma_addr;
/* RX channel offset is 0x30 */
priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
dev->init = axiemac_init;
dev->halt = axiemac_halt;
dev->send = axiemac_send;
dev->recv = axiemac_recv;
dev->write_hwaddr = axiemac_setup_mac;
#ifdef CONFIG_PHY_ADDR
priv->phyaddr = CONFIG_PHY_ADDR;
#else
priv->phyaddr = -1;
#endif
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
priv->bus = miiphy_get_dev_by_name(dev->name);
priv->bus->reset = axiemac_bus_reset;
#endif
return 1;
ret = phyread(bus->priv, addr, reg, &value);
debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
value, ret);
return value;
}
static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
return phywrite(bus->priv, addr, reg, value);
}
static int axi_emac_probe(struct udevice *dev)
{
struct axidma_priv *priv = dev_get_priv(dev);
int ret;
priv->bus = mdio_alloc();
priv->bus->read = axiemac_miiphy_read;
priv->bus->write = axiemac_miiphy_write;
priv->bus->priv = priv;
strcpy(priv->bus->name, "axi_emac");
ret = mdio_register(priv->bus);
if (ret)
return ret;
axiemac_phy_init(dev);
return 0;
}
static int axi_emac_remove(struct udevice *dev)
{
struct axidma_priv *priv = dev_get_priv(dev);
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
return 0;
}
static const struct eth_ops axi_emac_ops = {
.start = axiemac_start,
.send = axiemac_send,
.recv = axiemac_recv,
.free_pkt = axiemac_free_pkt,
.stop = axiemac_stop,
.write_hwaddr = axiemac_write_hwaddr,
};
static int axi_emac_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct axidma_priv *priv = dev_get_priv(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct axi_regs *)pdata->iobase;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"axistream-connected");
if (offset <= 0) {
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
offset, "reg", 0);
if (!priv->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
}
/* RX channel offset is 0x30 */
priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static const struct udevice_id axi_emac_ids[] = {
{ .compatible = "xlnx,axi-ethernet-1.00.a" },
{ }
};
U_BOOT_DRIVER(axi_emac) = {
.name = "axi_emac",
.id = UCLASS_ETH,
.of_match = axi_emac_ids,
.ofdata_to_platdata = axi_emac_ofdata_to_platdata,
.probe = axi_emac_probe,
.remove = axi_emac_remove,
.ops = &axi_emac_ops,
.priv_auto_alloc_size = sizeof(struct axidma_priv),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};

632
drivers/net/xilinx_emaclite.c
View File

@ -10,27 +10,25 @@
#include <common.h>
#include <net.h>
#include <config.h>
#include <dm.h>
#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
#include <asm-generic/errno.h>
#include <linux/kernel.h>
#undef DEBUG
DECLARE_GLOBAL_DATA_PTR;
#define ENET_ADDR_LENGTH 6
/* EmacLite constants */
#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
#define XEL_TSR_OFFSET 0x07FC /* Tx status */
#define XEL_RSR_OFFSET 0x17FC /* Rx status */
#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
#define ETH_FCS_LEN 4 /* Octets in the FCS */
/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK 0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
@ -46,14 +44,56 @@
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
struct xemaclite {
u32 nexttxbuffertouse; /* Next TX buffer to write to */
u32 nextrxbuffertouse; /* Next RX buffer to read from */
u32 txpp; /* TX ping pong buffer */
u32 rxpp; /* RX ping pong buffer */
/* MDIO Address Register Bit Masks */
#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
#define XEL_MDIOADDR_PHYADR_SHIFT 5
#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
/* MDIO Write Data Register Bit Masks */
#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
/* MDIO Read Data Register Bit Masks */
#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
/* MDIO Control Register Bit Masks */
#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
struct emaclite_regs {
u32 tx_ping; /* 0x0 - TX Ping buffer */
u32 reserved1[504];
u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
u32 mdiord;/* 0x7ec - MDIO Read Data Register */
u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
u32 tx_ping_tsr; /* 0x7fc - Tx status */
u32 tx_pong; /* 0x800 - TX Pong buffer */
u32 reserved2[508];
u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
u32 reserved3; /* 0xff8 */
u32 tx_pong_tsr; /* 0xffc - Tx status */
u32 rx_ping; /* 0x1000 - Receive Buffer */
u32 reserved4[510];
u32 rx_ping_rsr; /* 0x17fc - Rx status */
u32 rx_pong; /* 0x1800 - Receive Buffer */
u32 reserved5[510];
u32 rx_pong_rsr; /* 0x1ffc - Rx status */
};
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
struct xemaclite {
bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
u32 txpp; /* TX ping pong buffer */
u32 rxpp; /* RX ping pong buffer */
int phyaddr;
struct emaclite_regs *regs;
struct phy_device *phydev;
struct mii_dev *bus;
};
static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
@ -81,7 +121,7 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
*to8ptr++ = *from8ptr++;
}
static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
{
u32 i;
u32 alignbuffer;
@ -107,42 +147,206 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
*to32ptr++ = alignbuffer;
}
static void emaclite_halt(struct eth_device *dev)
static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
bool set, unsigned int timeout)
{
debug("eth_halt\n");
u32 val;
unsigned long start = get_timer(0);
while (1) {
val = readl(reg);
if (!set)
val = ~val;
if ((val & mask) == mask)
return 0;
if (get_timer(start) > timeout)
break;
if (ctrlc()) {
puts("Abort\n");
return -EINTR;
}
udelay(1);
}
debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
func, reg, mask, set);
return -ETIMEDOUT;
}
static int emaclite_init(struct eth_device *dev, bd_t *bis)
static int mdio_wait(struct emaclite_regs *regs)
{
struct xemaclite *emaclite = dev->priv;
return wait_for_bit(__func__, &regs->mdioctrl,
XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
}
static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
u16 *data)
{
struct emaclite_regs *regs = emaclite->regs;
if (mdio_wait(regs))
return 1;
u32 ctrl_reg = in_be32(&regs->mdioctrl);
out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
if (mdio_wait(regs))
return 1;
/* Read data */
*data = in_be32(&regs->mdiord);
return 0;
}
static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
u16 data)
{
struct emaclite_regs *regs = emaclite->regs;
if (mdio_wait(regs))
return 1;
/*
* Write the PHY address, register number and clear the OP bit in the
* MDIO Address register and then write the value into the MDIO Write
* Data register. Finally, set the Status bit in the MDIO Control
* register to start a MDIO write transaction.
*/
u32 ctrl_reg = in_be32(&regs->mdioctrl);
out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
out_be32(&regs->mdiowr, data);
out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
if (mdio_wait(regs))
return 1;
return 0;
}
static void emaclite_stop(struct udevice *dev)
{
debug("eth_stop\n");
}
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
/* Mask used to verify certain PHY features (or register contents)
* in the register above:
* 0x1000: 10Mbps full duplex support
* 0x0800: 10Mbps half duplex support
* 0x0008: Auto-negotiation support
*/
#define PHY_DETECT_MASK 0x1808
static int setup_phy(struct udevice *dev)
{
int i;
u16 phyreg;
struct xemaclite *emaclite = dev_get_priv(dev);
struct phy_device *phydev;
u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full;
if (emaclite->phyaddr != -1) {
phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
debug("Default phy address %d is valid\n",
emaclite->phyaddr);
} else {
debug("PHY address is not setup correctly %d\n",
emaclite->phyaddr);
emaclite->phyaddr = -1;
}
}
if (emaclite->phyaddr == -1) {
/* detect the PHY address */
for (i = 31; i >= 0; i--) {
phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
emaclite->phyaddr = i;
debug("emaclite: Found valid phy address, %d\n",
i);
break;
}
}
}
/* interface - look at tsec */
phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
PHY_INTERFACE_MODE_MII);
/*
* Phy can support 1000baseT but device NOT that's why phydev->supported
* must be setup for 1000baseT. phydev->advertising setups what speeds
* will be used for autonegotiation where 1000baseT must be disabled.
*/
phydev->supported = supported | SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
phydev->advertising = supported;
emaclite->phydev = phydev;
phy_config(phydev);
phy_startup(phydev);
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
return 0;
}
/* Do not setup anything */
return 1;
}
static int emaclite_start(struct udevice *dev)
{
struct xemaclite *emaclite = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emaclite_regs *regs = emaclite->regs;
debug("EmacLite Initialization Started\n");
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
out_be32(&regs->tx_ping_tsr, 0);
/* Copy MAC address */
xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
ENET_ADDR_LENGTH);
/* Set the length */
out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
while ((in_be32 (&regs->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_TSR_PROG_MAC_ADDR);
while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
out_be32(&regs->tx_pong_tsr, 0);
xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
ENET_ADDR_LENGTH);
out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
while ((in_be32(&regs->tx_pong_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
@ -150,52 +354,48 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
if (emaclite->rxpp)
out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_RSR_RECV_IE_MASK);
out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
if (!setup_phy(dev))
return -1;
debug("EmacLite Initialization complete\n");
return 0;
}
static int xemaclite_txbufferavailable(struct eth_device *dev)
static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
{
u32 reg;
u32 txpingbusy;
u32 txpongbusy;
struct xemaclite *emaclite = dev->priv;
u32 tmp;
struct emaclite_regs *regs = emaclite->regs;
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
reg = in_be32 (dev->iobase +
emaclite->nexttxbuffertouse + 0);
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
tmp = ~in_be32(&regs->tx_ping_tsr);
if (emaclite->txpp)
tmp |= ~in_be32(&regs->tx_pong_tsr);
reg = in_be32 (dev->iobase +
(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
return !(txpingbusy && txpongbusy);
return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}
static int emaclite_send(struct eth_device *dev, void *ptr, int len)
static int emaclite_send(struct udevice *dev, void *ptr, int len)
{
u32 reg;
u32 baseaddress;
struct xemaclite *emaclite = dev->priv;
struct xemaclite *emaclite = dev_get_priv(dev);
struct emaclite_regs *regs = emaclite->regs;
u32 maxtry = 1000;
if (len > PKTSIZE)
len = PKTSIZE;
while (!xemaclite_txbufferavailable(dev) && maxtry) {
while (xemaclite_txbufferavailable(emaclite) && maxtry) {
udelay(10);
maxtry--;
}
@ -203,58 +403,40 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
out_be32(&regs->tx_ping_tsr, 0);
if (emaclite->txpp) {
out_be32 (dev->iobase + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
out_be32(&regs->tx_pong_tsr, 0);
}
return -1;
}
/* Determine the expected TX buffer address */
baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
if (emaclite->txpp)
emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
debug("Send packet from 0x%x\n", baseaddress);
reg = in_be32(&regs->tx_ping_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_ping buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
out_be32(&regs->tx_ping_tplr, len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
reg = in_be32(&regs->tx_ping_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
out_be32(&regs->tx_ping_tsr, reg);
return 0;
}
if (emaclite->txpp) {
/* Switch to second buffer */
baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
debug("Send packet from 0x%x\n", baseaddress);
reg = in_be32(&regs->tx_pong_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_pong buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
(XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
out_be32(&regs->tx_pong_tplr, len &
(XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO));
reg = in_be32(&regs->tx_pong_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
out_be32(&regs->tx_pong_tsr, reg);
return 0;
}
}
@ -263,130 +445,188 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)
return -1;
}
static int emaclite_recv(struct eth_device *dev)
static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
{
u32 length;
u32 reg;
u32 baseaddress;
u32 length, first_read, reg, attempt = 0;
void *addr, *ack;
struct xemaclite *emaclite = dev->priv;
struct emaclite_regs *regs = emaclite->regs;
struct ethernet_hdr *eth;
struct ip_udp_hdr *ip;
baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
debug("Testing data at address 0x%x\n", baseaddress);
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
if (emaclite->rxpp)
emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
} else {
if (!emaclite->rxpp) {
debug("No data was available - address 0x%x\n",
baseaddress);
return 0;
try_again:
if (!emaclite->use_rx_pong_buffer_next) {
reg = in_be32(&regs->rx_ping_rsr);
debug("Testing data at rx_ping\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_ping buffer\n");
addr = &regs->rx_ping;
ack = &regs->rx_ping_rsr;
} else {
baseaddress ^= XEL_BUFFER_OFFSET;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
if ((reg & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) {
debug("No data was available - address 0x%x\n",
baseaddress);
return 0;
}
debug("Data not found in rx_ping buffer\n");
/* Pong buffer is not available - return immediately */
if (!emaclite->rxpp)
return -1;
/* Try pong buffer if this is first attempt */
if (attempt++)
return -1;
emaclite->use_rx_pong_buffer_next =
!emaclite->use_rx_pong_buffer_next;
goto try_again;
}
} else {
reg = in_be32(&regs->rx_pong_rsr);
debug("Testing data at rx_pong\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_pong buffer\n");
addr = &regs->rx_pong;
ack = &regs->rx_pong_rsr;
} else {
debug("Data not found in rx_pong buffer\n");
/* Try ping buffer if this is first attempt */
if (attempt++)
return -1;
emaclite->use_rx_pong_buffer_next =
!emaclite->use_rx_pong_buffer_next;
goto try_again;
}
}
/* Get the length of the frame that arrived */
switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
0xFFFF0000 ) >> 16) {
case 0x806:
length = 42 + 20; /* FIXME size of ARP */
debug("ARP Packet\n");
break;
case 0x800:
length = 14 + 14 +
(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
0x10))) & 0xFFFF0000) >> 16);
/* FIXME size of IP packet */
debug ("IP Packet\n");
break;
default:
debug("Other Packet\n");
length = PKTSIZE;
break;
/* Read all bytes for ARP packet with 32bit alignment - 48bytes */
first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
xemaclite_alignedread(addr, etherrxbuff, first_read);
/* Detect real packet size */
eth = (struct ethernet_hdr *)etherrxbuff;
switch (ntohs(eth->et_protlen)) {
case PROT_ARP:
length = first_read;
debug("ARP Packet %x\n", length);
break;
case PROT_IP:
ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
length = ntohs(ip->ip_len);
length += ETHER_HDR_SIZE + ETH_FCS_LEN;
debug("IP Packet %x\n", length);
break;
default:
debug("Other Packet\n");
length = PKTSIZE;
break;
}
xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
etherrxbuff, length);
/* Read the rest of the packet which is longer then first read */
if (length != first_read)
xemaclite_alignedread(addr + first_read,
etherrxbuff + first_read,
length - first_read);
/* Acknowledge the frame */
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
reg = in_be32(ack);
reg &= ~XEL_RSR_RECV_DONE_MASK;
out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
out_be32(ack, reg);
debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
net_process_received_packet((uchar *)etherrxbuff, length);
debug("Packet receive from 0x%p, length %dB\n", addr, length);
*packetp = etherrxbuff;
return length;
}
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp)
static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
int devad, int reg)
{
struct eth_device *dev;
struct xemaclite *emaclite;
u32 ret;
u16 val = 0;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return -1;
emaclite = calloc(1, sizeof(struct xemaclite));
if (emaclite == NULL) {
free(dev);
return -1;
}
dev->priv = emaclite;
emaclite->txpp = txpp;
emaclite->rxpp = rxpp;
sprintf(dev->name, "Xelite.%lx", base_addr);
dev->iobase = base_addr;
dev->init = emaclite_init;
dev->halt = emaclite_halt;
dev->send = emaclite_send;
dev->recv = emaclite_recv;
eth_register(dev);
return 1;
ret = phyread(bus->priv, addr, reg, &val);
debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
return val;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int xilinx_emaclite_of_init(const void *blob)
static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
return phywrite(bus->priv, addr, reg, value);
}
static int emaclite_probe(struct udevice *dev)
{
struct xemaclite *emaclite = dev_get_priv(dev);
int ret;
emaclite->bus = mdio_alloc();
emaclite->bus->read = emaclite_miiphy_read;
emaclite->bus->write = emaclite_miiphy_write;
emaclite->bus->priv = emaclite;
strcpy(emaclite->bus->name, "emaclite");
ret = mdio_register(emaclite->bus);
if (ret)
return ret;
return 0;
}
static int emaclite_remove(struct udevice *dev)
{
struct xemaclite *emaclite = dev_get_priv(dev);
free(emaclite->phydev);
mdio_unregister(emaclite->bus);
mdio_free(emaclite->bus);
return 0;
}
static const struct eth_ops emaclite_ops = {
.start = emaclite_start,
.send = emaclite_send,
.recv = emaclite_recv,
.stop = emaclite_stop,
};
static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
u32 ret = 0;
u32 reg;
do {
offset = fdt_node_offset_by_compatible(blob, offset,
"xlnx,xps-ethernetlite-1.00.a");
if (offset != -1) {
reg = fdtdec_get_addr(blob, offset, "reg");
if (reg != FDT_ADDR_T_NONE) {
u32 rxpp = fdtdec_get_int(blob, offset,
"xlnx,rx-ping-pong", 0);
u32 txpp = fdtdec_get_int(blob, offset,
"xlnx,tx-ping-pong", 0);
ret |= xilinx_emaclite_initialize(NULL, reg,
txpp, rxpp);
} else {
debug("EMACLITE: Can't get base address\n");
return -1;
}
}
} while (offset != -1);
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
emaclite->regs = (struct emaclite_regs *)pdata->iobase;
return ret;
emaclite->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,tx-ping-pong", 0);
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
return 0;
}
#endif
static const struct udevice_id emaclite_ids[] = {
{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
{ }
};
U_BOOT_DRIVER(emaclite) = {
.name = "emaclite",
.id = UCLASS_ETH,
.of_match = emaclite_ids,
.ofdata_to_platdata = emaclite_ofdata_to_platdata,
.probe = emaclite_probe,
.remove = emaclite_remove,
.ops = &emaclite_ops,
.priv_auto_alloc_size = sizeof(struct xemaclite),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};

3
drivers/net/xilinx_ll_temac.c
View File

@ -303,7 +303,8 @@ int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf)
if (devinf->devname) {
strncpy(dev->name, devinf->devname, sizeof(dev->name));
} else {
snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr);
snprintf(dev->name, sizeof(dev->name), "ll_tem.%lx",
devinf->base_addr);
devinf->devname = dev->name;
}

4
drivers/net/zynq_gem.c
View File

@ -57,7 +57,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
#ifdef CONFIG_ARM64
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */
#else
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
#endif
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */

14
drivers/serial/Kconfig
View File

@ -112,6 +112,13 @@ config DEBUG_UART_S5P
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
config DEBUG_UART_UARTLITE
bool "Xilinx Uartlite"
help
Select this to enable a debug UART using the serial_uartlite driver.
You will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
@ -271,4 +278,11 @@ config UNIPHIER_SERIAL
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
config XILINX_UARTLITE
bool "Xilinx Uarlite support"
depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
help
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.
endmenu

196
drivers/serial/serial_xuartlite.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2008-2011 Michal Simek <monstr@monstr.eu>
* (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
@ -10,13 +10,17 @@
#include <config.h>
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
DECLARE_GLOBAL_DATA_PTR;
#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
#define ULITE_CONTROL_RST_TX 0x01
#define ULITE_CONTROL_RST_RX 0x02
@ -28,135 +32,111 @@ struct uartlite {
unsigned int control;
};
static struct uartlite *userial_ports[4] = {
#ifdef XILINX_UARTLITE_BASEADDR
[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
#endif
#ifdef XILINX_UARTLITE_BASEADDR1
[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
#endif
#ifdef XILINX_UARTLITE_BASEADDR2
[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
#endif
#ifdef XILINX_UARTLITE_BASEADDR3
[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
#endif
struct uartlite_platdata {
struct uartlite *regs;
};
static void uartlite_serial_putc(const char c, const int port)
static int uartlite_serial_putc(struct udevice *dev, const char ch)
{
struct uartlite *regs = userial_ports[port];
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
if (c == '\n')
uartlite_serial_putc('\r', port);
if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
return -EAGAIN;
while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
;
out_be32(&regs->tx_fifo, c & 0xff);
out_be32(&regs->tx_fifo, ch & 0xff);
return 0;
}
static void uartlite_serial_puts(const char *s, const int port)
static int uartlite_serial_getc(struct udevice *dev)
{
while (*s)
uartlite_serial_putc(*s++, port);
}
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
static int uartlite_serial_getc(const int port)
{
struct uartlite *regs = userial_ports[port];
if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
return -EAGAIN;
while (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
;
return in_be32(&regs->rx_fifo) & 0xff;
}
static int uartlite_serial_tstc(const int port)
static int uartlite_serial_pending(struct udevice *dev, bool input)
{
struct uartlite *regs = userial_ports[port];
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
if (input)
return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
}
static int uartlite_serial_init(const int port)
static int uartlite_serial_probe(struct udevice *dev)
{
struct uartlite *regs = userial_ports[port];
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
if (regs) {
out_be32(&regs->control, 0);
out_be32(&regs->control,
ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
in_be32(&regs->control);
return 0;
}
out_be32(&regs->control, 0);
out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
in_be32(&regs->control);
return -1;
return 0;
}
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
static int userial##port##_init(void) \
{ return uartlite_serial_init(port); } \
static void userial##port##_setbrg(void) {} \
static int userial##port##_getc(void) \
{ return uartlite_serial_getc(port); } \
static int userial##port##_tstc(void) \
{ return uartlite_serial_tstc(port); } \
static void userial##port##_putc(const char c) \
{ uartlite_serial_putc(c, port); } \
static void userial##port##_puts(const char *s) \
{ uartlite_serial_puts(s, port); }
/* Serial device descriptor */
#define INIT_ESERIAL_STRUCTURE(port, __name) { \
.name = __name, \
.start = userial##port##_init, \
.stop = NULL, \
.setbrg = userial##port##_setbrg, \
.getc = userial##port##_getc, \
.tstc = userial##port##_tstc, \
.putc = userial##port##_putc, \
.puts = userial##port##_puts, \
}
DECLARE_ESERIAL_FUNCTIONS(0);
struct serial_device uartlite_serial0_device =
INIT_ESERIAL_STRUCTURE(0, "ttyUL0");
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device uartlite_serial1_device =
INIT_ESERIAL_STRUCTURE(1, "ttyUL1");
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device uartlite_serial2_device =
INIT_ESERIAL_STRUCTURE(2, "ttyUL2");
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device uartlite_serial3_device =
INIT_ESERIAL_STRUCTURE(3, "ttyUL3");
__weak struct serial_device *default_serial_console(void)
static int uartlite_serial_ofdata_to_platdata(struct udevice *dev)
{
if (userial_ports[0])
return &uartlite_serial0_device;
if (userial_ports[1])
return &uartlite_serial1_device;
if (userial_ports[2])
return &uartlite_serial2_device;
if (userial_ports[3])
return &uartlite_serial3_device;
struct uartlite_platdata *plat = dev_get_platdata(dev);
return NULL;
plat->regs = (struct uartlite *)dev_get_addr(dev);
return 0;
}
void uartlite_serial_initialize(void)
static const struct dm_serial_ops uartlite_serial_ops = {
.putc = uartlite_serial_putc,
.pending = uartlite_serial_pending,
.getc = uartlite_serial_getc,
};
static const struct udevice_id uartlite_serial_ids[] = {
{ .compatible = "xlnx,opb-uartlite-1.00.b", },
{ .compatible = "xlnx,xps-uartlite-1.00.a" },
{ }
};
U_BOOT_DRIVER(serial_uartlite) = {
.name = "serial_uartlite",
.id = UCLASS_SERIAL,
.of_match = uartlite_serial_ids,
.ofdata_to_platdata = uartlite_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct uartlite_platdata),
.probe = uartlite_serial_probe,
.ops = &uartlite_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_UARTLITE
#include <debug_uart.h>
static inline void _debug_uart_init(void)
{
#ifdef XILINX_UARTLITE_BASEADDR
serial_register(&uartlite_serial0_device);
#endif /* XILINX_UARTLITE_BASEADDR */
#ifdef XILINX_UARTLITE_BASEADDR1
serial_register(&uartlite_serial1_device);
#endif /* XILINX_UARTLITE_BASEADDR1 */
#ifdef XILINX_UARTLITE_BASEADDR2
serial_register(&uartlite_serial2_device);
#endif /* XILINX_UARTLITE_BASEADDR2 */
#ifdef XILINX_UARTLITE_BASEADDR3
serial_register(&uartlite_serial3_device);
#endif /* XILINX_UARTLITE_BASEADDR3 */
struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
out_be32(&regs->control, 0);
out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
in_be32(&regs->control);
}
static inline void _debug_uart_putc(int ch)
{
struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
;
out_be32(&regs->tx_fifo, ch & 0xff);
}
DEBUG_UART_FUNCS
#endif

8
drivers/serial/serial_zynq.c
View File

@ -156,13 +156,8 @@ static int zynq_serial_pending(struct udevice *dev, bool input)
static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct uart_zynq *)addr;
priv->regs = (struct uart_zynq *)dev_get_addr(dev);
return 0;
}
@ -177,6 +172,7 @@ static const struct dm_serial_ops zynq_serial_ops = {
static const struct udevice_id zynq_serial_ids[] = {
{ .compatible = "xlnx,xuartps" },
{ .compatible = "cdns,uart-r1p8" },
{ .compatible = "cdns,uart-r1p12" },
{ }
};

50
include/configs/fx12mm.h
View File

@ -1,50 +0,0 @@
/*
* (C) Copyright 2008
*
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com
*
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
* see http://www.em.avnet.com
*/
#ifndef __CONFIG_FX12_H
#define __CONFIG_FX12_H
#include "../board/avnet/fx12mm/xparameters.h"
/* cmd config */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
/* sdram */
#define CONFIG_SYS_SDRAM_SIZE_MB 64
/* environment */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_SYS_ENV_OFFSET 0xA0000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
#define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (4*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define MTDIDS_DEFAULT "nor0=fx12mm-flash"
#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)"
#include "configs/xilinx-ppc405.h"
#endif /* __CONFIG_H */

74
include/configs/microblaze-generic.h
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@ -32,54 +32,20 @@
#endif
/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
# define CONFIG_SYS_NS16550_REG_SIZE -4
# else
# define CONFIG_SYS_NS16550_REG_SIZE 4
# endif
# define CONFIG_CONS_INDEX 1
# define CONFIG_SYS_NS16550_COM1 \
((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG "console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif
/* setting reset address */
/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
# define CONFIG_XILINX_EMACLITE 1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC 1
# define CONFIG_SYS_ENET
#endif
#undef ET_DEBUG
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
#define CONFIG_BOARD_LATE_INIT
/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
@ -103,13 +69,6 @@
# endif
#endif
#if !defined(CONFIG_OF_CONTROL) || \
(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
/* ddr sdram - main memory */
# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
#endif
#define CONFIG_SYS_MALLOC_LEN 0xC0000
/* Stack location before relocation */
@ -198,16 +157,6 @@
#endif /* !SPIFLASH */
#endif /* !FLASH */
/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif
#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
@ -245,17 +194,6 @@
# undef CONFIG_CMD_CACHE
#endif
#ifdef CONFIG_SYS_ENET
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif
#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif
#if defined(FLASH)
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
@ -315,7 +253,7 @@
#define CONFIG_SYS_MAXARGS 15
#define CONFIG_SYS_LONGHELP
/* default load address */
#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
#define CONFIG_SYS_LOAD_ADDR 0
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS "root=romfs"
@ -342,15 +280,10 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/* Enable flat device tree support */
#define CONFIG_LMB 1
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
#if defined(CONFIG_XILINX_AXIEMAC)
@ -358,20 +291,19 @@
# define CONFIG_CMD_MII 1
# define CONFIG_PHY_GIGE 1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
# define CONFIG_PHYLIB 1
# define CONFIG_PHY_ATHEROS 1
# define CONFIG_PHY_BROADCOM 1
# define CONFIG_PHY_DAVICOM 1
# define CONFIG_PHY_LXT 1
# define CONFIG_PHY_MARVELL 1
# define CONFIG_PHY_MICREL 1
# define CONFIG_PHY_MICREL_KSZ9021
# define CONFIG_PHY_NATSEMI 1
# define CONFIG_PHY_REALTEK 1
# define CONFIG_PHY_VITESSE 1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif
/* SPL part */

38
include/configs/ml507.h
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@ -1,38 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/xilinx/ml507/xparameters.h"
/*Mem Map*/
#define CONFIG_SYS_SDRAM_SIZE_MB 256
/*Env*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x340000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 259
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

38
include/configs/v5fx30teval.h
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@ -1,38 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/avnet/v5fx30teval/xparameters.h"
/*Mem Map*/
#define CONFIG_SYS_SDRAM_SIZE_MB 64
/*Env*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x1A0000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (16*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 131
#define MTDIDS_DEFAULT "nor0=v5fx30t-flash"
#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */

22
include/configs/xilinx-ppc.h
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
@ -101,22 +101,10 @@
#define CONFIG_SYS_NO_FLASH
#endif
/* serial communication */
#ifdef XPAR_UARTLITE_0_BASEADDR
#define CONFIG_XILINX_UARTLITE
#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#else
#ifdef XPAR_UARTNS550_0_BASEADDR
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR
#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ
#define CONFIG_OF_LIBFDT 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 }
#endif
#endif
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#endif /* __CONFIG_H */

19
include/configs/xilinx-ppc405-generic.h
View File

@ -1,7 +1,7 @@
/*
*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
@ -14,6 +14,9 @@
#include "../board/xilinx/ppc405-generic/xparameters.h"
#define CONFIG_405 1
#define CONFIG_XILINX_405 1
/* sdram */
#define CONFIG_SYS_SDRAM_SIZE_MB 256
@ -26,16 +29,16 @@
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
#define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/
#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CONFIG_SYS_FLASH_SIZE (128*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define MTDIDS_DEFAULT "nor0=ppc405-flash"
#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)"
#define MTDIDS_DEFAULT "nor0=flash"
#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)"
#include <configs/xilinx-ppc405.h>
#include <configs/xilinx-ppc.h>
#endif /* __CONFIG_H */

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